Cirrus Logic EP93xx User Manual

EP93XX

ARM®9 Embedded Processor Family

EP93xx

User’s Guide

http://www.cirrus.com

DS785UM1

EP93xx User’s Guide

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com

Cirrus Logic, Inc. and its sub si di ari es ( “Ci rrus”) believe that the inform at ion contained in this document i s accurate and reliable. However, the information is subject to change without not ice and is provi ded “AS IS” wi thout warranty of an y kind (exp ress or implied). Customer s are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at th e time of order acknowledg ment, includ ing those pert aining to warrant y, patent inf ringement, and limitation of liability. No respons ibility is assumed by Cirrus f or the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only f o r use wi thi n your organization with respect to Cirrus integr ated circuits or ot her products of Cir rus. This consent does not extend to other copy ing such as copying for ge neral distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICO NDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APP LICATIONS , PRODUCTS SURGICALLY IMP LANTE D INTO THE BODY, LIFE SUP PORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICE S). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD T O BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM ER'S CUSTOMER USES OR PE RMITS THE USE OF CIRRU S PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE , TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYE ES, DISTRIBUTORS AND OTHER AGENTS F ROM ANY AND A LL LIABILITY, INCLUDING ATTORNEYS ' FEES AND COS TS, THAT MAY RESU LT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Log ic logo designs are tradema rks of Cirrus Logic, Inc. Al l other brand and pr oduct names in this document may be trademarks or service marks of their respective owners.

Microsoft, Windows, and Windows CE are registered trademarks of Microsoft Corporation. Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola is a registered trademark of Motorola, Inc. LINUX is a registered trademark of Linus Torvalds. ARM and Thumb are registered trademarks of ARM Limited Intel is a registered trademark of Intel Corporation Hewlett-Packard is a registered trademark of Hewlett-Packard Corporation. Compaq is a regis t e red trademark of BV, a private Limited Liability Company in the Netherlands.

EP93xx User’s Guide

Chapter Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiv

Chapter Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii

Preface................................................................................................................... P-1

P.1 About the EP93xx User’s Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P-1

P.2 Related Documents from Cirrus Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P-3

P.3 Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P-3

P.4 Notational Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P-3

P.5 Register Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P-4

Chapter 1. Introduction.........................................................................................1-1

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

1.2 EP93xx Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

1.3 EP93xx Processor Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

1.4 EP93xx Processor Highlights. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

1.4.1 High-Performance ARM920T Core .................................................................................1-7

1.4.2 MaverickCrunch

1.4.3 MaverickKey

1.4.4 Integrated Multi-Port USB 2.0 Full Speed Hosts with Transceivers ................................1-8

1.4.5 Integrated Ethernet MAC Reduces BOM Costs ........................................ ...... ....... .........1-9

1.4.6 8x8 Keypad Interface Reduces BOM Costs....................................................................1-9

1.4.7 Multiple Booting Mechanisms Increase Flexibility...........................................................1-9

1.4.8 Abundant General Purpose I/Os Build Flexible Systems ................................................1-9

1.4.9 General-Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) ...........................1-9

1.4.10 12-Bit Analog-to-Digital Converter (ADC) Provides an Integrated

Touch-Screen Interface or General ADC Functionality..........................................................1-10

1.4.11 Raster Analog / LCD Controller...................................................................................1-10

1.4.12 Graphics Accelerator...................................................................................................1-10

1.4.13 PCMCIA Interface........................................................................................................1-10

™

Co-processor for Ultra-Fast Math Processing....................................1-7

™

Unique ID Secures Digital Content in OEM Designs ..............................1-8

Chapter 2. ARM920T Core and Advanced High-Speed Bus (AHB)...................2-1

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

2.2 Overview: ARM920T Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

2.2.1 Features ..........................................................................................................................2-1

2.2.2 Block Diagram .................................................................................................................2-2

2.2.3 Operations.......................................................................................................................2-2

2.2.3.1 ARM9TDMI Core ...........................................................................................2-3

2.2.3.2 Memory Management Unit ............................................................................2-4

2.2.3.3 Cache and Write Buffer .................................................................................2-5

2.2.4 Co-processor Interface....................................................................................................2-6

2.2.5 AMBA AHB Bus Interface Overview................................................................................2-6

2.2.6 AHB Implementation Details............................................................................................2-7

2.2.7 Memory and Bus Access Errors......................................................................................2-9

2.2.8 Bus Arbitration.................................................................................................................2-9

2.2.8.1 Main AHB Bus Arbiter..................................................................................2-10

2.2.8.2 SDRAM Slave Arbiter..................................................................................2-11

2.2.8.3 EBI Bus Arbiter............................................................................................2-11

2.3 AHB Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11

2.3.1 AHB Slave .....................................................................................................................2-11

EP93xx User’s Guide

2.3.2 AHB-to-APB Bridge.......................................................................................................2-12

2.3.2.1 Function and Operation of the AHB-to-APB Bridge.....................................2-12

2.3.3 APB Slave .....................................................................................................................2-13

2.3.4 Register Definitions .......................................................................................................2-13

2.3.5 Memory Map..................................................................................................................2-16

2.3.6 Internal Register Map ....................................................................................................2-17

2.3.6.1 Memory Access Rules.................................................................................2-17

Chapter 3. MaverickCrunch Co-Processor .........................................................3-1

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

3.1.1 Features ..........................................................................................................................3-1

3.1.2 Operational Overview......................................................................................................3-1

3.1.3 Pipelines and Latency .....................................................................................................3-3

3.1.4 Data Registers.................................................................................................................3-3

3.1.5 Integer Saturation Arithmetic...........................................................................................3-4

3.1.6 Comparisons ...................................................................................................................3-6

3.2 Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8

3.2.1 Example 1........................................................................................................................3-8

3.2.1.1 Setup Code....................................................................................................3-8

3.2.1.2 C Code...........................................................................................................3-8

3.2.1.3 Accessing MaverickCrunch with ARM Co-Processor Instructions.................3-8

3.2.1.4 MaverickCrunch Assembly Language Instructions........................................3-8

3.2.2 Example 2........................................................................................................................3-9

3.2.2.1 C Code...........................................................................................................3-9

3.2.2.2 MaverickCrunch Assembly Language Instructions........................................3-9

3.3 DSPSC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10

3.4 ARM Co-Processor Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

3.5 Instruction Set for the MaverickCrunch Co-Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

3.5.1 Load and Store Instructions...........................................................................................3-21

3.5.2 Move Instructions ..........................................................................................................3-24

3.5.3 Accumulator and DSPSC Move Instructions.................................................................3-27

3.5.4 Copy and Conversion Instructions.................................................................................3-31

3.5.5 Shift Instructions............................................................................................................3-35

3.5.6 Compare Instructions ....................................................................................................3-36

3.5.7 Floating Point Arithmetic Instructions ............................................................................3-38

3.5.8 Integer Arithmetic Instructions.......................................................................................3-41

3.5.9 Accumulator Arithmetic Instructions ..............................................................................3-45

Chapter 4. Boot ROM ............................................................................................4-1

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

4.1.1 Boot ROM Hardware Operational Overview....................................................................4-1

4.1.1.1 Memory Map..................................................................................................4-1

4.1.2 Boot ROM Software Operational Overview.....................................................................4-1

4.1.2.1 Image Header................................................................................................4-2

4.1.2.2 Boot Algorithm ...............................................................................................4-2

4.1.2.3 Flowchart .......................................................................................................4-3

4.2 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

4.2.1 UART Boot ......................................................................................................................4-6

4.2.2 SPI Boot ..........................................................................................................................4-6

4.2.3 FLASH Boot.....................................................................................................................4-6

4.2.4 SDRAM or SyncFLASH Boot ..........................................................................................4-7

EP93xx User’s Guide

4.2.5 Synchronous Memory Operation............................................................... ...... ....... ...... ...4-7

Chapter 5. System Controller...............................................................................5-1

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

5.1.1 System Startup................................................................................................................5-1

5.1.2 System Reset ..................................................................................................................5-1

5.1.3 Hardware Configuration Control......................................................................................5-2

5.1.4 Software System Configuration Options..........................................................................5-4

5.1.5 Clock Control...................................................................................................................5-4

5.1.5.1 Oscillators and Programmable PLLs .............................................................5-4

5.1.5.2 Bus and Peripheral Clock Generation ...........................................................5-5

5.1.5.3 Steps for Clock Configuration........................................................................5-9

5.1.6 Power Management ........................................................................................................5-9

5.1.6.1 Clock Gatings ................................................................................................5-9

5.1.6.2 System Power States ..................................................................................5-10

5.1.7 Interrupt Generation ......................................................................................................5-12

5.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13

Chapter 6. Vectored Interrupt Controller.............................................................6-1

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

6.1.1 Interrupt Priority...............................................................................................................6-2

6.1.2 Interrupt Configuration.....................................................................................................6-3

6.1.3 Interrupt Details ...............................................................................................................6-4

6.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8

Chapter 7. Raster Engine With Analog/LCD Integrated

Timing and Interface ............................................................................................7-1

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1

7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3

7.3 Raster Engine Features Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3

7.3.1 Hardware Blinking ...........................................................................................................7-3

7.3.2 Color Look-Up Tables......................................................................................................7-4

7.3.3 Grayscale/Color Generation for Monochrome/Passive Low Color Displays ...................7-4

7.3.4 Frame Buffer Organization..............................................................................................7-4

7.3.5 Frame Buffer Memory Size..............................................................................................7-6

7.3.6 Pulse Width Modulated Brightness..................................................................................7-6

7.3.7 Hardware Cursor .............................................................................................................7-7

7.4 Functional Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7

7.4.1 VILOSATI (Video Image Line Output Scanner and Transfer Interface) ..........................7-8

7.4.2 Video FIFO ......................................................................................................................7-9

7.4.3 Video Pixel MUX............................................................................................................7-10

7.4.4 Blink Function................................................................................................................7-10

7.4.5 Color Look-Up-Tables ...................................................................................................7-11

7.4.6 Color RGB Mux .............................................................................................................7-11

7.4.7 Pixel Shift Logic.............................................................................................................7-12

7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays ...................7-15

7.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters........................................................7-16

7.4.8.2 VERT_CNT3, VERT_CNT4 Counters .........................................................7-16

7.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters ...................................................7-16

7.4.8.4 HORZ_CNTx (pixel) timing..........................................................................7-16

7.4.8.5 VERT_CNTx (line) timing ............................................................................7-16

EP93xx User’s Guide

7.4.8.6 FRAME_CNTx timing ..................................................................................7-16

7.4.8.7 Grayscale Look-Up Table (GrySclLUT).......................................................7-17

7.4.8.8 GrySclLUT Timing Diagram.........................................................................7-18

7.4.9 Hardware Cursor ...........................................................................................................7-24

7.4.9.1 Registers Used for Cursor ...........................................................................7-26

7.4.10 Video Timing................................................................................................................7-28

7.4.10.1 Setting the Video Memory Parameters......................................................7-31

7.4.10.2 PixelMode ..................................................................................................7-32

7.4.11 Blink Logic ...................................................................................................................7-32

7.4.11.1 BlinkRate ...................................................................................................7-32

7.4.11.2 Defining Blink Pixels ..................................................................................7-32

7.4.11.3 Types of Blinking .................................. ....... ...... ....... .................................7-33

7.4.12 Color Mode Definition..................................................................................................7-35

7.4.12.1 Pixel Look-up Table Mode.........................................................................7-35

7.4.12.2 Triple 8-bit Color Definition Mode ..............................................................7-35

7.4.12.3 16-bit 565 Color Definition Mode ...............................................................7-35

7.4.12.4 16-bit 555 Color Definition Mode ...............................................................7-35

7.5 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-36

Chapter 8. Graphics Accelerator..........................................................................8-1

8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1

8.2 Block Processing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1

8.2.1 Copy ................................................................................................................................8-2

8.2.1.1 Transparency.................................................................................................8-2

8.2.1.2 Logical Mask..................................................................................................8-2

8.2.1.3 Logical Destination ........................................................................................8-2

8.2.1.4 Operation Precedence...................................................................................8-2

8.2.2 Remapping ......................................................................................................................8-3

8.2.3 Block Fills ........................................................................................................................8-3

8.2.4 Packed Memory Transfer................................................................................................8-3

8.3 Line Draws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3

8.3.1 Breshenham Line Draws.................................................................................................8-4

8.3.2 Pixel Step Line Draws .....................................................................................................8-4

8.4 Memory Organization for Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4

8.4.1 Memory Organization for 1 Bit Per Pixel (bpp)...............................................................8-5

8.4.2 Memory Organization for 4-Bits Per Pixel .......................................................................8-5

8.4.3 Memory Organization for 8-Bits Per Pixel .......................................................................8-5

8.4.4 Memory Organization for 16-Bits Per Pixel .....................................................................8-6

8.4.5 Memory Organization for 24-Bits Per Pixel .....................................................................8-7

8.4.6 Memory Map Access.......................................................................................................8-8

8.5 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8

8.5.1 Word Count .....................................................................................................................8-8

8.5.1.1 Example: 8 BPP mode...................................................................................8-8

8.5.1.2 Example: 24 BPP (packed) mode..................................................................8-9

8.5.2 Pixel End and Start..........................................................................................................8-9

8.5.2.1 4 BPP Word Layout .....................................................................................8-10

8.5.2.2 8 BPP Word Layout .....................................................................................8-11

8.5.2.3 16 BPP WORD Layout ................................................................................8-11

8.5.2.4 24 BPP mode...............................................................................................8-12

8.6 Register Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13

8.6.1 Breshenham’s Algorithm Line Draw ..............................................................................8-13

8.6.2 Example of Breshenham’s Algori thm Lin e Draw ...... ....... ...... ....... ...... ....... ...... ..............8-1 5

8.6.3 Block Fill Function .........................................................................................................8-16

EP93xx User’s Guide

8.6.4 Block Copy Function......................................................................................................8-18

8.6.4.1 Example of Block Copy................................................................................8-21

8.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22

Chapter 9. 1/10/100 Mbps Ethernet LAN Controller ...........................................9-1

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1

9.1.1 Detailed Description ........................................................................................................9-1

9.1.1.1 Host Interface and Descriptor Processor.......................................................9-1

9.1.1.2 Reset and Initialization...................................................................................9-2

9.1.1.3 Power-down Modes.......................................................................................9-2

9.1.1.4 Address Space ..............................................................................................9-2

9.1.2 MAC Engine ....................................................................................................................9-3

9.1.2.1 Data Encapsulation........................................................................................9-3

9.1.3 Packet Transmission Process.........................................................................................9-5

9.1.3.1 Carrier Deference..........................................................................................9-5

9.1.4 Transmit Back-Off............................................................................................................9-7

9.1.4.1 Transmission .................................................................................................9-7

9.1.4.2 The FCS Field................................................................................................9-7

9.1.4.3 Bit Order ........................................................................................................9-8

9.1.4.4 Destination Address (DA) Filter .....................................................................9-8

9.1.4.5 Perfect Address Filtering ...............................................................................9-8

9.1.4.6 Hash Filter .....................................................................................................9-9

9.1.4.7 Flow Control.................................................................................................9-10

9.1.4.8 Receive Flow Control...................................................................................9-10

9.1.4.9 Transmit Flow Control..................................................................................9-10

9.1.4.10 Rx Missed and Tx Collision Counters....................................................... .9-11

9.1.4.11 Accessing the MII ......................................................................................9-11

9.2 Descriptor Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13

9.2.1 Receive Descriptor Processor Queues .........................................................................9-13

9.2.2 Receive Descriptor Queue ............................................................................................9-13

9.2.3 Receive Status Queue...................................................................................................9-16

9.2.3.1 Receive Status Format................................................................................9-18

9.2.3.2 Receive Flow ...............................................................................................9-21

9.2.3.3 Receive Errors.............................................................................................9-22

9.2.3.4 Receive Descriptor Data/Status Flow..........................................................9-23

9.2.3.5 Receive Descriptor Example .......................................................................9-24

9.2.3.6 Receive Frame Pre-Processing...................................................................9-25

9.2.3.7 Transmit Descriptor Processor Queues.......................................................9-26

9.2.3.8 Transmit Descriptor Queue..........................................................................9-26

9.2.3.9 Transmit Descriptor Format.........................................................................9-28

9.2.3.10 Transmit Status Queue..............................................................................9-30

9.2.3.11 Transmit Status Format .............................................................................9-32

9.2.3.12 Transmit Flow ............................................................................................9-34

9.2.3.13 Transmit Errors..........................................................................................9-35

9.2.3.14 Transmit Descriptor Data/Status Flow.......................................................9-36

9.2.4 Interrupts .......................................................................................................................9-37

9.2.4.1 Interrupt Processing.....................................................................................9-37

9.2.5 Initialization....................................................................................................................9-37

9.2.5.1 Interrupt Processing.....................................................................................9-38

9.2.5.2 Receive Queue Processing .........................................................................9-38

9.2.5.3 Transmit Queue Processing ........................................................................9-38

9.2.5.4 Other Processing.........................................................................................9-38

9.2.5.5 Transmit Restart Process ............................................................................9-39

9.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-40

EP93xx User’s Guide

Chapter 10. DMA Controller................................................................................10-1

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1

10.1.1 DMA Features List.......................................................................................................10-1

10.1.2 Managing Data Transfers Using a DMA Channel ...................... .................................10-2

10.1.3 DMA Operations..........................................................................................................10-3

10.1.3.1 Memory-to-Memory Channels ...................................................................10-3

10.1.3.2 Memory-to-Peripheral Channels................................................................10-4

10.1.4 Internal M2P or P2M AHB Master Interface Functional Description............................10-4

10.1.5 M2M AHB Master Interface Functional Description.....................................................10-5

10.1.5.1 Software Trigger Mode ..............................................................................10-5

10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and

for External Peripherals without Hand sh aking Signa ls ............................. ..............10- 6

10.1.5.3 Hardware Trigger Mode for External Peripherals with

Handshaking Signals............................................................................ ...... ....... .......10-6

10.1.6 AHB Slave Interface Limitations..................................................................................10-6

10.1.7 Interrupt Interface........................................................................................................10-6

10.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description..............................10-6

10.1.9 Internal M2P/P2M DMA Functional Description..........................................................10-7

10.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine ....................10-7

10.1.9.2 Data Transfer Initiation and Termination ...................................................10-9

10.1.10 M2M DMA Functional Description...........................................................................10-10

10.1.10.1 M2M DMA Control Finite State Machine ...............................................10-10

10.1.10.2 M2M Buffer Control Finite State Machine..............................................10-12

10.1.10.3 Data Transfer Initiation ..........................................................................10-13

10.1.10.4 Data Transfer Termination.....................................................................10-15

10.1.10.5 Memory Block Transfer..........................................................................10-16

10.1.10.6 Bandwidth Control .................................................................................10-16

10.1.10.7 External DMA Request (DREQ) Mode ..................................................10-16

10.1.11 DMA Data Transfer Size Determination ..................................................................10-17

10.1.11.1 Software Initiated M2M and M2P/P2M Transfers..................................10-17

10.1.11.2 Hardware-Initiated M2M Transfers ........................................................10-18

10.1.12 Buffer Descriptors....................................................................................................10-18

10.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors ................................10-19

10.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors.................................10-19

10.1.12.3 M2M Channel Buffer Descriptors...........................................................10-19

10.1.13 Bus Arbitration.........................................................................................................10-19

10.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-20

10.2.1 DMA Controller Memory Map....................................................................................10-20

10.2.2 Internal M2P/P2M Channel Register Map.................................................................10-21

Chapter 11. Universal Serial Bus Host Controller............................................11-1

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1

11.1.1 Features ......................................................................................................................11-1

11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1

11.2.1 Data Transfer Types....................................................................................................11-2

11.2.2 Host Controller Interface..............................................................................................11-3

11.2.2.1 Communication Channels..........................................................................11-3

11.2.2.2 Data Structures..........................................................................................11-4

11.2.3 Host Controller Driver Responsibilities........................................................................11-6

11.2.3.1 Host Controller Management.....................................................................11-6

11.2.3.2 Bandwidth Allocation .................................................................................11-6

11.2.3.3 List Management.......................................................................................11-7

11.2.3.4 Root Hub....................................................................................................11-7

EP93xx User’s Guide

11.2.4 Host Controller Responsibilities...................................................................................11-8

11.2.4.1 USB States ................................................................................................11-8

11.2.4.2 Frame Management ..................................................................................11-8

11.2.4.3 List Processing ..........................................................................................11-8

11.2.5 USB Host Controller Blocks.........................................................................................11-9

11.2.5.1 AHB Slave .................................................................................................11-9

11.2.5.2 AHB Master ...............................................................................................11-9

11.2.5.3 HCI Slave Block.........................................................................................11-9

11.2.5.4 HCI Master Block.....................................................................................11-10

11.2.5.5 USB State Control ...................................................................................11-10

11.2.5.6 Data FIFO................................................................................................11-10

11.2.5.7 List Processor..........................................................................................11-10

11.2.5.8 Root Hub and Host SIE ...........................................................................11-10

11.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11

Chapter 12. Static Memory Controller ...............................................................12-1

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1

12.2 Static Memory Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2

12.3 PCMCIA Interface (EP9315 Processor Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5

12.4 PC Card Memory-Mode Enable Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8

12.5 PC Card Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8

12.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10

12.6.1 Bank Configuration Registers....................................................................................12-10

12.6.2 PCMCIA Configuration Registers (EP9315 Processor Only) ....................................12-13

Chapter 13. SDRAM, SyncROM, and SyncFLASH Controller..........................13-1

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1

13.2 Booting from SyncROM or SyncFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1

13.3 Address Pin Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3

13.4 SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4

13.5 Programming Mode Register: SDRAM Or SyncROM Device. . . . . . . . . . . . . . . . . . . . . . .13-6

13.6 SDRAM Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8

13.6.1 Entering Self Refresh Mode ........................................................................................13-8

13.6.2 Exiting Self Refresh Mode...........................................................................................13-8

13.7 Programming Registers: SyncFLASH Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8

13.8 External Synchronous Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9

13.8.1 Chip Select SDCSN[3:0] Decoding .............................................................................13-9

13.8.2 Address/Data/Control Required by Memory System.................................................13-10

13.9 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-17

Chapter 14. UART1 With HDLC and Modem Control Signals..........................14-1

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

14.2 UART Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

14.2.1 UART Functional Description ......................................................................................14-2

14.2.1.1 AMBA APB Interface .................................................................................14-2

14.2.1.2 DMA Block.................................................................................................14-2

14.2.1.3 Register Block............................................................................................14-2

14.2.1.4 Baud Rate Generator.................................................................................14-4

14.2.1.5 Transmit FIFO............................................................................................14-4

14.2.1.6 Receive FIFO........ ....... ...... ....... ...... ...... ....... ...... ....... .................................14-4

14.2.1.7 Transmit Logic...........................................................................................14-4

14.2.1.8 Receive Logic ....... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ..............14-4

EP93xx User’s Guide

14.2.2 UART Operation..........................................................................................................14-5

14.2.3 Interrupts .....................................................................................................................14-7

14.3 Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8

14.4 HDLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8

14.4.1 Overview of HDLC Modes...........................................................................................14-9

14.4.2 Selecting HDLC Modes...............................................................................................14-9

14.4.3 HDLC Transmit..........................................................................................................14-11

14.4.4 HDLC Receive...........................................................................................................14-11

14.4.5 CRCs.........................................................................................................................14-12

14.4.6 Address Matching......................................................................................................14-12

14.4.7 Aborts ........................................................................................................................14-13

14.4.8 DMA...........................................................................................................................14-14

14.4.9 Writing Configuration Registers.................................................................................14-14

14.5 UART1 Package Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-14

14.5.1 Clocking Requirements .............................................................................................14-15

14.5.2 Bus Bandwidth Requirements ...................................................................................14-16

14.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-17

14.2.1.9 Interrupt Generation Logic.........................................................................14-4

14.2.1.10 Synchronizing Registers and Logic .........................................................14-5

14.2.2.1 Error Bits....................................................................................................14-6

14.2.2.2 Disabling the FIFOs...................................................................................14-6

14.2.2.3 System/diagnostic Loo pbac k Testin g ... .............................................. ...... .14-6

14.2.2.4 UART Character Frame.............................................................................14-6

14.2.3.1 UARTMSINTR ...........................................................................................14-7

14.2.3.2 UARTRXINTR............................................................................................14-7

14.2.3.3 UARTTXINTR............................................................................................14-7

14.2.3.4 UARTRTINTR............................................................................................14-8

14.2.3.5 UARTINTR.................................................................................................14-8

Chapter 15. UART2..............................................................................................15-1

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1

15.2 IrDA SIR Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1

15.2.1 IrDA SIR Encoder/decoder Functional Description .....................................................15-1

15.2.1.1 IrDA SIR Transmit Encoder .......................................................................15-2

15.2.1.2 IrDA SIR Receive Decoder........................................................................15-2

15.2.2 IrDA SIR Operation......................................................................................................15-3

15.2.2.1 System/diagnostic Loo pbac k Testin g ... .............................................. ...... .15-4

15.2.3 IrDA Data Modulation..................................................................................................15-4

15.2.4 Enabling Infrared (Ir) Modes........................................................................................15-5

15.3 UART2 Package Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-5

15.3.1 Clocking Requirements ...............................................................................................15-5

15.3.2 Bus Bandwidth Requirements .....................................................................................15-6

15.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7

Chapter 16. UART3 With HDLC Encoder...........................................................16-1

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1

16.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1

16.2.1 UART3 Package Dependency.....................................................................................16-1

16.2.2 Clocking Requirements ...............................................................................................16-2

16.2.3 Bus Bandwidth Requirements .....................................................................................16-2

16.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3

EP93xx User’s Guide

Chapter 17. IrDA ..................................................................................................17-1

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1

17.2 IrDA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1

17.3 Shared IrDA Interface Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-2

17.3.1 Overview......................................................................................................................17-2

17.3.2 Functional Description.................................................................................................17-2

17.3.2.1 General Configuration................................................................................17-3

17.3.2.2 Transmitting Data ......................................................................................17-3

17.3.2.3 Receiving Data ..........................................................................................17-5

17.3.2.4 Special Conditions.....................................................................................17-7

17.3.3 Control Information Buffering.......................................................................................17-8

17.4 Medium IrDA Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-8

17.4.1 Introduction..................................................................................................................17-8

17.4.1.1 Bit Encoding...............................................................................................17-8

17.4.1.2 Frame Format............................................................................................17-9

17.4.2 Functional Description...............................................................................................17-11

17.4.2.1 Baud Rate Generation.............................................................................17-11

17.4.2.2 Receive Operation...................................................................................17-11

17.4.2.3 Transmit Operation..................................................................................17-13

17.5 Fast IrDA Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-13

17.5.1 Introduction................................................................................................................17-14

17.5.1.1 4PPM Modulation ..................................................... ...... ....... ..................17-14

17.5.1.2 4.0 Mbps FIR Frame Format ...................................................................17-15

17.5.2 Functional Description...............................................................................................17-17

17.5.2.1 Baud Rate Generation.............................................................................17-17

17.5.2.2 Receive Operation...................................................................................17-18

17.5.2.3 Transmit Operation..................................................................................17-19

17.5.3 IrDA Connectivity.......................................................................................................17-20

17.5.4 IrDA Integration Information ......................................................................................17-21

17.5.4.1 Enabling Infrared Modes..........................................................................17-21

17.5.4.2 Clocking Requirements............................................................................17-21

17.5.4.3 Bus Bandwidth Requirements .................................................................17-22

17.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-23

Chapter 18. Timers ..............................................................................................18-1

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1

18.1.1 Features ......................................................................................................................18-1

18.1.2 16 and 32-bit Timer Operation.....................................................................................18-1

18.1.2.1 Free Running Mode ...................................................................................18-2

18.1.2.2 Pre-load Mode ............. ...... ....... ...... ...... .............................................. ...... .18-2

18.1.3 40-bit Timer Operation.................................................................................................18-2

18.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2

Chapter 19. Watchdog Timer..............................................................................19-1

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1

19.1.1 Watchdog Activation....................................................................................................19-2

19.1.2 Clocking Requirements ...............................................................................................19-2

19.1.3 Reset Requirements....................................................................................................19-2

19.1.4 Watchdog Status .........................................................................................................19-2

19.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-3

EP93xx User’s Guide

Chapter 20. Real Time Clock With Software Trim ............................................20-1

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1

20.1.1 Software Trim ..............................................................................................................20-1

20.1.1.1 Software Compensation ............................................................................20-2

20.1.1.2 Oscillator Frequency Calibration................................................................20-2

20.1.1.3 RTCSWComp Value Determination ..........................................................20-2

20.1.1.4 Example - Measured Value Split Into Integer and Fractional Component.20-3

20.1.1.5 Maximum Error Calculation vs. Real Time Clock Accuracy.......................20-3

20.1.1.6 Real-Time Interrupt....................................................................................20-3

20.1.2 Reset Control...............................................................................................................20-4

20.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-4

Chapter 21. I2S Controller...................................................................................21-1

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1

21.2 I

21.3 I

21.4 I

21.5 I

21.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10

21.7 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-12

S Transmitter Channel Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-2

S Receiver Channel Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-5

21.3.1 Receiver FIFO’s...........................................................................................................21-6

S Master Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-7

S Bit Clock Rate Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9

21.5.1 Example of the Bit Clock Generation...........................................................................21-9

21.5.2 Example of Right Justified LRCK format ...................................................................21-10

21.7.1 I

21.7.2 I

21.7.3 I

21.7.4 I

S TX Registers............................ ...... ....... ...... ............................................. ....... .....21-12

S RX Registers ................................. ....... ...... ...... ....... ...... ....... ...... ....... ...... ............21-19

S Configuration and Status Registers.....................................................................21-25

S Global Status Registers.......................................................................................21-29

Chapter 22. AC’97 Controller..............................................................................22-1

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1

22.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3

22.2.1 Channel Interrupts.......................................................................................................22-3

22.2.1.1 RIS.............................................................................................................22-3

22.2.1.2 TIS .............................................................................................................22-3

22.2.1.3 RTIS...........................................................................................................22-4

22.2.1.4 TCIS...........................................................................................................22-4

22.2.2 Global Interrupts..........................................................................................................22-4

22.2.2.1 CODECREADY .........................................................................................22-4

22.2.2.2 WINT..........................................................................................................22-4

22.2.2.3 GPIOINT....................................................................................................22-4

22.2.2.4 GPIOTXCOMPLETE .................................................................................22-5

22.2.2.5 SLOT2INT..................................................................................................22-5

22.2.2.6 SLOT1TXCOMPLETE...............................................................................22-5

22.2.2.7 SLOT2TXCOMPLETE...............................................................................22-5

22.3 System Loopback Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5

22.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5

Chapter 23. Synchronous Serial Port................................................................23-1

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1

23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1

23.3 SSP Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2

23.4 SSP Pin Multiplex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2

EP93xx User’s Guide

23.5 Configuring the SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2

23.5.1 Enabling SSP Operation..............................................................................................23-2

23.5.2 Master/Slave Mode......................................................................................................23-3

23.5.3 Serial Bit Rate Generation...........................................................................................23-3

23.5.4 Frame Format.............................................................................................................23-3

23.5.5 Texas Instruments

23.5.6 Motorola

23.5.6.1 SPO Clock Polarity ....................................................................................23-5

23.5.6.2 SPH Clock Phase......................................................................................23-5

23.5.7 Motorola SPI Format with SPO=0, SPH=0..................................................................23-5

23.5.8 Motorola SPI Format with SPO=0, SPH=1.................................................................23-7

23.5.9 Motorola SPI Format with SPO=1, SPH=0..................................................................23-8

23.5.10 Motorola SPI Format with SPO=1, SPH=1................................................................23-9

23.5.11 National Semiconductor

23.5.11.1 Setup and Hold Time Requirements on SFRMIN with

Respect to SCLKIN in Microwire Mode ............... ....... ...... ....... ...... ....... ...... ............23-12

23.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-13

SPI Frame Format......................................................................................23-5

Synchronous Serial Frame Format.............................................23-4

Microwire™ Frame Format .............................................23-10

Chapter 24. Pulse Width Modulator...................................................................24-1

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1

24.2 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1

24.2.1 PWM Programming Examples ....................................................................................24-2

24.2.1.1 Example.....................................................................................................24-2

24.2.1.2 Static Programming (PWM is Not Running) Example ...............................24-2

24.2.1.3 Dynamic Programming (PWM is Running) Example.................................24-3

24.2.2 Programming Rules.....................................................................................................24-3

24.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-3

Chapter 25. Analog Touch Screen Interface.....................................................25-1

25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-1

25.2 Touch Screen Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-1

25.2.1 Touch Screen Scanning: Four-wire and Eight-wire Operation ....................................25-4

25.2.2 Five-wire and Seven-wire Operation .........................................................................25-10

25.2.3 Direct Operation ........................................................................................................25-12

25.2.4 Measuring Analog Input with the Touch Screen Controls Disabled ..........................25-13

25.2.5 Measuring Touch Screen Resistance........................................................................25-15

25.2.6 Polled and Interrupt-Driven Modes............................................................................25-16

25.2.7 Touch Screen Package Dependency........................................................................25-16

25.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-17

Chapter 26. Keypad Interface.............................................................................26-1

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-1

26.2 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-2

26.2.1 Apparent Key Detection...............................................................................................26-3

26.2.2 Scan and Debounce....................................................................................................26-5

26.2.3 Interrupt Generation ....................................................................................................26-5

26.2.4 Low Power Mode.........................................................................................................26-6

26.2.5 Three-key Reset..........................................................................................................26-6

26.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-6

EP93xx User’s Guide

Chapter 27. IDE Interface....................................................................................27-1

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-1

27.2 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-1

27.2.1 Diagrams and State Machines ....................................................................................27-2

27.2.2 PIO Operations............................................................................................................27-3

27.2.3 MDMA Operations.......................................................................................................27-4

27.2.4 UDMA Operations .......................................................................................................27-5

27.2.5 Performance Considerations.......................................................................................27-5

27.2.6 UDMA Example...........................................................................................................27-6

27.2.7 DMA Request Latency.................................................................................................27-7

27.2.7.1 DMA Request Deassertion ........................................................................27-7

27.2.7.2 DMA Request Latency Overview...............................................................27-7

27.2.7.3 IDE DMA Programming Considerations....................................................27-8

27.2.8 IDE Package Dependency ..........................................................................................27-9

27.2.8.1 System Configuration Constraints .............................................................27-9

27.2.8.2 Bus Bandwidth Requirements ...................................................................27-9

27.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-10

Chapter 28. GPIO Interface.................................................................................28-1

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-1

28.1.1 Memory Map................................................................................................................ 28-3

28.1.2 Functional Description.................................................................................................28-3

28.1.3 Reset ...........................................................................................................................28-5

28.1.4 GPIO Pin Map .............................................................................................................28-6

28.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-9

Chapter 29. Security............................................................................................29-1

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-1

29.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-1

29.3 Contact Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-1

29.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-2

Chapter 30. Glossary...........................................................................................30-1

Chapter 31. EP93XX Register List......................................................................31-1

Figures

Figure 1-1. EP9301 Block Diagram...............................................................................................................1-2

Figure 1-2. EP9302 Block Diagram ..............................................................................................................1-3

Figure 1-3. EP9307 Block Diagram...............................................................................................................1-3

Figure 1-4. EP9312 Block Diagram...............................................................................................................1-4

Figure 1-5. EP9315 Block Diagram...............................................................................................................1-4

Figure 2-1. ARM920T Block Diagram ...........................................................................................................2-2

Figure 2-2. Typical AMBA AHB System........................................................................................................2-7

Figure 2-3. Main Data Paths .........................................................................................................................2-8

EP93xx User’s Guide

Figure 4-1. Flow Chart of Boot ROM Software..............................................................................................4-4

Figure 4-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices...........................................................4-7

Figure 5-1. Phase Locked Loop (PLL) Structure...........................................................................................5-4

Figure 5-2. Clock Generation System ...........................................................................................................5-6

Figure 5-3. Bus Clock Generation.................................................................................................................5-7

Figure 5-4. Power States and Transitions...................................................................................................5-11

Figure 6-1. Vectored Interrupt Controller Block Diagram ..............................................................................6-2

Figure 7-1. Raster Engine Block Diagram.....................................................................................................7-8

Figure 7-2. Video Buffer Diagram..................................................................................................................7-9

Figure 7-3. Graphics Matrix for 50% Duty Cycle.........................................................................................7-20

Figure 7-4. Sample Matrix Causing Flickering ............................................................................................7-21

Figure 7-5.. Sample Matrix That Avoids Flickering......................................................................................7-21

Figure 7-6. Programming for One-third Luminous Intensity ........................................................................7-22

Figure 7-7. Creating Bit Patterns that Move to the Right.............................................................................7-23

Figure 7-8. Three and Four Count Axis.......................................................................................................7-24

Figure 7-9. Progressive/Dual Scan Video Si gna ls ................................. ....... ...... ........................................7-29

Figure 7-10. Interlaced Video Signals ................................. ....... ...... ...... .....................................................7-30

Figure 9-1. 1/10/100 Mbps Ethernet LAN Controller Block Diagram.............................................................9-1

Figure 9-2. Ethernet Frame / Packet Format (Type II only)...........................................................................9-4

Figure 9-3. Packet Transmission Process.....................................................................................................9-5

Figure 9-4. Carrier Deference State Diagram ...............................................................................................9-6

Figure 9-5. Data Bit Transmission Order.......................................................................................................9-8

Figure 9-6. CRC Logic...................................................................................................................................9-9

Figure 9-7. Receive Descriptor Format and Data Fragments .....................................................................9-14

Figure 9-8. Receive Status Queue..............................................................................................................9-17

Figure 9-9. Receive Flow Diagram ............................................................................................................9-21

Figure 9-10. Receive Descriptor Data/Status Flow ................................ ....... ...... ....... ...... ....... ....................9-23

Figure 9-11. Receive Descriptor Example.............. ....... ...... ....... ...... ...... ....... ...... ....... ...... ...........................9-24

Figure 9-12. Receive Frame Pre-processing ... ...... ....... ...... ............................................. ....... ...... ..... .........9-25

Figure 9-13. Transmit Descriptor Format and Data Fragments ..................................................................9-27

Figure 9-14. Multiple Fragments Per Transmit Frame ................................................................................9-28

Figure 9-15. Transmit Status Queue...........................................................................................................9-31

Figure 9-16. Transmit Flow Diagram...........................................................................................................9-34

Figure 9-17. Transmit Descriptor Data/Status Flow ....................................................................................9-36

Figure 10-1. DMA M2P/P2M Finite State Machine .....................................................................................10-7

Figure 10-2. M2M DMA Control Finite State Machine...............................................................................10-10

Figure 10-3. M2M DMA Buffer Finite State Machine.................................................................................10-12

EP93xx User’s Guide

Figure 10-4. Edge-triggered DREQ Mode..................................................... ...... ....... ...............................10-17

Figure 11-1. USB Focus Areas ...................................................................................................................11-2

Figure 11-2. Communication Channels......................................................... ...... ........................................11-3

Figure 11-3. Typical List Structure ............ ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... .................................11-4

Figure 11-4. Interrupt Endpoint Descriptor Structure ..................................................................................11-5

Figure 11-5. Sample Interrupt Endpoint Schedule ......................................................................................11-6

Figure 11-6. USB Host Controller Block Diagram .......................................................................................11-9

Figure 12-1. 32-bit Read, 32-bit Memory, 0 Wait Cycles, RBLE = 1, WAITn Inactive.................................12-3

Figure 12-2. 32-bit Write, 32-bit Memory, 0 Wait Cycles, RBLE = 1, WAITn Inactive.................................12-3

Figure 12-3. 16-bit Read, 16-bit Memory, RBLE = 1, WAITn Active ...........................................................12-4

Figure 12-4. 16-bit Write, 16-bit Memory, RBLE = 1, WAITn Active ...........................................................12-4

Figure 12-5. Single PC Card Interface ........................................................................................................12-7

Figure 14-1. UART Block Diagram..............................................................................................................14-3

Figure 14-2. UART Character Frame .........................................................................................................14-6

Figure 14-3. UART Character Frame..........................................................................................................14-6

Figure 15-1. IrDA SIR Encoder/decoder Block Diagram.............................................................................15-2

Figure 15-2. IrDA Data Modulation (3/16) ...................................................................................................15-4

Figure 17-1. RZ1/NRZ Bit Encoding Example.............................................................................................17-9

Figure 17-2. 4PPM Modulation Encoding............................................................ ....... ...... ....... ..................17-14

Figure 17-3. 4PPM Modulation Example....................... ............................................. ...... ....... ..................17-15

Figure 17-4. IrDA (4.0 Mbps) Transmission Format..................................................................................17-15

Figure 21-1. Architectural Overview of the I

S Controller ...........................................................................21-1

Figure 21-2. Bit Clock Generation Example ...........................................................................................21-10

Figure 21-3. Frame Format for Right Justified Data..................................................................................21-10

Figure 23-1. Texas Instruments Synchronous Serial Frame Format (Single Transfer)...............................23-4

Figure 23-2. TI Synchronous Serial Frame Format (Continuous Transfer).................................................23-4

Figure 23-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0 ................................23-5

Figure 23-4. Motorola SPI Frame Format (Continuous Transfer)

with SPO=0 and SPH=0 ...................... ...... ....... ............................................. ...... ....... ...... ...........................23-6

Figure 23-5. Motorola SPI Frame Format with SPO=0 and SPH=1............................................................23-7

Figure 23-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ................................23-8

Figure 23-7. Motorola SPI Frame Format (Continuous Transfer)

with SPO=1 and SPH=0 ...................... ...... ....... ............................................. ...... ....... ...... ...........................23-8

Figure 23-8. Motorola SPI Frame Format with SPO=1 and SPH=1............................................................23-9

Figure 23-9. Microwire Frame Format (Single Transfer) ...........................................................................23-10

Figure 23-10. Microwire Frame Format (Continuous Transfers)...............................................................23-12

Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements...........................23-12

Figure 24-1. PWM_INV Example .................................. ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ..............24-6

EP93xx User’s Guide

Figure 25-1. Different Types of Touch Screens ..........................................................................................25-2

Figure 25-2. 8-Wire Resistive Interface Switching Diagram.......................................................................25-5

Figure 25-3. 4-Wire Analog Resistive Interface Switching Diagram............................................................25-6

Figure 25-4. Analog Resistive Touch Screen Scan Flow Chart .......................... ....... ...... ....... ...... ..............25-9

Figure 25-5. 5-Wire Analog Resistive Interface Switching Diagram..........................................................25-11

Figure 25-6. 5-Wire Feedback (7-Wire) Analog Resistive Interface Switching Diagram...........................25-12

Figure 25-7. Power Down Detect Press Switching Diagram.....................................................................25-13

Figure 25-8. Other Switching Diagrams ..................................... ...... ...... ....... ...... ....... ...... ....... ...... ............25-14

Figure 25-9. Measure Resistance Switching Diagram..............................................................................25-15

Figure 26-1. Key Array Block Diagram ...................................................................................................26-1

Figure 26-2. 8 x 8 Key Array Diagram ......................................................................................................26-3

Figure 26-3. Apparent Key 00H...................................................................................................................26-4

Figure 27-1. IDE Interface Signal Connections ................................................................ ....... ...... ..............27-2

Figure 28-1. System Level GPIO Connectivity............................................................................................28-2

Figure 28-2. Signal Connections Within the Standard GPIO Port Control Logic

(Ports C, D, E, G, H)....................................................................................................................................28-4

Figure 28-3. Signal Connections Within the Enhanced GPIO Port Control Logic

(Ports A, B, F)..............................................................................................................................................28-5

Tables

Table P-1. Frequency, Package, Applicable EP93xx Processor.................................................................. P-1

Table P-2. Chapter Number and Function, Applicable EP93xx Processor ..................................................P-1

Table 1-1. EP93xx Maximum Clock Rates, Package Type and Number of Balls .........................................1-1

Table 1-2. EP93xx Features Summary .........................................................................................................1-2

Table 2-1. AHB Arbiter Priority Scheme......................................................................................................2-10

Table 2-2. AHB Peripheral Address Range.................................................................................................2-11

Table 2-3. APB Peripheral Address Range.................................................................................................2-12

Table 2-4. ARM920T Core Operating Modes..............................................................................................2-13

Table 2-5. Register Organization Summary................................................................................................2-14

Table 2-6. CP15 ARM920T Register Description........................................................................................2-15

Table 2-7. Global Memory Map for the Two Boot Modes............................................................................2-16

Table 2-8. Internal Register Map ................................................................................................................2-17

Table 3-1. Saturation for Non-accumulator Instructions................................................................................3-5

Table 3-2. Accumulator Bit Formats for Saturation .......................................................................................3-5

Table 3-3. Comparison Relationships and Their Results..............................................................................3-7

Table 3-4. ARM® Condition Codes and Crunch Compare Results...............................................................3-7

Table 3-5. Condition Code Definitions.........................................................................................................3-15

EP93xx User’s Guide

Table 3-6. LDC/STC Opcode Map..............................................................................................................3-16

Table 3-7. CDP Opcode Map......................................................................................................................3-16

Table 3-8. MCR Opcode Map .....................................................................................................................3-17

Table 3-9. MRC Opcode Map .....................................................................................................................3-17

Table 3-10. MaverickCrunch Instruction Set .............................................................................................3-18

Table 3-11. Mnemonic Codes for Loading Floating Point Value from Memory...........................................3-21

Table 3-12. Mnemonic Codes for Loading Integer Value from Memory......................................................3-22

Table 3-13. Mnemonic Codes for Storing Floating Point Values to Memory...............................................3-23

Table 3-14. Mnemonic Codes for Storing Integer Values to Memory .........................................................3-23

Table 4-1. Boot Configuration Options..........................................................................................................4-5

Table 5-1. Hardware Configuration Control Latched Pins.............................................................................5-2

Table 5-2. Boot Configuration Options..........................................................................................................5-3

Table 5-3. Clock Speeds and Sources..........................................................................................................5-8

Table 5-4. Peripherals with PCLK Gating....................................................................................................5-10

Table 5-5. Syscon Register List ................................................................................................................5-13

Table 5-6. Priority Order for AHB Arbiter.....................................................................................................5-23

Table 5-7. Audio Interfaces Pin Assignment ...............................................................................................5-26

Table 6-1. Interrupt Configuration .................................................................................................................6-3

Table 6-2. VICx Register Summary...............................................................................................................6-8

Table 7-1. Raster Engine Video Mode Output Examples..............................................................................7-2

Table 7-2. Byte Oriented Frame Buffer Organization....................................................................................7-5

Table 7-3. Output Pixel Transfer Modes .....................................................................................................7-13

Table 7-4. Grayscale Lookup Table (GrySclLUT) .......................................................................................7-17

Table 7-5. Grayscale Timing Diagram.........................................................................................................7-18

Table 7-6. Programming Format.................................................................................................................7-19

Table 7-7. Programming 50% Duty Cycle Into Lookup Table .....................................................................7-22

Table 7-8. Programming 33% Duty Cycle into the Lookup Table ...............................................................7-23

Table 7-9. Programming 33% Duty Cycle into the Lookup Table ...............................................................7-24

Table 7-10. Cursor Memory Organization...................................................................................................7-25

Table 7-11. Bits P[2:0] in the PixelMode Register.......................................................................................7-32

Table 7-12. Raster Engine Register List .....................................................................................................7-36

Table 7-13. Color Mode Definition Table.....................................................................................................7-58

Table 7-14. Blink Mode Definition Table .....................................................................................................7-58

Table 7-15. Output Shift Mode Table..........................................................................................................7-59

Table 7-16. Bits per Pixel Scanned Out ......................................................................................................7-59

Table 7-17. Grayscale Look-Up-Table (LUT)..............................................................................................7-75

Table 8-1. Screen Pixels ...............................................................................................................................8-4

EP93xx User’s Guide

Table 8-2. bpp Memory Organization............................................................................................................8-5

Table 8-3. 4 bpp Memory Organization.........................................................................................................8-5

Table 8-4. 8 bpp Memory Organization.........................................................................................................8-6

Table 8-5. 16 bpp Memory Organization.......................................................................................................8-6

Table 8-6. 24 bpp Packed Memory Organization (4 pixel/ 3 words) .............................................................8-7

Table 8-7. 24 bpp Unpacked Memory Organization (1 pixel/ 1 word)...........................................................8-7

Table 8-8. Transfer Example 1......................................................................................................................8-8

Table 8-9. Transfer Example 2......................................................................................................................8-9

Table 8-10. Transfer Example 3....................................................................................................................8-9

Table 8-11. Transfer Example 4....................................................................................................................8-9

Table 8-12. Transfer Example 5....................................................................................................................8-9

Table 8-13. 4 BPP Memory Layout for Source Image.................................................................................8-10

Table 8-14. 4 BPP Memory Layout for Destination Image..........................................................................8-10

Table 8-15. 8 BPP Memory Layout for Source Image.................................................................................8-11

Table 8-16. 8 BPP Memory Layout for Destination Image..........................................................................8-11

Table 8-17. 16 BPP Memory Layout for Source Image...............................................................................8-11

Table 8-18. 16 BPP Memory Layout for Destination Image........................................................................8-12

Table 8-19. 24 BPP Memory Layout for Source Image...............................................................................8-12

Table 8-20. 24 BPP Memory Layout for Destination Image.......................................................................8-13

Table 8-21. Words Needed for Six 24-Bit Pixels.........................................................................................8-19

Table 8-22. Graphics Accelerator Registers ...............................................................................................8-22

Table 8-23. Pixel Mode Encoding ...............................................................................................................8-30

Table 9-1. FIFO RAM Address Map..............................................................................................................9-3

Table 9-2. RXCtl.MA and RXCtl.IAHA[0] Relationships..............................................................................9-10

Table 9-3. Ethernet Register List.................................................................................................................9-40

Table 9-4. Individual Accept, RxFlow Control Enable and Pause Accept Bits............................................9-42

Table 9-5. Address Filter Pointer.................................................................................................................9-52

Table 10-1. Data Transfer Size.................................................................................................................10-18

Table 10-2. M2P DMA Bus Arbitration ......................................................................................................10-19

Table 10-3. DMA Memory Map.................................................................................................................10-20

Table 10-4. Internal M2P/P2M Channel Register Map..............................................................................10-21

Table 10-5. PPALLOC Register Bits Decode for a Transmit Channel ......................................................10-24

Table 10-6. PPALLOC Register Bits Decode for a Receive Channel .......................................................10-24

Table 10-7. PPALLOC Register Reset Values..........................................................................................10-24

Table 10-8. PPALLOC Register Reset Values..........................................................................................10-30

Table 10-9. BWC Decode Values .............................................................................................................10-33

Table 10-10. DMA Global Interrupt (DMAGlInt) Register ..........................................................................10-45

EP93xx User’s Guide

Table 11-1. Frame Bandwidth Allocation ....................................................................................................11-7

Table 11-2. OpenHCI Register Addresses................................................................................................11-11

Table 12-1. PCMCIA Address Memory Ranges..........................................................................................12-5

Table 12-2. PCMCIA Pin Usage..................................................................................................................12-5

Table 12-3. Supported 8-Bit Accesses........................................................................................................12-8

Table 12-4. Supported 16-Bit Accesses......................................................................................................12-8

Table 12-5. PCMCIA Legacy Usage...........................................................................................................12-8

Table 12-6. Accesses to 8-Bit Attribute / Common / IO Memory.................................................................12-9

Table 12-7. Accesses to 16-Bit Attribute / Common / IO Memory...............................................................12-9

Table 12-8. Static Memory Controller (SMC) Register Map......................................................................12-10

Table 13-1. Boot Device Selection..............................................................................................................13-2

Table 13-2. Address Decoding for Synchronous Memory Domains ...........................................................13-3

Table 13-3. Synchronous Memory Address Decoding................................................................................13-4

Table 13-4. General SDRAM Initialization Sequence .................................................................................13-4

Table 13-5. Mode Register Command Decoding for 32-bit Wide Memory Bus ..........................................13-6

Table 13-6. Sync Memory CAS...................................................................................................................13-7

Table 13-7. Sync Memory RAS, Burst Type, and Write Burst Length.........................................................13-7

Table 13-8. Burst Length.............................................................................................................................13-7

Table 13-9. Chip Select Decoding...............................................................................................................13-9

Table 13-10. Memory Addressing Example ..............................................................................................13-11

Table 13-11. EP93xx SDRAM Address Ranges (16-Bit Wide Data Systems)..........................................13-12

Table 13-12. Address Bits Used for Chip Select.......................................................................................13-17

Table 13-13. Synchronous Memory Controller Registers .........................................................................13-17

Table 13-14. Synchronous Memory Command Encoding.........................................................................13-20

Table 14-1. Receive FIFO Bit Functions.....................................................................................................14-6

Table 14-2. Legal HDLC Mode Configurations .........................................................................................14-10

Table 14-3. HDLC Receive Address Matching Modes..............................................................................14-13

Table 14-4. UART1 Pin Functionality........................................................................................................14-15

Table 14-5. DeviceCfg Register Bit Functions ..........................................................................................14-15

Table 15-1. UART2 / IrDA Modes ...............................................................................................................15-5

Table 15-2. IonU2 Pin Function...................................................................................................................15-5

Table 16-1. UART3 Pin Functionality..........................................................................................................16-1

Table 16-2. DeviceCfg Register Bit Functions ............................................................................................16-2

Table 17-1. Bit Values to Select Ir Module..................................................................................................17-3

Table 17-2. Address Offsets for End-of-Frame Data...................................................................................17-5

Table 17-3. MIR Frame Format...................................................................................................................17-9

Table 17-4. DeviceCfg.IonU2 Pin Function...............................................................................................17-20

EP93xx User’s Guide

Table 17-5. UART2 / IrDA Modes .............................................................................................................17-21

Table 17-6. IrDA Service Memory Accesses / Second .............................................................................17-22

Table 18-1. Timers Register Map................................................................................................................18-2

Table 19-1. Watchdog Timer Register Memory Map ..................................................................................19-3

Table 20-1. Real Time Clock Register Memory Map ..................................................................................20-4

Table 21-1. I

S Controller Input and Output Signals...................................................................................21-2

Table 21-2. Audio Interfaces Pin Assignment .............................................................................................21-2

Table 21-3. Transmitter FIFO’s...................................................................................................................21-3

Table 21-4. I2SClkDiv SYSCON Register Effect on I

S Clock Generation........ ....... ...... ....... ...... ....... ...... .21-8

Table 21-5. Bit Clock Rate Generation........................................................................................................21-9

Table 21-6. FIFO Flags .............................................................................................................................21-12

Table 21-7. I Table 21-8. I Table 21-9. I

S TX Registers ................................. ....... ...... ....... ...... ...... ....... ...... ....... ...............................21-12

S RX Registers..................................................... ...... ...... ....... ...... ....... ...............................21-19

S Configuration and Status Registers .................................................................................21-25

Table 22-1. AC’97 Input and Output Signals...............................................................................................22-1

Table 22-2. AC’97 Register Memory Map...................................................................................................22-5

Table 22-3. Interaction Between RSIZE and CM ........................................................................................22-9

Table 22-4. Interaction Between RSIZE and CM Bits ...............................................................................22-11

Table 23-1. SSP Register Memory Map Description.................................................................................23-13

Table 24-1. Static Programming Steps .......................................................................................................24-2

Table 24-2. Dynamic Programming Steps ..................................................................................................24-3

Table 24-3. PWM Registers Map................................................................................................................24-3

Table 25-1. Switch Definitions and Logical Safeguards to Prevent Physical Damage................................25-3

Table 25-2. Touch Screen Switch Register Configurations.........................................................................25-7

Table 25-3. External Signal Functions ......................................................................................................25-16

Table 25-4. Analog Touch Screen Register Memory Map........................................................................25-17

Table 26-1. Keypad Interface Register Memory Map..................................................................................26-6

Table 27-1. IDE Host to IDE Interface Definition.........................................................................................27-2

Table 27-2. IDE Cycle Times and Data Transfer Rates.............................................................................. 27-7

Table 27-3. Wait State Value for the DMA M2M Register Control.PWSC ..................................................27-8

Table 27-4. HCLK Cycles to De-assert DMA Request................................................................................27-8

Table 27-5. Maximum Theoretical Bandwidths for Various Operating Modes ............................................27-9

Table 27-6. IDE Interface Register Map....................................................................................................27-10

Table 28-1. EP9301 and EP9302 GPIO Port to Pin Map............................................................................28-6

Table 28-2. EP9307 GPIO Port to Pin Map.................................................................................................28-6

Table 28-3. EP9312 GPIO Port to Pin Map.................................................................................................28-7

Table 28-4. EP9315 GPIO Port to Pin Map.................................................................................................28-8

EP93xx User’s Guide

Table 28-5. GPIO Register Address Map....................................................................................................28-9

Table 29-1. Security Register List ...............................................................................................................29-2

Table 30-1. Glossary...................................................................................................................................30-1

Table 31-1. EP93xx Register List................................................................................................................31-1

Revision History

Revision Date Changes

This is the Initial Release of the EP93xx User's Guide. This manual covers all products in the

UM1

September 14,

2007

EP93xx product family. This manual is based on the content of previous User’s Guides for each of the individual products in the EP93xx family. New content has been added, formatting improved, and all known documentation errors fixed. Please discard previous User’s Guides and rely on this manual for your future reference needs.

P.1 About the EP93xx User’s Guide

This EP93xx User’s Guide describes the architecture, hardwar e, and operation of the Cirrus Logic EP9301, EP9302, EP9307, EP9312, and EP931 5 pr ocessors. It is i ntended t o be used in conjunction with the respective EP93xx Data Sheets, which contain the full electrical specifications for the EP93xx processors.

The EP9301, EP9302, EP9307, EP9312 processors are functional subsets of the EP9315 processor. All chapters in this Guide apply to the EP9315 processor. Most, but not all, chapters apply to the EP9301, EP9302, EP9307, EP9312 processors. Table P-1 shows the maximum core frequency and the maximum high-speed bus frequency as well as number of package balls and package type for the EP93xx processors. Table P-2 shows chapter numbers and function, and which EP93xx processors include the function (or not).

Ta ble P-1. F r eque ncy, Package, Applicable EP93xx Processor

EP9301 EP9302 EP9307 EP9312 EP9315

Chapter P 17Preface

Maximum Core

Frequency - MHz

Maximum High-Speed

Bus Frequency - MHz

Package Type

Table P-2. Chapter Number and Function, Applicable EP93xx Processor

Chapter Number and Function Applicable EP93xx Processor

0: Preface 1: Introduction 2: ARM920T Core and Advanced High-Speed Bus 3: MaverickCrunch Co-processor 4: Boot ROM 5: System Controller X X X X X

166 200 200 200 200

66 100 100 100 100

208 LQFP 208 LQFP 272 TFBGA 352 PBGA 352 PBGA

EP9301 EP9302 EP9307 EP9312 EP9315

X X XXX

- X XXX

X X XXX

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EP93xx User’s Guide

Table P-2. Chapter Number and Function, Applicable EP93xx Processor (Continued)

Chapter Number and Function Applicable EP93xx Processor

EP9301 EP9302 EP9307 EP9312 EP9315 6: Vectored Interrupt Controller X X X X X 7: Raster Engine with Analog and LCD Integrated

Timing and I nterface 8: Graphics Accelerator - - X - X 9: 1/10/100 Mbps Ethernet LAN Controller X X X X X 10: DMA Controller X X X X X 11: Universal Serial Bus Host Controllers 2 2 3 3 3 12: Static Memory Controller

Static Memory Controller with PCMCIA 13: SDRAM, SyncROM, SyncFLASH Controllers X X X X X 14: UART1 with Modem Control Signals and HDLC X X X X X 15: UART2 with IrDA X X X X X 16: UART3 with HDLC - - X X X 17: IrDA X X X X X 18: Timers 4 4 4 4 4 19: Watchdog Timer X X X X X

--XXX

20: Real Time Clock with Softw a re Trim X X X X X

21: I

S Controller 22: AC’97 Controller 1 1 1 1 1 23: Synchronous Serial Port 1 1 1 1 1 24: Pulse Width Modulators 2 2 1 2 2 25: Analog Touch Screen Interface/ADC 5-ADC 5-ADC 8-Wire TS 8-Wire TS 8-Wire TS 26: Keypad Interface - - X X X 27: IDE Interface - - - 2 Devices 2 Devices 28: GPIO Interface 29: Security 30: Glossary

P-2 DS785UM1

3 3 333

X X XXX

Note:“X” means Function is included; “-” means Function is not included

P.2 Related Documents from Cir rus Logic

1. EP9301 Data Sheet, Document Number - DS636PP5

2. EP9302 Data Sheet, Document Number - DS653PP3

3. EP9307 Data Sheet, Document Number - DS667PP4

4. EP9312 Data Sheet, Document Number - DS515PP7

5. EP9315 Data Sheet, Document Number - DS638PP1

P.3 Reference Documents

1. ARM®920T Technical Reference Manual, ARM Limited

2. AMBA Specification (Rev. 2.0), ARM IHI 0011A, ARM Limited

3. AHB Example AMBA System (Addendum 01), ARM DDI 0170A, ARM Limited

Preface

EP93xx User’s Guide

4. The co-processor instruction assembler notation can be referenced from ARM programming manuals or the Quick Reference Card, document number ARM QRC 0001D, ARM Limited

5. The MAC engine is compliant with the requirement s of IS O/IEC 8802-3 (1993), Sections 3 and 4

6. OpenHCI - Open Host Controller interface Specification for USB, Release 1.0a;

Compaq

7. ARM Co-processor Quick Reference Card, document number ARM QRC 0001D, ARM Limited

8. Information Technology, AT Attachment with Packet Interface - 5 (ATA/ATAPI-5) ANSI NCITS document T13 1321D, Revision 3, 29 February 2000

9. ARM PrimeCell PL190-Rel1v1 Revision 1.7 Technical Reference Manual DDI0181C, ARM Limited

10.Audio Codec ‘97, Revision 2.3, April 2002, Intel

, Microsoft®, National Semiconductor

P.4 Notational Conventions

This document uses the following conventions :

Corporation

• Internal and external Signal Names, and Pin Names use mixed upper and lower case alphanumeric, and are shown in bold font, for example, RDLED

• Register Bit Fields are named using upper and lower case alphanumeric: for example, SBOOT, LCSn1

DS785UM1 P-3

Preface

EP93xx User’s Guide

• Registers are named using mixed upper and lower case alphanumeric, for example, SysCfg or PxDDR. Where there are multiple registers with the same names, a lower case “x” is used as a place holder. For example, in the PxDDR registers, x represents a let ter from A to H, indicating the specific port being discussed

CAUTION:In the Internal Register Map in “Internal Register Map” on page 2-17 some

(An example register description is shown below. This description is used for the following examples.)

A specific bit may be specified in one of three ways:

1. Register name[bit number], for example, SysCfg[29]

2. Register name.bit field[bit number], for example, SysCfg.REV[1]

3. Register name.bit field[bit name], for example, SysCfg.SBOOT

Hexidecimal numbers are referred to as 0x0000_0000.

memory locations are listed as Reserved. These memory locations should not be used. Reading from these memory locations will yield invalid data. Writing to these memory locations may cause unpredictable results.

Binary numbers are referred to as 0000_0000b.

P.5 Register Example

Note:This is only an example. For actual SysCfg register information, see “SysCfg” on page 5-

34 .

SysCfg

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

REV RSVD

1514131211109876543210

RSVD SBOOT LCSn7 LCSn6 LASDO LEEDA LEECLK RSVD LCSn2 LCSn1

Address:

0x8093_009C - Read/Write, Softw are locked

Default:

0x0000_0000

Definition:

System Configuration Register. Provides various system configuration options.

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

P-4 DS785UM1

Preface

EP93xx User’s Guide

REV: Revision, reads chip Version number: 0 - Rev A, 1 - Rev B,

2 - Rev C, 3 - Rev D.

SBOOT: Serial Boot Flag. This bit is read-only.

1 hardware detected Serial Boot selection 0 hardware detected Normal Boot

LCSn7, LCSn6: Latched version of CSn7 and CSn6 respectively. These

are used to define the external bus wid t h for the boot code boot.

LASDO: Lat ched ve rsion of ASDO pin. Used to select s ynchr onous

versus asynchronous boot device. LEEDA: Latched version of EEDAT pin. LEECLK: Define Internal or external boot:

1 Internal

0 External LCSn1, LCSn2: Define Watchdog startup action:

0 0 Watchdog disabled, Reset duration disabled

0 1 Watchdog disabled, Reset duration active

1 0 Watchdog active, Reset duration disabled

1 1 Watchdog active, Reset duration active

DS785UM1 P-5

Preface

EP93xx User’s Guide

P-6 DS785UM1

1.1 Introduction

The EP93xx processors are highly integrated systems-on-a-chip that pave the way for a multitude of next-generation consumer and industrial electronic pr oducts. Designers of digit al media servers and jukeboxes, telematic cont rol systems, thin clients, set -top boxes, point-ofsale terminals, industrial controls, biometric security systems, and GPS devices will benefit from the EP93x processors’ integrated architecture and advanced features. In fact, with amazingly agile performance provided by a 166 or 200 MHz ARM920T Core, and featuring an incredibly wide breadth of peripheral interfaces, the EP93xx processors are well suited to an even broader range of high volume app lications. Furthermore, by ena bling or disabli ng the EP93xx processor’s peripherals and their interf aces, designers can throttle power consumption and reduce development costs and accelerate time-to-market by creating a single platform that can be easily modified to deliver a variety of differentiated end products.

1.2 EP93xx Features

Chapter 1

1Introduction

Maximum clock rates plus package types and number of balls for EP93xx processors are shown in Table 1-1.

Table 1-1. EP93xx Maximum Clock Rates, Package Type and Number of Balls

Processor Max Core Clock Rate

EP9301 EP9302 EP9307 EP9312 EP9315

Features of the EP93xx process ors are summarized in Table 1-2. Block diagrams are shown in Figure 1-1 EP9301, Figure 1-2 EP9302, Figure 1-3 EP9307, Figure 1-4 EP9312, and

Figure 1-5 EP9315.

166 MHz 66 MHz 208 LQFP

200 MHz 100 MHz 208 LQFP

200 MHz 100 MHz 272 TFBGA

200 MHz 100 MHz 352 PBGA

Max High-Speed Bus

Clock Rate

Package

DS785UM1 1-1

Introduction

EP93xx User’s Guide

Table 1-2. EP93xx Features Summary

Processor

EP9301 X - - - - X - 2 2 5-ADC 37 -

EP9302 X - X - - X - 2 2 5-ADC 37 -

EP9307 - X X X X X - 3 3

EP9312 - X X X - X 1 3 3

EP9315 - X X X X X 1 3 3

16-Bit

External

Bus

32-Bit

External

Bus

Math Co-

Processor

Raster

Analog /

LCD

2-D

Graphics

Accelerator

Ethernet

MAC

IDE

USB 2.0

Host

UART

Touch

Screen

/ ADC

8-Wire/

12-

ADC

8-Wire/

12-

ADC

8-Wire/

12-

ADC

GPIO

48 -

47 -

55 X

Note:“X” means that the function is included; “-” means that the function is not included.

UART2 with IrDA

UART1 with HDLC

System Control –

2 PLLs

Card

SDRAM

SRAM, FLASH,

ROM

12 Channel DMA

1/10/100 Ethernet

MAC

JTAG

2 USB 2.0 FS Host

Boot ROM

Vectored Inerrupts

ARM920T

I-Cache

16 KB

Memory Management Unit

High-Speed Bus (AHB)

AHB/APB Bridge

Figure 1-1. EP9301 Block Diagram

D-Cache

16 KB

Peripheral Bus (APB)

5-Channel ADC

2 PWM

Enhanced GPIO,

2-wire, 2 LED

I2S

SPI

AC’97

RTC with SW Trim

Watchdog Timer

4 Timers

1-2 DS785UM1

+ 794 hidden pages

Cirrus Logic EP93xx User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Figures

Tables

Revision History

P.1 About the EP93xx User’s Guide

Chapter P 17Preface

P.2 Related Documents from Cir rus Logic

P.3 Reference Documents

P.4 Notational Conventions

P.5 Register Example

1.1 Introduction

1.2 EP93xx Features

1Introduction