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Cirrus Logic EP9315 User's Guide

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EP9315 User’s Guide

http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
FEB ‘04
DS638UM1
Revision Date Changes
1 February 2004 Initial Release
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterizati on data is not yet avai lable. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the i nformati on contained in this document is accurate and reliabl e. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest versi on of r elevant information to verify, before placing orders, that informati on being relied on is current and complete. All products are sold subject to the terms and condi tions of sale supplied at the ti me of order acknowledgment, incl uding those pertai ning to warrant y, patent infringement, and limitatio n of liabili ty. No responsi bility is assumed by Cirr us for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Ci rrus and by furni shing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, tr ademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gi ves consent for copies to be made of the information onl y for use with in your organizat ion with respect to Ci rrus integra ted circuit s or other product s of Cirrus. This consent does not extend to other copying such as copying for general distr ibution, advertisi ng or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USI NG SEMI CONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANT­ED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PROD­UCTS OR OTHER CRITICAL APPLICATIONS ( INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). I NCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA­TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTH­ER AGENTS FROM ANY AND ALL LIABILITY, I NCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE I N CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
Microsoft and Windows are registered trademarks of Microsoft Corporation. MicrowireTM is a trademark of National Semiconductor Corp. Nati onal Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola is a registered trademark of Motorola, Inc. LINUX is a registered trademark of Linus Torval ds.
Copyright 2004 Cirrus Logic

About the EP9315 User’s Guide

This Guide describes the architecture, hardware, and operation of the Cirrus Logic EP9315. It is intended to be used in conjunction with the EP9315 Datasheet, which contains the full electrical specifications for the device.

How to Use this Guide

Subject Matter Location
AC’97 Chapter 22 - AC’97 Controller
ARM920T Processor
Boot ROM, Hardware and Software Chapter 4 - Boot ROM
Booting From SROM or SyncFlash Chapter 13 - SDRAM, SyncROM, and SyncFLASH Controller
Buses - AMBA, AHB, APB
Coprocessor Unit Chapter 3 - MaverickCrunch Coprocessor
DMA Controller Chapter 10 - DMA Controller
EP9315 Block Diagram
Ethernet Chapter 9 - 1/10/100 Mbps Ethernet LAN Controller
GPIO Chapter 28 - GPIO Interface
Graphics Accelerator Chapter 8 - Graphics Accelerator
HDLC
2
I
S
IDE Chapter 27 - IDE Interface
Infra-Red Interface Chapter 17 - IrDA
Interrupt Registers Chapter 6 - Vectored Interrupt Controller
Interrupts Chapter 6 - Vectored Interrupt Controller
IrDA Chapter 17 - IrDA
Key Pad Matrix Chapter 26 - Keypad Interface
LCD Interface
MAC Chapter 9 - 1/10/100 Mbps Ethernet LAN Controller
Chapter 2 - ARM920T Core and Advanced High-Speed Bus (AHB)
Chapter 2 - ARM920T Core and Advanced High-Speed Bus (AHB)
Chapter 2 - ARM920T Core and Advanced High-Speed Bus (AHB)
Chapter 14 - UART1 With HDLC and Modem Control Signals Chapter 16 - UART3 With HDLC Encoder
Chapter 21 - I2S Controller
Chapter 7 - Raster Engine With Analog/LCD Integrated Timing and Interface

Preface

EP9315 User’s Manual - DS638UM1 3 Copyright 2004 Cirrus Logic
Subject Matter Location
Memory Map
Modem Chapter 14 - UART1 With HDLC and Modem Control Signals
PCMCIA Chapter 12 - Static Memory Controller
Power Management Chapter 5 - System Controller
Programming Clocks Chapter 5 - System Controller
PWM Chapter 24 - Pulse Width Modulator
Raster Graphics
Real Time Clock Chapter 20 - Real Time Clock With Software Trim
Register List Chapter 1 - Introduction
RTC Chapter 20 - Real Time Clock With Software Trim
SDRAM Chapter 13 - SDRAM, SyncROM, and SyncFLASH Controller
Security Chapter 29 - Security
SMC Chapter 12 - Static Memory Controller
SSP Chapter 23 - Synchronous Serial Port
Static Memory Controller Chapter 12 - Static Memory Controller
System Configuration Chapter 5 - System Controller
System Registers Chapter 5 - System Controller
Timers Chapter 18 - Timers
Touch Screen Chapter 25 - Analog Touch Screen Interface
UART
USB Chapter 11 - Universal Serial Bus Host Controller
Vectored Interrupt Registers Chapter 6 - Vectored Interrupt Controller
Vectored Interrupts Chapter 6 - Vectored Interrupt Controller
Watchdog Timer Chapter 19 - Watchdog Timer
Chapter 2 - ARM920T Core and Advanced High-Speed Bus (AHB)
Chapter 7 - Raster Engine With Analog/LCD Integrated Timing and Interface
Chapter 14 - UART1 With HDLC and Modem Control Signals Chapter 15 - UART2 Chapter 16 - UART3 With HDLC Encoder

Related Documents from Cirrus Logic

1. EP9315 Data Sheet, Document Number - DS638PP1

Reference Documents

1. ARM920T Technical Reference Manual
2. AMBA Specification (Rev. 2.0), ARM IHI 0011A, ARM Limited.
Copyright 2004 Cirrus Logic
3. AHB Example AMBA System (Addendum 01), ARM DDI 0170A, ARM Limited.
4. The coprocessor instruction assembler notation can be referenced from ARM programming manuals or the Quick Reference Card, document number ARM QRC 0001D.
5. The MAC engine is compliant with the requirements of ISO/IEC 8802-3 (1993), Sections 3 and 4.
6. OpenHCI - Open Host Controller interface Specification for USB, Release
1.0a; Compaq, Microsoft, National Semiconductor.
7. ARM Coprocessor Quick Reference Card, document number ARM QRC 0001D.
8. Information Technology, AT Attachment with Packet Interface - 5 (ATA/ATAPI-5) ANSI NCITS document T13 1321D, Revision 3, 29 February 2000
9. OpenHCI - Open Host Controller Interface Specification for USB, Release: 1.0a, Released - 09/14/99 2:33 PM
10. ARM PrimeCell PL190-Rel1v1 Revision 1.7 Technical Reference Manual DDI0181C
11. Audio Codec ‘97, Revision 2.3, April 2002, Intel Corporation

Notational Conventions

This document uses the following conventions:
• Internal and external Signal Names, and Pin Names use mixed upper and lower case alphanumeric, and are shown in bold font: RDLED.
• Register Bit Fields are named using upper and lower case alphanumeric: that is, SBOOT, LCSn1.
• Registers are named using mixed upper and lower case alphanumeric: that is, SysCfg or PxDDR. (Where there are multiple registers with similar names, a lower case “x” is used as a place holder. For example, in the PxDDR registers, x represents a letter between A and H, indicating the specific port being discussed.)
Caution: In the Internal Register Map in Table 2-7 on page 7-53, some
memory locations are listed as Reserved. These memory locations should not be used. Reading from these memory locations will yield invalid data. Writing to these memory locations may cause unpredictable results.
(An example register description is shown below. This description is used for the following examples.)
EP9315 User’s Manual - DS638UM1 5 Copyright 2004 Cirrus Logic
A specific bit may be specified in one of two ways:
By
register name[bit number]
or by
register name.bit field[bit number]
:
SysCfg[29]
Both of these representations refer to the same bit.
The following:
,
:
SysCfg.REV[1]
SysCfg[8]
, or
SysCfg.SBOOT
also refer to the same bit.
Hexidecimal numbers are referred to as
Binary numbers are referred to as
0x0000_0000
0000_0000b
.
.
Register Example
Note: This is only and example. For actual SysCfg register information, see “SysCfg”
on page 162.
SysCfg
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD SBOOT LCSn7 LCSn6 LASDO LEEDA LEECLK RSVD LCSn2 LCSn1
Address:
0x8093_009C - Read/Write, Software locked
Default:
0x0000_0000
Definition:
System Configuration Register. Provides various system configuration options.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
REV: Revision, reads chip Version number: 0 - Rev A, 1 - Rev B,
2 - Rev C, 3 - Rev D.
SBOOT: Serial Boot Flag. This bit is read-only.
1 hardware detected Serial Boot selection, 0 hardware detected Normal Boot.
Copyright 2004 Cirrus Logic
LCSn7, LCSn6: Latched version of CSn7 and CSn6 respectively. These
are used to define the external bus width for the boot code boot.
LASDO: Latched version of ASDO pin. Used to select synchronous
versus asynchronous boot device.
LEEDA: Latched version of EEDAT pin.
LEECLK: Define Internal or external boot:
1 Internal 0 External
LCSn2, LCSn1: Define Watchdog startup action:
0 0 Watchdog disabled, Reset duration disabled 0 1 Watchdog disabled, Reset duration active 1 0 Watchdog active, Reset duration disabled 1 1 Watchdog active, Reset duration active
EP9315 User’s Manual - DS638UM1 7 Copyright 2004 Cirrus Logic
This page intentionally blank.
Copyright 2004 Cirrus Logic

Table of Contents

Preface............................................................................................................. 3
About the EP9315 User’s Guide ............................................................................................................ 3
How to Use this Guide ...........................................................................................................................3
Related Documents from Cirrus Logic ...................................................................................................4
Reference Documents ...........................................................................................................................4
Notational Conventions ..........................................................................................................................5
Chapter 1 Introduction ............................................................................... 29
1.1 Introduction ...................................................................................................................................29
1.2 EP9315 Features ..........................................................................................................................30
1.3 EP9315 Applications .....................................................................................................................31
1.4 Overview of EP9315 Features ......................................................................................................32
1.4.1 High-Performance ARM920T Processor Core ....................................................................32
1.4.2 MaverickCrunch™ Coprocessor for Ultra-Fast Math Processing........................................32
1.4.3 MaverickKey™ Unique ID Secures Digital Content and OEM Designs ..............................32
1.4.4 Integrated Three-port USB 2.0 Full Speed Host with Transceivers.....................................33
1.4.5 Integrated Ethernet MAC Reduces BOM Costs ..................................................................33
1.4.6 8x8 Keypad Interface Reduces BOM Costs ........................................................................33
1.4.7 Multiple Booting Mechanisms Increase Flexibility ...............................................................33
1.4.8 Abundant General Purpose I/Os Build Flexible Systems ....................................................34
1.4.9 General-Purpose Memory Interface (SDRAM, SRAM, ROM and FLASH) .........................34
1.4.10 12-Bit Analog-to-Digital Converter (ADC) Provides an Integrated
Touch-Screen Interface or General ADC Functionality..............................................34
1.4.11 Graphics Accelerator .........................................................................................................34
1.4.12 PCMCIA Interface..............................................................................................................34
Chapter 2 ARM920T Core and Advanced High-Speed Bus (AHB) ......... 35
2.1 Introduction ...................................................................................................................................35
2.2 Overview: ARM920T Processor Core ...........................................................................................35
2.2.1 Features ..............................................................................................................................35
2.2.2 Block Diagram .....................................................................................................................36
2.2.3 Operations...........................................................................................................................36
2.2.3.1 ARM9TDMI Core........................................................................................................37
2.2.3.2 Memory Management Unit .........................................................................................38
2.2.3.3 Cache and Write Buffer..............................................................................................39
2.2.4 Coprocessor Interface .........................................................................................................40
2.2.5 AMBA AHB Bus Interface Overview....................................................................................41
2.2.6 EP9315 AHB Implementation Details..................................................................................42
2.2.7 Memory and Bus Access Errors ..........................................................................................43
2.2.8 Bus Arbitration .....................................................................................................................44
2.2.8.1 Main AHB Bus Arbiter ................................................................................................44
2.2.8.2 SDRAM Slave Arbiter.................................................................................................45
2.2.8.3 EBI Bus Arbiter...........................................................................................................45
2.3 AHB Decoder ................................................................................................................................45
2.3.1 AHB Bus Slave ....................................................................................................................46
2.3.2 AHB to APB Bridge..............................................................................................................46
2.3.2.1 Function and Operation of APB Bridge......................................................................46
2.3.3 APB Bus Slave ....................................................................................................................47
EP9315 User’s Manual - DS638UM1 9 Copyright 2004 Cirrus Logic
2.3.4 Register Definitions............................................................................................................. 47
2.3.5 Memory Map ....................................................................................................................... 51
2.3.6 Internal Register Map.......................................................................................................... 52
2.3.6.1 Memory Access Rules............................................................................................... 52
Chapter 3 MaverickCrunch Coprocessor ................................................. 69
3.1 Introduction ................................................................................................................................... 69
3.1.1 Features.............................................................................................................................. 69
3.1.2 Operational Overview.......................................................................................................... 69
3.1.3 Pipelines and Latency......................................................................................................... 71
3.1.4 Data Registers .................................................................................................................... 71
3.1.5 Integer Saturation Arithmetic............................................................................................... 72
3.1.6 Comparisons....................................................................................................................... 74
3.2 Programming Examples ............................................................................................................... 75
3.2.1 Example 1 ........................................................................................................................... 75
3.2.1.1 Setup Code................................................................................................................ 76
3.2.1.2 C Code ...................................................................................................................... 76
3.2.1.3 Accessing MaverickCrunch with ARM Coprocessor Instructions .............................. 76
3.2.1.4 MaverickCrunch Assembly Language Instructions.................................................... 76
3.2.2 Example 2 ........................................................................................................................... 76
3.2.2.1 C Code ...................................................................................................................... 77
3.2.2.2 MaverickCrunch Assembly Language Instructions.................................................... 77
3.3 DSPSC Register........................................................................................................................... 78
3.4 ARM Coprocessor Instruction Format .......................................................................................... 81
3.5 Instruction Set for the MaverickCrunch Coprocessor ................................................................... 86
3.5.1 Load and Store Instructions ................................................................................................ 90
3.5.2 Move Instructions................................................................................................................ 94
3.5.3 Accumulator and DSPSC Move Instructions....................................................................... 98
3.5.4 Copy and Conversion Instructions .................................................................................... 102
3.5.5 Shift Instructions................................................................................................................ 106
3.5.6 Compare Instructions........................................................................................................ 108
3.5.7 Floating Point Arithmetic Instructions................................................................................ 110
3.5.8 Integer Arithmetic Instructions........................................................................................... 114
3.5.9 Accumulator Arithmetic Instructions.................................................................................. 118
Chapter 4 Boot ROM ................................................................................. 121
4.1 Introduction ................................................................................................................................. 121
4.1.1 Boot ROM Hardware Operational Overview ..................................................................... 121
4.1.1.1 Memory Map............................................................................................................ 121
4.1.2 Boot ROM Software Operational Overview....................................................................... 121
4.1.2.1 Image Header .......................................................................................................... 122
4.1.2.2 Boot Algorithm .........................................................................................................122
4.1.2.3 Flowchart................................................................................................................. 124
4.2 Boot Options............................................................................................................................... 125
4.2.1 UART Boot........................................................................................................................ 125
4.2.2 SPI Boot............................................................................................................................ 126
4.2.3 FLASH Boot ...................................................................................................................... 126
4.2.4 SDRAM or SyncFLASH Boot............................................................................................ 127
Copyright 2004 Cirrus Logic
4.2.5 Synchronous Memory Operation.......................................................................................127
Chapter 5 System Controller ................................................................... 129
5.1 Introduction .................................................................................................................................129
5.1.1 System Startup ..................................................................................................................129
5.1.2 System Reset ....................................................................................................................129
5.1.3 Hardware Configuration Control ........................................................................................130
5.1.4 Software System Configuration Options............................................................................132
5.1.5 Clock Control..................................................................................................................... 132
5.1.5.1 Oscillators and Programmable PLLs........................................................................132
5.1.5.2 Bus and Peripheral Clock Generation......................................................................133
5.1.5.3 Steps for Clock Configuration ..................................................................................137
5.1.6 Power Management ..........................................................................................................138
5.1.6.1 Clock Gatings...........................................................................................................138
5.1.6.2 System Power States...............................................................................................138
5.1.7 Interrupt Generation ..........................................................................................................140
5.2 Registers.....................................................................................................................................142
Chapter 6 Vectored Interrupt Controller................................................. 165
6.1 Introduction .................................................................................................................................165
6.1.1 Interrupt Priority.................................................................................................................166
6.1.2 Interrupt Descriptions ........................................................................................................168
6.2 Registers.....................................................................................................................................173
Chapter 7 Raster Engine With Analog/LCD Integrated Timing and
Interface....................................................................................................... 183
7.1 Introduction .................................................................................................................................183
7.2 Features......................................................................................................................................185
7.3 Raster Engine Features Overview ..............................................................................................185
7.3.1 Hardware Blinking .............................................................................................................185
7.3.2 Color Look-Up Tables........................................................................................................186
7.3.3 Grayscale/Color Generation for Monochrome/Passive Low Color Displays ..................... 186
7.3.4 Frame Buffer Organization ................................................................................................186
7.3.5 Frame Buffer Memory Size................................................................................................188
7.3.6 Pulse Width Modulated Brightness....................................................................................188
7.3.7 Hardware Cursor ...............................................................................................................189
7.4 Functional Details........................................................................................................................190
7.4.1 VILOSATI (Video Image Line Output Scanner and Transfer Interface) ............................ 190
7.4.2 Video FIFO ........................................................................................................................ 192
7.4.3 Video Pixel MUX................................................................................................................192
7.4.4 Blink Function .................................................................................................................... 192
7.4.5 Color Look-Up-Tables .......................................................................................................193
7.4.6 Color RGB Mux .................................................................................................................194
7.4.7 Pixel Shift Logic................................................................................................................. 194
7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays .......................198
7.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters ....................................................................199
7.4.8.2 VERT_CNT3, VERT_CNT4 Counters......................................................................199
7.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters................................................................199
EP9315 User’s Manual - DS638UM1 11 Copyright 2004 Cirrus Logic
7.4.8.4 HORZ_CNTx (pixel) timing...................................................................................... 199
7.4.8.5 VERT_CNTx (line) timing ........................................................................................ 199
7.4.8.6 FRAME_CNTx timing .............................................................................................. 199
7.4.8.7 Grayscale Look-Up Table (GrySclLUT)................................................................... 200
7.4.8.8 GrySclLUT Timing Diagram..................................................................................... 201
7.4.9 Hardware Cursor............................................................................................................... 210
7.4.9.1 Registers Used for Cursor ....................................................................................... 212
7.4.10 Video Timing ................................................................................................................... 213
7.4.10.1 Setting the Video Memory Parameters.................................................................. 216
7.4.10.2 PixelMode.............................................................................................................. 218
7.4.11 Blink Logic....................................................................................................................... 218
7.4.11.1 BlinkRate ............................................................................................................... 218
7.4.11.2 Defining Blink Pixels .............................................................................................. 219
7.4.11.3 Types of Blinking ................................................................................................... 219
7.4.12 Color Mode Definition...................................................................................................... 221
7.4.12.1 Pixel Look-up Table............................................................................................... 221
7.4.12.2 Triple 8-bit Mode.................................................................................................... 222
7.4.12.3 16-bit 565 Mode..................................................................................................... 222
7.4.12.4 16-bit 555 Mode..................................................................................................... 222
7.5 Registers .................................................................................................................................... 223
Chapter 8 Graphics Accelerator .............................................................. 265
8.1 Overview..................................................................................................................................... 265
8.2 Block Processing Modes ............................................................................................................ 265
8.2.1 Copy.................................................................................................................................. 265
8.2.2 Transparency .................................................................................................................... 266
8.2.3 Logical Mask ..................................................................................................................... 266
8.2.3.1 Logical Destination .................................................................................................. 266
8.2.3.2 Operation Precedence............................................................................................. 266
8.2.4 Remapping........................................................................................................................ 267
8.2.5 Block Fills .......................................................................................................................... 267
8.2.6 Packed Memory Transfer.................................................................................................. 267
8.3 Line Draws.................................................................................................................................. 267
8.3.1 Breshenham Line Draws................................................................................................... 268
8.3.2 Pixel Step Line Draws....................................................................................................... 268
8.4 Memory Organization for Graphics Accelerator ......................................................................... 268
8.4.1 Memory Organization for 1 Bit Per Pixel (bpp)................................................................. 269
8.4.2 Memory Organization for 4 Bit Per Pixel ........................................................................... 269
8.4.3 Memory Organization for 8 Bit Per Pixel ........................................................................... 269
8.4.4 Memory Organization for 24 Bit Per Pixel ......................................................................... 271
8.5 Register Programming................................................................................................................ 272
8.6 Word Count ................................................................................................................................ 272
8.6.1 Example: 8 BPP mode...................................................................................................... 273
8.6.2 Example: 24 BPP (packed) mode..................................................................................... 273
8.7 Pixel End and Start..................................................................................................................... 274
8.7.1 4 BPP mode ...................................................................................................................... 274
8.7.1.1 4 BPP Word Layout ................................................................................................. 274
8.7.1.2 8 BPP Word Layout ................................................................................................. 275
Copyright 2004 Cirrus Logic
8.7.1.3 16 BPP WORD Layout.............................................................................................275
8.7.1.4 24 BPP mode ...........................................................................................................275
8.8 Register Usage ...........................................................................................................................276
8.8.1 Line (Bresenham’s Algorithm) ...........................................................................................276
8.8.2 DX/DY Line Draw Function................................................................................................278
8.8.3 Block Fill ............................................................................................................................279
8.8.4 Block Copy ........................................................................................................................ 280
8.8.4.1 Source Memory Setup .............................................................................................280
8.8.4.2 Destination Memory Setup.......................................................................................280
8.9 Registers ....................................................................................................................................282
Chapter 9 1/10/100 Mbps Ethernet LAN Controller ............................... 297
9.1 Introduction .................................................................................................................................297
9.1.1 Detailed Description ..........................................................................................................297
9.1.1.1 Host Interface and Descriptor Processor .................................................................297
9.1.1.2 Reset and Initialization ............................................................................................. 298
9.1.1.3 Powerdown Modes...................................................................................................298
9.1.1.4 Address Space.........................................................................................................299
9.1.2 MAC Engine ......................................................................................................................299
9.1.2.1 Data Encapsulation..................................................................................................299
9.1.3 Packet Transmission Process ...........................................................................................300
9.1.3.1 Carrier Deference.....................................................................................................301
9.1.4 Transmit Back-Off..............................................................................................................303
9.1.4.1 Transmission............................................................................................................303
9.1.4.2 The FCS Field..........................................................................................................304
9.1.4.3 Bit Order...................................................................................................................304
9.1.4.4 Destination Address (DA) Filter................................................................................304
9.1.4.5 Perfect Address Filtering..........................................................................................304
9.1.4.6 Hash Filter................................................................................................................305
9.1.4.7 Flow Control .............................................................................................................306
9.1.4.8 Receive Flow Control...............................................................................................306
9.1.4.9 Transmit Flow Control ..............................................................................................307
9.1.4.10 Rx Missed and Tx Collision Counters....................................................................307
9.1.4.11 Accessing the MII...................................................................................................308
9.2 Descriptor Processor...................................................................................................................309
9.2.1 Receive Descriptor Processor Queues .............................................................................309
9.2.2 Receive Descriptor Queue ................................................................................................310
9.2.3 Receive Status Queue.......................................................................................................312
9.2.3.1 Receive Status Format.............................................................................................315
9.2.3.2 Receive Flow............................................................................................................318
9.2.3.3 Receive Errors .........................................................................................................319
9.2.3.4 Receive Descriptor Data/Status Flow ......................................................................320
9.2.3.5 Receive Descriptor Example....................................................................................321
9.2.3.6 Receive Frame Pre-Processing ...............................................................................321
9.2.3.7 Transmit Descriptor Processor.................................................................................322
9.2.3.8 Transmit Descriptor Queue ......................................................................................322
9.2.3.9 Transmit Descriptor Format .....................................................................................325
EP9315 User’s Manual - DS638UM1 13 Copyright 2004 Cirrus Logic
9.2.3.10 Transmit Status Queue.......................................................................................... 326
9.2.3.11 Transmit Status Format......................................................................................... 328
9.2.3.12 Transmit Flow ........................................................................................................ 330
9.2.3.13 Transmit Errors...................................................................................................... 331
9.2.3.14 Transmit Descriptor Data/Status Flow................................................................... 332
9.2.4 Interrupts........................................................................................................................... 333
9.2.4.1 Interrupt Processing ................................................................................................ 333
9.2.5 Initialization ....................................................................................................................... 333
9.2.5.1 Interrupt Processing ................................................................................................ 334
9.2.5.2 Receive Queue Processing ..................................................................................... 334
9.2.5.3 Transmit Queue Processing .................................................................................... 334
9.2.5.4 Other Processing..................................................................................................... 335
9.2.5.5 Transmit Restart Process ........................................................................................ 335
9.3 Registers .................................................................................................................................... 337
Chapter 10 DMA Controller ...................................................................... 391
10.1 Introduction............................................................................................................................... 391
10.1.1 DMA Features List .......................................................................................................... 391
10.1.2 Managing Data Transfers Using a DMA Channel ........................................................... 392
10.1.3 DMA Operations.............................................................................................................. 394
10.1.3.1 Memory-to-Memory Channels ............................................................................... 394
10.1.3.2 Memory-to-Peripheral Channels............................................................................ 395
10.1.4 Internal M2P or P2M AHB Master Interface Functional Description ............................... 395
10.1.5 M2M AHB Master Interface Functional Description ........................................................ 396
10.1.5.1 Software Trigger Mode .......................................................................................... 396
10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and
for External Peripherals without Handshaking Signals ..................................................... 396
10.1.5.3 Hardware Trigger Mode for External Peripherals with Handshaking Signals ........ 397
10.1.6 AHB Slave Interface Limitations...................................................................................... 397
10.1.7 Interrupt Interface............................................................................................................ 397
10.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description.................................. 397
10.1.9 Internal M2P/P2M DMA Functional Description.............................................................. 398
10.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine................................ 398
10.1.9.2 Data Transfer Initiation and Termination ............................................................... 400
10.1.10 M2M DMA Functional Description................................................................................. 401
10.1.10.1 M2M DMA Control Finite State Machine ............................................................. 401
10.1.10.2 M2M Buffer Control Finite State Machine............................................................ 403
10.1.10.3 Data Transfer Initiation ........................................................................................ 405
10.1.10.4 Data Transfer Termination................................................................................... 407
10.1.10.5 Memory Block Transfer ....................................................................................... 408
10.1.10.6 Bandwidth Control ............................................................................................... 408
10.1.10.7 External Peripheral DMA Request (DREQ) Mode ............................................... 408
10.1.11 DMA Data Transfer Size Determination........................................................................ 410
10.1.11.1 Software Initiated M2M and M2P/P2M Transfers ................................................ 410
10.1.11.2 Hardware Initiated M2M Transfers ...................................................................... 410
10.1.12 Buffer Descriptors ......................................................................................................... 411
10.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors .............................................. 411
Copyright 2004 Cirrus Logic
10.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors ...............................................411
10.1.12.3 M2M Channel Buffer Descriptors .........................................................................411
10.1.13 Bus Arbitration...............................................................................................................411
10.2 Registers...................................................................................................................................413
10.2.1 DMA Controller Memory Map..........................................................................................413
10.2.2 Internal M2P/P2M Channel Register Map .......................................................................413
Chapter 11 Universal Serial Bus Host Controller .................................. 441
11.1 Introduction ...............................................................................................................................441
11.1.1 Features ..........................................................................................................................441
11.2 Overview ...................................................................................................................................441
11.2.1 Data Transfer Types........................................................................................................442
11.2.2 Host Controller Interface..................................................................................................443
11.2.2.1 Communication Channels ......................................................................................443
11.2.2.2 Data Structures ......................................................................................................444
11.2.3 Host Controller Driver Responsibilities ............................................................................446
11.2.3.1 Host Controller Management .................................................................................446
11.2.3.2 Bandwidth Allocation..............................................................................................446
11.2.3.3 List Management....................................................................................................447
11.2.3.4 Root Hub................................................................................................................448
11.2.4 Host Controller Responsibilities.......................................................................................448
11.2.4.1 USB States.............................................................................................................448
11.2.4.2 Frame management...............................................................................................448
11.2.4.3 List Processing.......................................................................................................448
11.2.5 USB Host Controller Blocks.............................................................................................449
11.2.5.1 AHB Slave..............................................................................................................449
11.2.5.2 AHB Master............................................................................................................449
11.2.5.3 HCI Slave Block .....................................................................................................449
11.2.5.4 HCI Master Block ...................................................................................................450
11.2.5.5 USB State Control..................................................................................................450
11.2.5.6 Data FIFO ..............................................................................................................450
11.2.5.7 List Processor ........................................................................................................450
11.2.5.8 Root Hub and Host SIE..........................................................................................450
11.3 Registers...................................................................................................................................451
Chapter 12 Static Memory Controller ..................................................... 479
12.1 Introduction ...............................................................................................................................479
12.2 Static Memory Controller Operation..........................................................................................480
12.3 Byte Lane Write / Read Control ................................................................................................482
12.4 PCMCIA Interface Signals ........................................................................................................483
12.5 PCMCIA Card Memory Mode Enable Signals ..........................................................................484
12.6 PCMCIA Card Memory Mapping...............................................................................................485
12.7 Registers...................................................................................................................................489
Chapter 13 SDRAM, SyncROM, and SyncFLASH Controller................ 495
13.1 Introduction ...............................................................................................................................495
13.1.1 Booting (from SROM or SyncFLASH) .............................................................................495
13.1.1.1 Address Pin Usage ................................................................................................496
EP9315 User’s Manual - DS638UM1 15 Copyright 2004 Cirrus Logic
13.1.1.2 SDRAM Initialization.............................................................................................. 498
13.1.1.3 Programming External Device Mode Register....................................................... 499
13.1.1.4 SDRAM Self Refresh............................................................................................. 502
13.1.1.5 SROM and SyncFlash ........................................................................................... 502
13.1.1.6 External Synchronous Memory System................................................................. 503
13.2 Registers .................................................................................................................................. 507
Chapter 14 UART1 With HDLC and Modem Control Signals ................ 515
14.1 Introduction............................................................................................................................... 515
14.2 UART Overview........................................................................................................................ 515
14.2.1 UART Functional Description.......................................................................................... 516
14.2.1.1 AMBA APB Interface ............................................................................................. 516
14.2.1.2 DMA Block.............................................................................................................516
14.2.1.3 Register Block ....................................................................................................... 517
14.2.1.4 Baud Rate Generator ............................................................................................ 518
14.2.1.5 Transmit FIFO ....................................................................................................... 518
14.2.1.6 Receive FIFO ........................................................................................................ 518
14.2.1.7 Transmit Logic ....................................................................................................... 518
14.2.1.8 Receive Logic ........................................................................................................ 518
14.2.1.9 Interrupt Generation Logic ..................................................................................... 518
14.2.1.10 Synchronizing Registers and Logic ..................................................................... 519
14.2.2 UART Operation.............................................................................................................. 519
14.2.2.1 Error Bits................................................................................................................ 520
14.2.2.2 Disabling the FIFOs............................................................................................... 520
14.2.2.3 System/diagnostic Loopback Testing .................................................................... 520
14.2.2.4 UART Character Frame......................................................................................... 520
14.2.3 Interrupts......................................................................................................................... 521
14.2.3.1 UARTMSINTR....................................................................................................... 521
14.2.3.2 UARTRXINTR ....................................................................................................... 521
14.2.3.3 UARTTXINTR........................................................................................................ 522
14.2.3.4 UARTRTINTR........................................................................................................ 522
14.2.3.5 UARTINTR ............................................................................................................ 522
14.3 Modem...................................................................................................................................... 522
14.4 HDLC........................................................................................................................................ 523
14.4.1 Overview of HDLC Modes............................................................................................... 523
14.4.2 Selecting HDLC Modes................................................................................................... 524
14.4.3 HDLC Transmit ............................................................................................................... 525
14.4.4 HDLC Receive ................................................................................................................ 526
14.4.5 CRCs............................................................................................................................... 527
14.4.6 Address Matching ........................................................................................................... 527
14.4.7 Aborts.............................................................................................................................. 528
14.4.8 DMA ................................................................................................................................ 528
14.4.9 Writing Configuration Registers ...................................................................................... 529
14.5 UART1 Package Dependency..................................................................................................529
14.5.1 Clocking Requirements ...................................................................................................530
14.5.2 Bus Bandwidth Requirements......................................................................................... 530
14.6 Registers .................................................................................................................................. 532
Copyright 2004 Cirrus Logic
Chapter 15 UART2 .................................................................................... 553
15.1 Introduction ...............................................................................................................................553
15.2 IrDA SIR Block..........................................................................................................................553
15.2.1 IrDA SIR Encoder/decoder Functional Description .........................................................553
15.2.1.1 IrDA SIR Transmit Encoder....................................................................................554
15.2.1.2 IrDA SIR Receive Decoder ....................................................................................554
15.2.2 IrDA SIR Operation..........................................................................................................555
15.2.2.1 System/diagnostic Loopback Testing.....................................................................556
15.2.3 IrDA Data Modulation ......................................................................................................556
15.2.4 Enabling Infrared (Ir) Modes ............................................................................................557
15.3 UART2 Package Dependency ..................................................................................................557
15.3.1 Clocking Requirements ...................................................................................................557
15.3.2 Bus Bandwidth Requirements .........................................................................................558
15.4 Registers...................................................................................................................................559
Chapter 16 UART3 With HDLC Encoder ................................................. 571
16.1 Introduction ...............................................................................................................................571
16.2 Implementation Details..............................................................................................................571
16.2.1 UART3 Package Dependency.........................................................................................571
16.2.2 Clocking Requirements ...................................................................................................572
16.2.3 Bus Bandwidth Requirements .........................................................................................572
16.3 Registers...................................................................................................................................573
Chapter 17 IrDA ........................................................................................ 591
17.1 Introduction ...............................................................................................................................591
17.2 IrDA Interfaces ..........................................................................................................................591
17.3 Shared IrDA Interface Feature..................................................................................................592
17.3.1 Overview..........................................................................................................................592
17.3.2 Functional Description .....................................................................................................592
17.3.2.1 General Configuration ............................................................................................593
17.3.2.2 Transmitting Data................................................................................................... 593
17.3.2.3 Receiving Data.......................................................................................................596
17.3.2.4 Special Conditions .................................................................................................598
17.3.3 Control Information Buffering...........................................................................................598
17.4 Medium IrDA Specific Features ................................................................................................599
17.4.1 Introduction ......................................................................................................................599
17.4.1.1 Bit Encoding...........................................................................................................599
17.4.1.2 Frame Format ........................................................................................................599
17.4.2 Functional Description .....................................................................................................601
17.4.2.1 Baud Rate Generation ...........................................................................................601
17.4.2.2 Receive Operation .................................................................................................602
17.4.2.3 Transmit Operation ................................................................................................603
17.5 Fast IrDA Specific Features ......................................................................................................604
17.5.1 Introduction ......................................................................................................................604
17.5.1.1 4PPM Modulation...................................................................................................604
17.5.1.2 4.0 Mbps FIR Frame Format..................................................................................606
17.5.2 Functional Description .....................................................................................................607
17.5.2.1 Baud Rate Generation ...........................................................................................608
EP9315 User’s Manual - DS638UM1 17 Copyright 2004 Cirrus Logic
17.5.2.2 Receive Operation................................................................................................. 608
17.5.2.3 Transmit Operation................................................................................................ 610
17.5.3 IrDA Connectivity ............................................................................................................ 611
17.5.4 IrDA Integration Information............................................................................................612
17.5.4.1 Enabling Infrared Modes ....................................................................................... 612
17.5.4.2 Clocking Requirements ......................................................................................... 612
17.5.4.3 Bus Bandwidth Requirements ............................................................................... 613
17.6 Registers .................................................................................................................................. 614
Chapter 18 Timers..................................................................................... 629
18.1 Introduction............................................................................................................................... 629
18.1.1 Features .......................................................................................................................... 629
18.1.2 16 and 32-bit Timer Operation ........................................................................................ 629
18.1.2.1 Free Running Mode ............................................................................................... 630
18.1.2.2 Pre-load Mode ....................................................................................................... 630
18.1.3 40-bit Timer Operation .................................................................................................... 630
18.2 Registers .................................................................................................................................. 631
Chapter 19 Watchdog Timer .................................................................... 637
19.1 Introduction............................................................................................................................... 637
19.1.1 Watchdog Activation ....................................................................................................... 638
19.1.2 Clocking Requirements ...................................................................................................638
19.1.3 Reset Requirements ....................................................................................................... 638
19.1.4 Watchdog Status............................................................................................................. 638
19.2 Registers .................................................................................................................................. 640
Chapter 20 Real Time Clock With Software Trim................................... 643
20.1 Introduction............................................................................................................................... 643
20.1.1 Software Trim.................................................................................................................. 643
20.1.1.1 Software Compensation ........................................................................................ 644
20.1.1.2 Oscillator Frequency Calibration............................................................................ 644
20.1.1.3 RTCSWComp Value Determination ...................................................................... 644
20.1.1.4 Example - Measured Value Split Into Integer and Fractional Component............. 645
20.1.1.5 Maximum Error Calculation vs. Real Time Clock Accuracy................................... 645
20.1.1.6 Real-Time Interrupt................................................................................................ 646
20.1.2 Reset Control.................................................................................................................. 646
20.2 Registers .................................................................................................................................. 647
Chapter 21 I2S Controller ......................................................................... 651
21.1 Introduction............................................................................................................................... 651
2
21.2 I
21.3 I
21.4 I
21.5 I
21.6 I
S Transmitter Channel Overview ........................................................................................... 653
2
S Receiver Channel Overview ............................................................................................... 657
21.3.1 Receiver FIFO’s .............................................................................................................. 657
2
S Configuration and Status Registers.................................................................................... 659
2
S Master Clock Generation.................................................................................................... 659
2
S Bit Clock Rate Generation .................................................................................................. 661
21.6.1 Example of the Bit Clock Generation. ............................................................................. 662
21.6.2 Example of Right Justified LRCK format......................................................................... 662
Copyright 2004 Cirrus Logic
21.7 Interrupts...................................................................................................................................663
21.8 Registers...................................................................................................................................665
21.8.1 I
21.8.2 I
21.8.3 I
21.8.4 I
2
S TX Registers..............................................................................................................665
2
S RX Registers .............................................................................................................672
2
S Configuration and Status Registers...........................................................................678
2
S Global Status Registers.............................................................................................682
Chapter 22 AC’97 Controller.................................................................... 685
22.1 Introduction ...............................................................................................................................685
22.2 Interrupts...................................................................................................................................687
22.2.1 Channel Interrupts ...........................................................................................................687
22.2.1.1 RIS .........................................................................................................................687
22.2.1.2 TIS..........................................................................................................................688
22.2.1.3 RTIS.......................................................................................................................688
22.2.1.4 TCIS.......................................................................................................................688
22.2.2 Global Interrupts..............................................................................................................688
22.2.2.1 CODECREADY......................................................................................................688
22.2.2.2 WINT......................................................................................................................688
22.2.2.3 GPIOINT ................................................................................................................689
22.2.2.4 GPIOTXCOMPLETE..............................................................................................689
22.2.2.5 SLOT2INT..............................................................................................................689
22.2.2.6 SLOT1TXCOMPLETE ...........................................................................................689
22.2.2.7 SLOT2TXCOMPLETE ...........................................................................................689
22.3 System Loopback Testing .........................................................................................................689
22.4 Registers...................................................................................................................................690
Chapter 23 Synchronous Serial Port ...................................................... 709
23.1 Introduction ...............................................................................................................................709
23.2 Features....................................................................................................................................709
23.3 SSP Functionality......................................................................................................................710
23.4 SSP Pin Multiplex......................................................................................................................710
23.5 Configuring the SSP..................................................................................................................710
23.5.1 Enabling SSP Operation..................................................................................................711
23.5.2 Master/Slave Mode..........................................................................................................711
23.5.3 Serial Bit Rate Generation...............................................................................................711
23.5.4 Frame Format.................................................................................................................711
23.5.5 Texas Instruments® Synchronous Serial Frame Format ................................................712
23.5.6 Motorola® SPI Frame Format .........................................................................................713
23.5.6.1 SPO Clock Polarity.................................................................................................713
23.5.6.2 SPH Clock Phase...................................................................................................713
23.5.7 Motorola SPI Format with SPO=0, SPH=0......................................................................713
23.5.8 Motorola SPI Format with SPO=0, SPH=1.....................................................................715
23.5.9 Motorola SPI Format with SPO=1, SPH=0......................................................................716
23.5.10 Motorola SPI Format with SPO=1, SPH=1....................................................................718
23.5.11 National Semiconductor® Microwire® Frame Format ...................................................719
23.5.11.1 Setup and Hold Time Requirements on SFRMIN with
Respect to SCLKIN in Microwire Mode.............................................................................721
23.6 Registers...................................................................................................................................722
EP9315 User’s Manual - DS638UM1 19 Copyright 2004 Cirrus Logic
Chapter 24 Pulse Width Modulator ......................................................... 729
24.1 Introduction............................................................................................................................... 729
24.2 Theory of Operation.................................................................................................................. 729
24.2.1 PWM Programming Examples........................................................................................ 730
24.2.1.1 Example................................................................................................................. 730
24.2.1.2 Static Programming (PWM is Not Running) Example ........................................... 730
24.2.1.3 Dynamic Programming (PWM is Running) Example............................................. 731
24.2.2 Programming Rules ........................................................................................................ 731
24.3 Registers .................................................................................................................................. 732
Chapter 25 Analog Touch Screen Interface ........................................... 737
25.1 Introduction............................................................................................................................... 737
25.2 Touch Screen Controller Operation.......................................................................................... 737
25.2.1 Touch Screen Scanning: Four-wire and Eight-wire Operation ........................................ 740
25.2.2 Five-wire and Seven-wire Operation............................................................................... 747
25.2.3 Direct Operation.............................................................................................................. 750
25.2.4 Measuring Analog Input with the Touch Screen Controls Disabled ................................ 752
25.2.5 Measuring Touch Screen Resistance ............................................................................. 754
25.2.6 Polled and Interrupt-Driven Modes ................................................................................. 756
25.2.7 Touch Screen Package Dependency.............................................................................. 756
25.3 Registers .................................................................................................................................. 757
Chapter 26 Keypad Interface ................................................................... 765
26.1 Introduction............................................................................................................................... 765
26.2 Theory of Operation.................................................................................................................. 766
26.2.1 Apparent Key Detection ..................................................................................................767
26.2.2 Scan and Debounce........................................................................................................ 769
26.2.3 Interrupt Generation ........................................................................................................ 770
26.2.4 Low Power Mode ............................................................................................................ 770
26.2.5 Three-key Reset.............................................................................................................. 771
26.3 Registers .................................................................................................................................. 772
Chapter 27 IDE Interface .......................................................................... 777
27.1 Introduction............................................................................................................................... 777
27.2 Theory of Operation.................................................................................................................. 777
27.2.1 Diagrams and State Machines........................................................................................ 778
27.2.2 PIO Operations ............................................................................................................... 779
27.2.3 MDMA Operations........................................................................................................... 781
27.2.4 UDMA Operations ........................................................................................................... 781
27.2.5 Performance Considerations........................................................................................... 782
27.2.6 UDMA Example............................................................................................................... 782
27.2.7 DMA Request Latency .................................................................................................... 784
27.2.7.1 DMA Request Deassertion .................................................................................... 784
27.2.7.2 DMA Request Latency Overview........................................................................... 784
27.2.7.3 IDE DMA Programming Considerations................................................................ 785
27.2.8 IDE Package Dependency .............................................................................................. 786
27.2.8.1 System Configuration Constraints......................................................................... 786
27.2.8.2 Bus Bandwidth Requirements ............................................................................... 786
Copyright 2004 Cirrus Logic
27.3 Registers...................................................................................................................................788
Chapter 28 GPIO Interface ....................................................................... 799
28.1 Introduction ...............................................................................................................................799
28.1.1 Memory Map....................................................................................................................800
28.1.2 Functional Description .....................................................................................................801
28.1.3 Reset ...............................................................................................................................803
28.1.4 GPIO Pin Map .................................................................................................................803
28.2 Registers...................................................................................................................................806
Chapter 29 Security .................................................................................. 815
29.1 Introduction ...............................................................................................................................815
29.2 Features....................................................................................................................................815
29.3 Contact Information...................................................................................................................815
29.4 Registers...................................................................................................................................816
Chapter 30 Glossary................................................................................. 817
EP9315 User’s Manual - DS638UM1 21 Copyright 2004 Cirrus Logic

List of Figures

Figure 1-1. EP9315 Block Diagram .................................................................................. 29
Figure 2-1. ARM920T Block Diagram ................................................................................. 36
Figure 2-2. Typical AMBA AHB System ............................................................................ 41
Figure 2-3. EP9315 Main Data Paths .................................................................................. 42
Figure 4-1. Flow Chart of Boot ROM Software .............................................................. 124
Figure 4-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices ............................. 127
Figure 5-1. Phase Locked Loop (PLL) Structure ............................................................ 133
Figure 5-2. EP9315 Clock Generation System.................................................................. 134
Figure 5-3. Bus Clock Generation ................................................................................... 135
Figure 5-4. EP9315 Power States and Transitions ......................................................... 139
Figure 6-1. Vectored Interrupt Controller Block Diagram ................................................ 166
Figure 7-1. Raster Engine Block Diagram ...................................................................... 190
Figure 7-2. Video Buffer Diagram ................................................................................... 191
Figure 7-3. Graphics Matrix for 50% Duty Cycle ............................................................. 204
Figure 7-4. Sample Matrix Causing Flickering ................................................................ 205
Figure 7-5. Sample Matrix That Avoids Flickering .......................................................... 206
Figure 7-6. Programming for One-third Luminous Intensity ............................................ 207
Figure 7-7. Creating Bit Patterns that Move to the Right ................................................ 208
Figure 7-8. Three and Four Count Axis .......................................................................... 209
Figure 7-9. Progressive/Dual Scan Video Signals .......................................................... 215
Figure 7-10. Interlaced Video Signals ............................................................................... 216
Figure 9-1. Block Diagram ................................................................................................ 297
Figure 9-2. Ethernet Frame / Packet Format (Type II only) ............................................... 300
Figure 9-3. Packet Transmission Process ......................................................................... 301
Figure 9-4. Carrier Deference State Diagram .................................................................... 302
Figure 9-5. Data Bit Transmission Order .......................................................................... 304
Figure 9-6. CRC Logic .................................................................................................... 305
Figure 9-7. Receive Descriptor Format and Data Fragments ......................................... 311
Figure 9-8. Receive Status Queue .................................................................................. 314
Figure 9-9. Receive Flow Diagram ................................................................................. 318
Figure 9-10. Receive Descriptor Data/Status Flow ........................................................... 320
Figure 9-11. Receive Descriptor Example ........................................................................ 321
Figure 9-12. Receive Frame Pre-processing .................................................................. 322
Figure 9-13. Transmit Descriptor Format and Data Fragments ........................................ 324
Figure 9-14. Multiple Fragments Per Transmit Frame ...................................................... 324
Figure 9-15. Transmit Status Queue ............................................................................... 327
Figure 9-16. Transmit Flow Diagram .............................................................................. 330
Figure 9-17. Transmit Descriptor Data/Status Flow ........................................................ 332
Figure 10-1. DMA M2P/P2M Finite State Machine............................................................ 398
Figure 10-2. M2M DMA Control Finite State Machine ....................................................... 401
Figure 10-3. M2M DMA Buffer Finite State Machine ........................................................ 403
Figure 10-4. Edge-triggered DREQ Mode ......................................................................... 409
Figure 11-1. USB Focus Areas .......................................................................................... 442
EP9315 User’s Manual - DS638UM1 22 Copyright 2004 Cirrus Logic
Figure 11-2. Communication Channels ............................................................................ 443
Figure 11-3. Typical List Structure .................................................................................... 444
Figure 11-4. Interrupt Endpoint Descriptor Structure ........................................................ 445
Figure 11-5. Sample Interrupt Endpoint Schedule ............................................................ 446
Figure 11-6. Frame Bandwidth Allocation ......................................................................... 447
Figure 11-7. USB Host Controller Block Diagram.............................................................. 449
Figure 12-1. 32-bit read, 32-bit Memory, 0 wait cycles, RBLE = 1,
WAITn Inactive ................................................................................................................ 480
Figure 12-2. 32-bit write, 32-bit Memory, 0 wait cycles, RBLE = 1,
WAITn Inactive ............................................................................................................... 481
Figure 12-3. 16-bit read, 16-bit Memory, RBLE = 1, WAITn Active ................................... 481
Figure 12-4. 16-bit write, 16-bit Memory, RBLE = 1, WAITn Active................................... 482
Figure 12-5. PCMCIA Single Card Interface ..................................................................... 488
Figure 14-1. UART Block Diagram ................................................................................... 517
Figure 14-2. UART Character Frame ................................................................................ 521
Figure 15-1. IrDA SIR Encoder/decoder Block Diagram ................................................... 554
Figure 15-2. IrDA Data Modulation (3/16) ......................................................................... 556
Figure 17-1. RZ1/NRZ Bit Encoding Example .................................................................. 599
Figure 17-2. 4PPM Modulation Encoding ......................................................................... 605
Figure 17-3. 4PPM Modulation Example .......................................................................... 605
Figure 17-4. IrDA (4.0 Mbps) Transmission Format .......................................................... 606
2
Figure 21-1. Architectural Overview of the I
S Controller ............................................... 652
Figure 21-2. Transmitter FIFO’s ...................................................................................... 654
Figure 21-3. Bit Clock Generation Example ................................................................. 662
Figure 21-4. Frame Format for Right Justified Data ................................................... 663
Figure 23-1. Texas Instruments Synchronous Serial Frame Format (Single Transfer) ..... 712
Figure 23-2. TI Synchronous Serial Frame Format (Continuous Transfer) ....................... 713
Figure 23-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0....... 714
Figure 23-4. Motorola SPI Frame Format (Continuous Transfer)
with SPO=0 and SPH=0.................................................................................................. 714
Figure 23-5. Motorola SPI Frame Format with SPO=0 and SPH=1 .................................. 715
Figure 23-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0....... 716
Figure 23-7. Motorola SPI Frame Format (Continuous Transfer)
with SPO=1 and SPH=0.................................................................................................. 717
Figure 23-8. Motorola SPI Frame Format with SPO=1 and SPH=1 .................................. 718
Figure 23-9. Microwire Frame Format (Single Transfer).................................................... 719
Figure 23-10. Microwire Frame Format (Continuous Transfers)........................................ 720
Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements.... 721
Figure 24-1. PWM_INV Example....................................................................................... 735
Figure 25-1. Different Types of Touch Screens ................................................................ 738
Figure 25-2. 8-Wire Resistive Interface Switching Diagram ............................................. 742
Figure 25-3. 4-Wire Analog Resistive Interface Switching Diagram .................................. 743
Figure 25-4. Analog Resistive Touch Screen Scan Flow Chart ........................................ 746
Figure 25-5. 5-Wire Analog Resistive Interface Switching Diagram ................................. 748
EP9315 User’s Manual - DS638UM1 23 Copyright 2004 Cirrus Logic
Figure 25-6. 5-Wire Feedback (7-Wire) Analog Resistive Interface Switching Diagram ... 749
Figure 25-7. Power Down Detect Press Switching Diagram ............................................. 751
Figure 25-8. Other Switching Diagrams ............................................................................ 753
Figure 25-9. Measure Resistance Switching Diagram ...................................................... 755
Figure 26-1. Key Array Block Diagram .......................................................................... 765
Figure 26-2. 8 x 8 Key Array Diagram ............................................................................. 767
Figure 26-3. Apparent Key 00H .................................................................................... 769
Figure 27-1. IDE Interface Signal Connections ................................................................. 778
Figure 28-1. System Level GPIO Connectivity ................................................................ 800
Figure 28-2. Signal Connections Within the Standard GPIO Port Control Logic
(Ports C, D, E, G, H) ..................................................................................................... 802
Figure 28-3. Signal Connections Within the Enhanced GPIO Port Control Logic
(Ports A, B, F) .............................................................................................................. 803
Copyright 2004 Cirrus Logic

List of Tables

Table 2-1: AHB Arbiter Priority Scheme ......................................................................... 44
Table 2-2: AHB Peripheral Address Range ...................................................................... 46
Table 2-3: APB Peripheral Address Range ..................................................................... 47
Table 2-4: Register Organization Summary ........................................................................ 49
Table 2-5: CP15 ARM920T Register Description ................................................................ 50
Table 2-6: Global Memory Map for the Two Boot Modes .................................................... 51
Table 2-7: Internal Register Map ....................................................................................... 53
Table 3-1: Saturation for Non-accumulator Instructions ...................................................... 73
Table 3-2: Accumulator Bit Formats for Saturation.............................................................. 73
Table 3-3: Comparison Relationships and Their Results ................................................... 75
Table 3-4: ARM Condition Codes and Crunch Compare Results ....................................... 75
Table 3-5: Condition Code Definitions ................................................................................ 83
Table 3-6: LDC/STC Opcode Map ...................................................................................... 84
Table 3-7: CDP Opcode Map .............................................................................................. 85
Table 3-8: MCR Opcode Map .......................................................................................... 85
Table 3-9: MRC Opcode Map ............................................................................................. 85
Table 3-10: MaverickCrunch Instruction Set ...................................................................... 86
Table 3-11: Mnemonic Codes.............................................................................................. 90
Table 3-12: Mnemonic Codes ........................................................................................... 91
Table 4-1: Boot Configuration Options (Normal Boot) ...................................................... 125
Table 5-1: Boot Configuration Options ............................................................................. 131
Table 5-2: Clock Speeds and Sources ........................................................................... 137
Table 5-3: Peripherals with PCLK gating ........................................................................ 138
Table 5-4: Syscon Register List ....................................................................................... 142
Table 5-5: Audio Interfaces Pin Assignment ..................................................................... 155
Table 6-1: Interrupt Configuration...................................................................................... 167
Table 6-2: VICx Register Summary ................................................................................... 173
Table 7-1: Raster Engine Video Mode Output Examples ............................................... 184
Table 7-2: Byte Oriented Frame Buffer Organization ..................................................... 187
Table 7-3: Output Pixel Transfer Modes ........................................................................... 196
Table 7-4: Grayscale Lookup Table (GrySclLUT) ........................................................... 200
Table 7-5: Grayscale Timing Diagram ............................................................................... 202
Table 7-6: Programming Format ..................................................................................... 203
Table 7-7: Programming 50% Duty Cycle Into Lookup Table ......................................... 207
Table 7-8: Programming 33% Duty Cycle into the Lookup Table ................................... 209
Table 7-9: Programming 33% Duty Cycle into the Lookup Table ................................... 210
Table 7-10: Cursor Memory Organization.......................................................................... 210
Table 7-11: Bits P[2:0] in the PixelMode Register ............................................................. 218
Table 7-12: Register List ................................................................................................. 223
Table 7-13: Color Mode Definition Table ........................................................................ 243
Table 7-14: Blink Mode Definition Table ......................................................................... 243
Table 7-15: Output Shift Mode Table .............................................................................. 243
Table 7-16: Bits per Pixel Scanned Out ............................................................................ 244
EP9315 User’s Manual - DS638UM1 25 Copyright 2004 Cirrus Logic
Table 7-17: Grayscale Look-Up-Table (LUT) .................................................................... 257
Table 8-1: Screen Pixels ................................................................................................... 268
Table 8-2: 1 bpp Memory Organization ............................................................................. 269
Table 8-3: 4 bpp Memory Organization ........................................................................... 269
Table 8-4: 8 bpp Memory Organization............................................................................. 270
Table 8-5: 16 bpp Memory Organization ........................................................................... 271
Table 8-6: 24 bpp Packed Memory Organization (4 pixel/ 3 words) ................................. 271
Table 8-7: 24 bpp Unpacked Memory Organization (1 pixel/ 1 word) ............................... 272
Table 8-8: Transfer Example 1 .......................................................................................... 273
Table 8-9: Transfer Example 2 ......................................................................................... 273
Table 8-10: Transfer Example 3 ....................................................................................... 273
Table 8-11: Transfer Example 4 ....................................................................................... 273
Table 8-12: Transfer Example 5 ...................................................................................... 274
Table 8-13: 4 BPP Memory Layout .................................................................................. 274
Table 8-14: 8 BPP Memory Layout ................................................................................. 275
Table 8-15: 16 BPP Memory Layout ................................................................................ 275
Table 8-16: 24 BPP Memory Layout ................................................................................ 276
Table 9-1: FIFO RAM Address Map .................................................................................. 299
Table 9-2: RXCtl.MA and RXCtl.IAHA[0] Relationships .................................................. 306
Table 9-3: Ethernet Register List .................................................................................... 337
Table 9-4: Individual Accept, RxFlow Control Enable and Pause Accept Bits ................ 339
Table 9-5: Address Filter Pointer .................................................................................... 349
Table 10-1: Data Transfer Size.......................................................................................... 410
Table 10-2: M2P DMA Bus Arbitration............................................................................... 412
Table 10-3: DMA Memory Map .......................................................................................... 413
Table 10-4: Internal M2P/P2M Channel Register Map ...................................................... 414
Table 10-5: PPALLOC Register Bits Decode for a Transmit Channel .......................... 417
Table 10-6: PPALLOC Register Bits Decode for a Receive Channel ............................... 417
Table 10-7: PPALLOC Register Reset Values .................................................................. 417
Table 10-8: M2M Channel Register Map ....................................................................... 423
Table 10-9: BWC Decode Values ...................................................................................... 426
Table 10-10: DMA Global Interrupt (DMAGlInt) Register .................................................. 438
Table 11-1: OpenHCI Register Addresses ........................................................................ 451
Table 12-1: nXBLS[3:0] Multiplexing.................................................................................. 482
Table 12-2: WRITING to an External Memory System ...................................................... 483
Table 12-3: PCMCIA Pin Usage ....................................................................................... 484
Table 12-4: PCMCIA Card Enable Usage.......................................................................... 485
Table 12-5: PCMCIA Legacy Usage .................................................................................. 485
Table 12-6: EP9315 Supported 8-bit PCMCIA Accesses .................................................. 485
Table 12-7: EP9315 Supported 16-bit PCMCIA Accesses ................................................ 485
Table 12-8: Accesses to 8-bit PCMCIA Attribute / Common / IO Memoryry...................... 486
Table 12-9: Accesses to 16-bit PCMCIA Attribute / Common / IO Memoryry.................... 486
Table 12-10: SMC Register Map........................................................................................ 489
Copyright 2004 Cirrus Logic
Table 13-1: Boot Device Selection..................................................................................... 496
Table 13-2: Synchronous Memory Address Decoding ..................................................... 498
Table 13-3: General SDRAM Initialization Sequence ........................................................ 499
Table 13-4: Mode Register Command Decoding............................................................... 500
Table 13-5: Sync Memory CAS Settings ........................................................................... 500
Table 13-6: Sync Memory RAS, (Write) Burst Type Settings ............................................ 501
Table 13-7: Burst Length Settings ..................................................................................... 501
Table 13-8: Chip Select Decoding ..................................................................................... 503
Table 13-9: Memory System Examples ............................................................................. 504
Table 13-10: Memory Address Decoding for 256 Mbit, 16-Bit Wide, and
13-Row x 9-Column x 2-Bank Device ............................................................................. 504
Table 13-11: 32-Bit Wide Data Systems............................................................................ 505
Table 13-12: 16-Bit Wide Data Systems............................................................................ 506
Table 13-13: Synchronous Memory Controller Registers .................................................. 507
Table 13-14: Synchronous Memory Command Encoding ................................................. 509
Table 14-1: Receive FIFO Bit Functions............................................................................ 520
Table 14-2: Legal HDLC Mode Configurations ............................................................... 525
Table 14-3: HDLC Receive Address Matching Modes ...................................................... 528
Table 14-4: UART1 Pin Functionality ................................................................................ 530
Table 14-5: DeviceCfg Register Bit Functions .................................................................. 530
Table 15-1: UART2 / IrDA Modes ..................................................................................... 557
Table 15-2: IonU2 Pin Function ........................................................................................ 557
Table 16-1: UART3 Pin Functionality ................................................................................ 571
Table 16-2: DeviceCfg Register Bit Functions .................................................................. 571
Table 17-1: Bit Values to Select Ir Module ........................................................................ 593
Table 17-2: Address Offsets for End-of-frame Data ......................................................... 595
Table 17-3: MIR Frame Format ......................................................................................... 600
Table 17-4: DeviceCfg.IonU2 Pin Function ................................................................... 611
Table 17-5: UART2 / IrDA Modes ..................................................................................... 612
Table 17-6: IrDA Service Memory Accesses / Second ................................................... 613
Table 18-1: Timers Register Map ...................................................................................... 631
Table 19-1: Register Memory Map ................................................................................ 640
Table 20-1: Register Memory Map ................................................................................. 647
2
Table 21-1: I
S Controller Input and Output Signals ......................................................... 652
Table 21-2: Audio Interfaces Pin Assignment ................................................................... 653
Table 21-3: I2SClkDiv SYSCON Register Effect on I2S Clock Generation ................... 661
Table 21-4: Bit Clock Rate Generation ........................................................................... 661
Table 21-5: FIFO Flags ..................................................................................................... 664
2
Table 21-6: I Table 21-7: I Table 21-8: I
S TX Registers .......................................................................................... 665
2
S RX Registers .......................................................................................... 672
2
S Configuration and Status Registers ......................................................... 678
Table 22-1: Register Memory Map ................................................................................. 690
Table 22-2: Interaction Between RSIZE and CM ......................................................... 693
Table 22-3: Interaction Between RSIZE and CM Bits ................................................... 695
EP9315 User’s Manual - DS638UM1 27 Copyright 2004 Cirrus Logic
Table 23-1: SSP Register Memory Map Description ......................................................... 722
Table 24-1: Static Programming Steps .............................................................................. 730
Table 24-2: Dynamic Programming Steps ......................................................................... 731
Table 24-3: PWM Registers Map .................................................................................. 732
Table 25-1: Switch Definitions and Logical Safeguards to Prevent Physical Damage ..... 740
Table 25-2: Touch Screen Switch Register Configurations ......................................... 744
Table 25-3: External Signal Functions ............................................................................ 756
Table 25-4: Register Memory Map .................................................................................. 757
Table 26-1: Register Memory Map .................................................................................. 772
Table 27-1: IDE Host to IDE Interface Definition ............................................................ 779
Table 27-2: IDE Cycle Times and Data Transfer Rates .................................................... 784
Table 27-3: Wait State Value for the DMA M2M Register Control.PWSC ....................... 785
Table 27-4: HCLK Cycles to Deassert DMA Request ....................................................... 785
Table 27-5: Maximum Theoretical Bandwidths for Various Operating Modes .................. 786
Table 27-6: IDE Interface Register Map............................................................................. 788
Table 28-1: GPIO Port to Pin Map .................................................................................... 804
Table 28-2: GPIO Register Address Map .......................................................................... 806
Table 29-1: Security Register List ................................................................................. 816
Copyright 2004 Cirrus Logic
NN

1.1 Introduction

The EP9315 is a highly integrated system-on-chip processor that paves the way for a multitude of next-generation consumer and industrial electronic products. Designers of digital media servers and jukeboxes, telematic control systems, thin clients, set-top boxes, point-of-sale terminals, industrial controls, biometric security systems, and GPS devices will benefit from the EP9315’s integrated architecture and advanced features. In fact, with amazingly agile performance provided by a 200 MHz ARM920T processor, and featuring an incredibly wide breadth of peripheral interfaces, the EP9315 is well suited to an even broader range of high volume applications. Furthermore, by enabling or disabling the EP9315’s peripheral interfaces, designers can reduce development costs and accelerate time-to-market by creating a single platform that can be easily modified to deliver a variety of differentiated end products.
Figure 1-1. EP9315 Block Diagram

Chapter 1

1Introduction

1
18-bit Raster LCD
SDRAM
SRAM/FLASH/ROM
PCMCIA
12 Channel DMA
Engine
1/10/100 Ethernet
MAC
JTAG
USB Host, 3 Ports
IDE
Boot ROM
UART1 w/ HDLC
UART3 w/ HDLC
MaverickCrunch
Coprocessor
ARM920T
I-Cache
AMBA High-Speed Bus (AHB)
Vectored Interrupt
Controllers (2)
D-Cache
16KB
AHB/APB
16KB
MMU
Bridge
UART2 w/ IrDA
System Ctrl - PLLs (2)
Touch Screen ADC
TM
8x8 Key Scan
PWM
2
S (IIS)
I
Enhanced GPIO
EEPROM, LED (2)
SPI
AMBA Peripheral Bus (APB)
AC’97
RTC with Trim
Watchdog Timer
Timers
EP9315 User’s Manual - DS638UM1 29 Copyright 2004 Cirrus Logic
Introduction

1 1.2 EP9315 Features

The EP9315 system-on-chip processor has the following features:
• 200 MHz ARM920T Processor
• 16 KByte data cache and 16 KByte instruction cache
• MMU enabling Linux
• 100 MHz system bus
• MaverickCrunch
• Floating point, integer and signal processing instructions
• Optimized for digital music compression algorithms
• Hardware interlocks allow in-line coding
• MaverickKey
• 32-bit unique ID
• 128-bit random ID
• Integrated Peripheral Interfaces
• EIDE, up to 2 devices
• 1/10/100 Mbps Ethernet MAC
• Three-port USB 2.0 Full Speed host (OHCI)
• Three UARTs (16550 Type)
• IrDA interface, slow and fast mode
™
™
IDs for Digital Rights Management or Design IP Security
®
and Windows® CE
Coprocessor
• LCD and Raster Interface with Graphics Accelerator
• PCMCIA Interface
• Touch screen interface
•SPI port
• AC ‘97 interface
• I2S interface, up to 6 channels
• 8x8 keypad scanner
• PCMCIA Interface: Supports two 8-bit or 16-bit PCMCIA devices
• External Memory Options
• 32-bit SDRAM interface, up to four banks
• 32/16/8-bit SRAM/Flash/ROM interface (I/F)
• Serial EEPROM interface
Copyright 2004 Cirrus Logic
Introduction
NN
• Internal Peripherals
• Real-Time clock with software trim
• 12 DMA channels for data transfer that maximizes system performance
•Boot ROM
• Dual PLLs control all clock domains
• Watchdog timer
• Two general purpose 16-bit timers
• General purpose 32-bit timer
• 40-bit debug timer
• General-Purpose I/Os
• 16 enhanced GPIOs including interrupt capability
• 31 additional optional GPIOs multiplexed on peripherals
• Available in 352-pin PBGA package

1.3 EP9315 Applications

1
The EP9315 can be used in a variety of applications, such as:
• Digital media servers
• Integrated home media gateways
• Digital audio jukeboxes
• Portable audio/video players
• Streaming audio/video players
• Telematic control systems
• Set-top boxes
• Point-of-sale terminals
• Thin clients
• Internet TVs
• Biometric security systems
• Industrial controls
• GPS & fleet management systems
• Educational toys
• Voting machines
• Medical equipment
EP9315 User’s Manual - DS638UM1 31 Copyright 2004 Cirrus Logic
Introduction

1 1.4 Overview of EP9315 Features

1.4.1 High-Performance ARM920T Processor Core

The EP9315 features an advanced ARM920T processor design with an MMU that supports Linux®, Windows® CE, and many other embedded operating systems. The ARM920T’s 32-bit microcontroller architecture, with a five-stage pipeline, delivers impressive performance at very low power. The included 16 KByte instruction cache and 16 KByte data cache provide zero-cycle latency to the current program and data, or can be locked to provide guaranteed no­latency access to critical instructions and data. For applications with instruction memory size restrictions, the ARM920T’s compressed Thumb instruction set provides a space-efficient design that maximizes external instruction memory usage.

1.4.2 MaverickCrunch™ Coprocessor for Ultra-Fast Math Processing

The MaverickCrunch coprocessor is an advanced, mixed-mode math coprocessor that greatly accelerates the single and double-precision integer and floating-point processing capabilities of the ARM920T processor core. The engine simplifies the end-user’s programming task by using predefined coprocessor instructions, by utilizing standard ARM compiler tools, and by requiring just one debugger session for the entire system. Furthermore, the integrated design provides a single instruction stream and the advantage of zero latency for cached instructions. To emulate this capability, competitors’ solutions add a DSP to the system, which requires separate compiler/linker/debugger tool sets. This additional DSP requires programmers to write two separate programs and debug them simultaneously, which can result in frustration and costly delays.
®
The single-cycle integer multiply-accumulate instruction in the MaverickCrunch coprocessor allows the EP9315 to offer unique speed and performance while encoding digital audio and video formats, processing data via Ethernet, and performing other math-intensive computing and data­processing functions in consumer and industrial electronics.

1.4.3 MaverickKey™ Unique ID Secures Digital Content and OEM Designs

MaverickKey unique hardware programmed IDs provide an excellent solution to the growing concern over secure Web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs for DRM (Digital Rights Management) mechanisms.
Copyright 2004 Cirrus Logic
Introduction
NN
MaverickKey uses a specific 32-bit ID and a 128-bit random ID that are programmed into the EP9315 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device that the EP9315 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by matching device IDs to server IDs.
MaverickKey IDs can also be used by OEMs and design houses to protect against design piracy by presetting ranges for unique IDs. For more information on securing your design using MaverickKey, please contact your Cirrus Logic sales representative.

1.4.4 Integrated Three-port USB 2.0 Full Speed Host with Transceivers

The EP9315 integrates three USB 2.0 Full Speed host ports. Fully compliant to the OHCI USB 2.0 Full Speed specification (12 Mbps), the host ports can be used to provide connections to a number of external devices including mass storage devices, external portable devices such as audio players or cameras, printers, or USB hubs. Naturally, the three-port USB host also supports the USB 2.0 Low Speed standard. This provides the opportunity to create a wide array of flexible system configurations.

1.4.5 Integrated Ethernet MAC Reduces BOM Costs

1
The EP9315 integrates a 1/10/100 Mbps Ethernet Media Access Controller (MAC) on the device. With a simple connection to an MII-based external PHY, an EP9315-based system has easy, high-performance, cost-effective Internet capability.

1.4.6 8x8 Keypad Interface Reduces BOM Costs

The keypad circuitry scans an 8x8 array of 64 normally open, single pole switches. Any one or two keys depressed will be de-bounced and decoded. An interrupt is generated whenever a stable set of depressed keys is detected. If the keypad is not utilized, the 16 column/row pins may be used as general­purpose I/Os.

1.4.7 Multiple Booting Mechanisms Increase Flexibility

The processor includes a 16 KByte boot ROM to set up standard configurations. Optionally, the processor may be booted from FLASH memory, over the SPI serial interface, or through the UART. This boot flexibility makes it easy to design user-controlled, field-upgradable systems. See Chapter 4 on page 121, for additional details.
EP9315 User’s Manual - DS638UM1 33 Copyright 2004 Cirrus Logic
Introduction
1

1.4.8 Abundant General Purpose I/Os Build Flexible Systems

The EP9315 includes both enhanced and standard general-purpose I/O pins (GPIOs). The 16 different enhanced GPIOs may individually be configured as inputs, outputs, or interrupt-enabled inputs. There are an additional 31 standard GPIOs that may individually be used as inputs, outputs, or open­drain pins. The standard GPIOs are multiplexed with peripheral function pins, so the number available depends on the utilization of peripherals. Together, the enhanced and standard GPIOs facilitate easy system design with external peripherals not integrated on the EP9315.

1.4.9 General-Purpose Memory Interface (SDRAM, SRAM, ROM and FLASH)

The EP9315 features a unified memory address model in which all memory devices are accessed over a common address/data bus. A separate internal bus is dedicated to the read-only Raster/Display refresh engine, while the rest of the memory accesses are performed via the high-speed processor bus. The SRAM memory controller supports 8, 16 and 32-bit devices and accommodates an internal boot ROM concurrently with a 32-bit SDRAM memory.
1.4.10 12-Bit Analog-to-Digital Converter (ADC) Provides an Integrated Touch-Screen Interface or General ADC Functionality
The EP9315 includes a 12-bit ADC, which can be utilized either as a touch­screen interface or for general ADC functionality. The touch-screen interface performs all sampling, averaging, ADC range checking, and control for a wide variety of analog-resistive touchscreens. To improve system performance, the controller only interrupts the processor when a meaningful change occurs. The touch-screen hardware may be disabled, and the switch matrix and ADC controlled directly for general ADC usage if desired.

1.4.11 Graphics Accelerator

The EP9315 includes a hardware graphics acceleration engine that improves graphic performance by handling block copy, block fill and hardware line draw operations. The graphics accelerator is used in the system to off load graphics operations from the processor.

1.4.12 PCMCIA Interface

The PCMCIA interface supports one 16-bit PCMCIA PC Card. These devices are credit card sized peripherals that add memory, mass storage and I/O capabilities to computer systems, and can be used to further broaden the options of a designer’s platform.
Copyright 2004 Cirrus Logic

Chapter 2

OO

2ARM920T Core and Advanced High-Speed Bus (AHB)

2.1 Introduction

This section discusses the ARM920T processor core and the Advanced High­Speed Bus (AHB).

2.2 Overview: ARM920T Processor Core

The ARM920T is a Harvard architecture processor core with separate 16 kbyte instruction and data caches with an 8-word line length used in the EP9315. The processor core utilizes a five-stage pipeline consisting of fetch, decode, execute, data memory access, and write stages.

2.2.1 Features

Key features include:
• ARM V4T (32-bit) and Thumb (16-bit compressed) instruction sets
• 32-bit Advanced Micro-Controller Bus Architecture (AMBA)
2
• 16 kbyte Instruction Cache with lockdown
• 16 kbyte Data Cache (programmable write-through or write-back) with lockdown
• Write Buffer
• MMU for Microsoft Windows CE and Linux operating systems
• Translation Look-aside Buffers (TLB) with 64 Data and 64 Instruction Entries
• Programmable Page Sizes of 64 kbyte, 4 kbyte, and 1 kbyte
• Independent lockdown of TLB Entries
• JTAG Interface for Debug Control
• Coprocessor Interface
EP9315 User’s Manual - DS638UM1 35 Copyright 2004 Cirrus Logic
2
ARM920T Core and Advanced High-Speed Bus (AHB)

2.2.2 Block Diagram

Figure 2-1. ARM920T Block Diagram
External Co-Proc
Interface
Instruction
cache
R13
Instruction
MMU

2.2.3 Operations

The ARM920T core follows a Harvard architecture and consists of an ARM9TDMI core, MMU, instruction and data cache. The core supports both the 32-bit ARM and 16-bit Thumb instruction sets.
The internal bus structure (AMBA) includes both an internal high speed and external low speed bus. The high speed bus AHB (Advanced High­performance Bus) contains a high speed internal bus clock to synchronize coprocessor, MMU, cache, DMA controller, and memory modules. AMBA includes a AHB/APB bridge to the lower speed APB (Advanced Peripheral Bus). The APB bus connects to lower speed peripheral devices such as UARTs and GPIOs.
JTAG
ARM9TDMI
Processor core
(Integral
EmbeddedICE)
R13
Data cache Data MMU
CP15
Write
Buffer
Write Back
PA TAG
RAM
AMBA
Bus
Int.
APB
The MMU provides memory address translation for all memory and peripherals designed to remap memory devices and peripheral address locations. Sections, large, small and tiny pages are programmable to map memory in 1 Mbyte, 64 kbyte, 4 kbyte, 1 kbyte size blocks. To increase system performance, a 64-entry translation look-aside buffer will cache 64 address locations before a TLB miss occurs.
Copyright 2004 Cirrus Logic
A 16 kbyte instruction and a 16 kbyte data cache are included to increase performance for cache-enabled memory regions. The 64-way associative cache also has lock-down capability. Cached instructions and data also have access to a 16-word data and 4-word instruction write buffer to allow cached instructions to be fetched and decoded while the write buffer sends the information to the external bus.
The ARM920T core supports a number of coprocessors, including the MaverickCrunch coprocessor by means of a specific pipeline architecture interface.
2.2.3.1 ARM9TDMI Core
ARM9TDMI core is responsible for executing both 32-bit ARM and 16-bit Thumb instructions. Each provides a unique advantage to a system design. Internally, the instructions enter a 5-stage pipeline. These stages are:
• Instruction Fetch
• Instruction Decode
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
2
• Execute
• Data Memory Access
• Register Write
All instructions are fully interlocked. This mechanism will delay the execution stage of a instruction if data in that instruction comes from a previous instruction that is not available yet. This simply insures that software will function identically across different implementations.
For memory access instructions, the base register used for the access will be restored by the processor in the event of an Abort exception. The base register will be restored to the value contained in the processor register before execution of the instruction.
The ARM9TDMI core memory interface includes a separate instruction and data interface to allow concurrent access of instructions and data to reduce the number of CPI (cycles per instruction). Both interfaces use pipeline addressing. The core can operate in big and little endian mode. Endianess affects both the address and the data interfaces.
The memory interface executes four types of memory transfers: sequential, non-sequential, internal, and coprocessor. It will also support uni- and bi­directional transfer modes.
The core provides a debug interface called JTAG (Joint Testing Action Group). This interface provides debug capability with five external control signals:
• TDO - Test Data Out
• TDI - Test Data In
EP9315 User’s Manual - DS638UM1 37 Copyright 2004 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
• TMS - Test Mode Select
• TCK - Test Clock
2
• nTRST - Test Reset
There are six scan chains (0 through 5) in the ARM9TDMI controlled by the JTAG Test Access Port (TAP) controller. Details on the individual scan chain function and bit order can be found in the ARM920T Technical Reference Manual.
2.2.3.2 Memory Management Unit
The MMU provides the translation and access permissions for the address and data ports for the ARM9TDMI core. The MMU is controlled by page tables stored in system memory and accessed using the CP15 register 1. The main features of the MMU are as follows:
• Address Translation
• Access Permissions and Domains
• MMU Cache and Write Buffer Access
2.2.3.2.1 Address Translation
The virtual address from the ARM920T core is modified by R13 internally to create a modified virtual address. The MMU then translates the modified virtual address from R13 by the CP15 register 3 into a physical address to access external memory or a device. The MMU looks for the physical address from the Translation Table Base (TTB) in system memory. It will also update the TLB cache.
The TLB is two 64-entry caches, one for data and one for instruction. If the physical address for the current virtual address is not found in the TLB (miss), the processor will go to external memory and look for the TTB in system memory. The internal translation table walks hardware steps through the page table setup in external memory for the appropriate physical address.
When the physical address is acquired, the TLB is updated. When the address is found in the TLB, system performance will increase since it will take additional cycles to access memory and update the TLB.
Translation of system memory is done by breaking up the memory into different size blocks called sections, large pages, small pages, and tiny pages. System memory and registers can be remapped by the MMU. The block sizes are as follows:
• Section - 1 Mbyte
• Large Page - 64 kbyte
• Small Page - 16 kbyte
Copyright 2004 Cirrus Logic
• Tiny Page - 1 kbyte
2.2.3.2.2 Access Permission and Domains
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
Access to any section or page of memory is dependent on its domain. The page table in external memory also contains access permissions for all sub­divisions of external memory. Access to specific instructions or data has three possible states, assuming access is permitted:
•
•
•
2.2.3.2.3 MMU Enable
Enabling the MMU allows for system memory control, but is also required if the data cache and the write buffer are to be used. These features are enabled for specific memory regions, as defined in the system page table. MMU enable is done via CP15 register 1. The procedure is as follows:
1. Program the Translation Table Base (TTB) and domain access control
2. Create level 1 and level 2 pages for the system and enable the cache and
3. Enable MMU - bit 0 of CP15 register 1.
Client
: Access permissions based on the section or page table descriptor
Manager
descriptor
No access
registers.
the write buffer.
: Ignore access permissions in the section or page table
: any attempted access generates a domain fault
2
2.2.3.3 Cache and Write Buffer
Cache configuration is 64-way set associative. There is a separate 16 kbyte instruction and data cache. The cache has the following characteristics:
• 8 words per line with 1 valid bit and 2 dirty bits per line for allowing half­line write-backs.
• Write-through and write-back capable, selectable per memory region defined by the MMU.
• Pseudo random or round robin replacement algorithms for cache misses. This is determined by the RR bit (bit 14 in CP15 register 1). An 8-word line is reloaded on a cache miss.
• Independent cache lock-down with granularity of 1/64th of total cache size or 256 bytes for both instructions and data. Lock-down of the cache will prevent an eight-word cache line fill of that region of cache.
• For compatibility with Windows CE and to reduce latency, physical addresses stored for data cache entries are stored in the PA TAG RAM to be used for cache line write-back operations without need of the MMU, which prevents a possible TLB miss that would degrade performance.
EP9315 User’s Manual - DS638UM1 39 Copyright 2004 Cirrus Logic
2
ARM920T Core and Advanced High-Speed Bus (AHB)
• Write Buffer is a 4-word instruction x 16-word data buffer. If enabled, writes are sent to buffer directly from cache or from the CPU in the event of a cache miss or cache not enabled.
2.2.3.3.1 Instruction Cache Enable
• At reset, the cache is disabled.
• A write to CP15 register 1, bit 12, will enable or disable the Instruction Cache. If the Instruction Cache (I-Cache) is enabled without the MMU enabled, all accesses are treated as cacheable.
• If disabled, current contents are ignored. If re-enabled before a reset, contents will be unchanged but may not be coherent with main memory. If so, contents must be flushed before re-enabling.
2.2.3.3.2 Data Cache Enable
• A write to CP15 register 1, bit 0, will enable or disable the Data Cache (D­Cache)/Write Buffer.
• D-Cache must only be enabled when the MMU is enabled. All data accesses are subject to MMU and permission checks.
• If disabled, current contents are ignored. If re-enabled before a reset, contents will be unchanged but may not be coherent with main memory. Depending on system software, a clean and invalidate action may be required before re-enabling.
2.2.3.3.3 Write Buffer Enable
• The Write bugger is enabled by the page table entries in the MMU. The Write buffer is not enabled unless MMU is enabled.

2.2.4 Coprocessor Interface

The MaverickCrunch coprocessor is explained in detail in Chapter 3. The relationship between the ARM coprocessor instructions and MaverickCrunch coprocessor is also explained in Chapter 3.
The ARM coprocessor instruction set includes the following:
• LDC - Load coprocessor from memory
• STC - Store coprocessor register from memory
• MRC - Move to ARM register from coprocessor register
• MCR - Move to coprocessor register from ARM register
• Access to sixteen (C0 through C15) 64-bit registers to access the coprocessor for data transfer and data manipulation to be used with the above instructions. See Chapter 3, Section 3.2 on page 75 for a code example.
Copyright 2004 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)

2.2.5 AMBA AHB Bus Interface Overview

The AMBA AHB is designed for use with high-performance, high clock frequency system modules. The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral functions. AHB is also specified to ensure ease of use in an efficient design flow using synthesis and automated test techniques. Figure 2-2 shows a typical AMBA AHB System.
AHB (Advanced High-Performance Bus) connects with devices that require greater bandwidth, such as DMA controllers, external system memory, and coprocessors. The AMBA AHB bus has the following characteristics:
• Burst Transactions
• Split Transactions
• Bus Master hand-over to devices, that is, DSP or DMA controller
• Single clock edge operations
OO
2
APB (Advanced Peripheral Bus) is a lower bandwidth lower power bus which provides the following:
• Low Power Operations
• Latched address and control
• Simple Interface
Figure 2-2. Typical AMBA AHB System
External Memory
Interfa c e
ARM9TDMI
Co-
Processo
USB
r
AHB APB
DMA
Controller
AHB/
APB
B
r
i d g e
UART SPI
GPIO
AC97
EP9315 User’s Manual - DS638UM1 41 Copyright 2004 Cirrus Logic
2
ARM920T Core and Advanced High-Speed Bus (AHB)

2.2.6 EP9315 AHB Implementation Details

Peripherals that have high bandwidth or latency requirements are connected to the EP9315 processor using the AHB bus. These include the external memory interface, Vectored Interrupt Controllers (VIC1, VIC2), DMA, LCD/Raster registers, USB host, IDE, Ethernet MAC and the bridge to the APB interface. The AHB/APB Bridge transparently converts the AHB access into the slower speed APB accesses. All of the control registers for the APB peripherals are programmed using the AHB/APB bridge interface. The main AHB data and address lines are configured using a multiplexed bus. This removes the need for three state buffers and bus holders and simplifies bus arbitration. Figure 2-3 shows the main data paths in the EP9315 AHB implementation.
Figure 2-3. EP9315 Main Data Paths
VIC2
VIC1
Ethernet
ARM920T
18 Bit Raster
LCD I/F
SDRAM
Controller
E B I
Static
Memory/
PCMCIA
IDE
USB Host
AHB
Maverick
Crunch
Boot ROM
DMA
UARTs
Timers
AHB/APB
bridge
RTC
Watchdog
Test
Support
APB
Touchscreen
8x8 Key Mtx
GPIOs
PWM
SPI
I2S
IrDA
PLL1 PLL2
Clock & State
Control
AC97
Copyright 2004 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
Before an AMBA-to-AHB transfer can commence, the bus master must be granted access to the bus. This process is started by the master asserting a request signal to the arbiter. Then the arbiter indicates when the master will be granted use of the bus. A granted bus master starts an AMBA-to-AHB transfer by driving the address and control signals. These signals provide information on the address, direction and width of the transfer, as well as indicating whether the transfer forms part of a burst.
Two different forms of burst transfers are allowed:
• Incrementing bursts, which do not wrap at address boundaries
• Wrapping bursts, which wrap at particular address boundaries.
A write data bus is used to move data from the master to a slave, while a read data bus is used to move data from a slave to the master. Every transfer consists of:
• An address and control cycle
• One or more cycles for the data.
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2
In normal operation a master is allowed to complete all the transfers in a particular burst before the arbiter grants another master access to the bus. However, in order to avoid excessive arbitration latencies, it is possible for the arbiter to break up a burst, and, in such cases, the master must re-arbitrate for the bus in order to complete the remaining transfers in the burst.

2.2.7 Memory and Bus Access Errors

There are several possible sources of access errors.
• Reads to reserved or undefined register memory addresses will return indeterminate data. Writes to reserved or undefined memory addresses are generally ignored, but this behavior is not guaranteed. Many register addresses are not fully decoded, so aliasing may occur. Addresses and memory ranges listed as Reserved should not be accessed; access behavior to these regions is not defined.
• Access to non-existent registers or memory may result in a bus error.
• Any access in the APB control register space will complete normally, as these devices have no means of signaling an error.
• Access to non-existent AHB/APB registers may result in a bus error, depending on the device and nature of the error. Device specific access rules are defined in the device descriptions.
• External memory access is controlled by the Static Memory Controller (SMC) and the Synchronous Dynamic RAM (SDRAM) controller. In general, access to non-existent external memory will complete normally, with reads returning random false data.
EP9315 User’s Manual - DS638UM1 43 Copyright 2004 Cirrus Logic
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ARM920T Core and Advanced High-Speed Bus (AHB)

2.2.8 Bus Arbitration

The arbitration mechanism is used to ensure that only one master has access to the bus it controls at any one time. The arbiter performs this function by observing a number of different requests to use the bus and deciding which is currently the highest priority master requesting the bus.
The arbitration scheme can be broken down into three main areas:
• The main AHB system bus arbiter
• The SDRAM slave interface arbiter
• The EBI bus arbiter
2.2.8.1 Main AHB Bus Arbiter
This arbiter controls the bus master arbitration for the AHB bus. The AHB bus has eight Master interfaces, these are:
• ARM920T
• DMA controller
• USB host (USB1, 2, 3)
• Ethernet MAC
• LCD/Raster and Raster Hardware Cursor.
These interfaces have an order of priority that is linked closely with the power saving modes. The power saving modes of Halt and Standby force the arbiter to grant the default bus master, in this case, the ARM920T.
In summary, the order of priority of the bus masters, from highest to lowest, is shown in Table 2-1.
Table 2-1: AHB Arbiter Priority Scheme
Priority
Number
1 Raster Cursor Raster Raster Raster
2 MAC Raster Cursor Raster Cursor DMA
3 USB MAC DMA MAC
4 DMA USB USB USB
5 ARM920T ARM920T MAC Raster Cursor
6 Raster DMA ARM920T ARM920T
PRIORITY 00
(Reset value)
PRIORITY 01 PRIORITY 10 PRIORITY 11
The priority of the Arbiter can be programmed in the BusMstrArb register in the Clock and State Controller. The Arbiter can also be programmed to degrant one of the following masters: DMA, USB Host or Ethernet MAC, if an interrupt (IRQ or FIQ) is pending or being serviced. This prevents one of these masters from blocking important interrupt service routines. These masters are
Copyright 2004 Cirrus Logic
prevented from accessing the bus, and their bus requests are masked, until the IRQ/FIQ is removed (by the Interrupt Service Routine), at which point their bus requests will be recognized. The default is to program the Arbiter so that it does
not
degrant any of these masters.
In normal operation, when the ARM920T is granted the bus and a request to enter Halt mode is received, the ARM920T is de-granted from the AHB bus. Any other master requesting the bus in Halt mode (according to the priority) will be granted the bus. In the case of the entry into Standby, the dummy master will be granted the bus, which simply performs IDLE transfers. In this way, all the masters except the ARM920T can be used during Halt mode, but are shutdown during an entry into Standby.
2.2.8.2 SDRAM Slave Arbiter
The SDRAM controller has a slave interface for the main AHB bus and the Raster controller DMA bus. In order to control the accesses to these memory systems, the SDRAM controller has an arbiter that prioritizes between the AHB and the Raster DMA bus. In this case the Raster controller bus is given priority. If an access from the AHB is requested at the same time as a Raster DMA, the Raster will be given access while the AHB request is queued.
ARM920T Core and Advanced High-Speed Bus (AHB)
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2
2.2.8.3 EBI Bus Arbiter
This arbiter is used to arbitrate between accesses from the SDRAM controller and the Static Memory controller. The priority is given to accesses from the SDRAM controller.

2.3 AHB Decoder

The AHB decoder contains the memory map for all the AHB masters/slaves and the APB bridge. When a particular address range is selected, the appropriate signal is generated. It is defined in Table 2-2.
(For additional information, see “Reference Documents”, on Page 4.)
EP9315 User’s Manual - DS638UM1 45 Copyright 2004 Cirrus Logic
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ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-2: AHB Peripheral Address Range
Address Range Register Width Peripheral Type Peripheral
0x800D_0000 - 0x800F_FFFF - - Reserved
0x800C_0000 - 0x800C_FFFF 32 AHB VIC2
0x800B_0000 - 0x800B_FFFF 32 AHB VIC1
0x800A_0000 - 0x800A_FFFF 32 AHB IDE
0x8009_0000 - 0x8009_FFFF 32 AHB Boot ROM physical address
0x8008_0000 - 0x8008_FFFF 32 AHB SRAM Controller/ PCMCIA
0x8007_0000 - 0x8007_FFFF - - Reserved
0x8006_0000 - 0x8006_FFFF 32 AHB SDRAM Controller
0x8005_0000 - 0x8005_FFFF - - Reserved
0x8004_0000 - 0x8004_FFFF - - Reserved
0x8003_0000 - 0x8003_FFFF 32 AHB Raster
0x8002_0000 - 0x8002_FFFF 32 AHB USB Host
0x8001_0000 - 0x8001_FFFF 32 AHB Ethernet MAC
0x8000_0000 - 0x8000_FFFF 32 AHB DMA
Note: Due to decoding optimization, the AHB peripheral registers are aliased
throughout each peripherals register bank. Do not program access to an unspecified register within the bank.

2.3.1 AHB Bus Slave

An AHB slave responds to transfers initiated by bus masters within the system. The slave uses signals from the decoder to determine when it should respond to a bus transfer. All other signals required for the transfer, such as the address and control information, are generated by the bus master.

2.3.2 AHB to APB Bridge

The AHB to APB bridge is an AHB slave, providing an interface between the high-speed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB. As the APB is not pipelined. Wait states are added during transfers to and from the APB when the AHB is required to wait for the APB.
The main sections of this module are:
• AHB slave bus interface
• APB transfer state machine, which is independent of the device memory map
• APB output signal generation.
2.3.2.1 Function and Operation of APB Bridge
The APB bridge responds to transaction requests from the currently granted AHB master. The AHB transactions are then converted into APB transactions.
Copyright 2004 Cirrus Logic
If an undefined location is accessed, operation of the system continues as normal, but no peripherals are selected. The APB bridge acts as the only master on the APB.
The APB memory map is shown in Table 2-3.
Table 2-3: APB Peripheral Address Range
ARM920T Core and Advanced High-Speed Bus (AHB)
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2
Address Range
0x8095_0000 - 0x9000_FFFF - - Reserved
0x8094_0000 - 0x8094_FFFF 16 APB Watchdog Timer
0x8093_0000 - 0x8093_FFFF 32 APB Syscon
0x8092_0000 - 0x8092_FFFF 32 APB Real time clock
0x8091_0000 - 0x8091_FFFF 16 APB Pulse Width Modulation
0x8090_0000 - 0x8090_FFFF 32 APB Touchscreen
0x808F_0000 - 0x808F_FFFF 16 APB Key Matrix
0x808E_0000 - 0x808E_FFFF 32 APB UART3
0x808D_0000 - 0x808D_FFFF 8 APB UART2
0x808C_0000 - 0x808C_FFFF 32 APB UART1
0x808B_0000 - 0x808B_FFFF 32 APB IrDA
0x808A_0000 - 0x808A_FFFF 16 APB SPI
0x8089_0000 - 0x8089_FFFF - - Reserved
0x8088_0000 - 0x8088_FFFF 32 APB AAC
0x8087_0000 - 0x8087_FFFF - - Reserved
0x8086_0000 - 0x8086_FFFF - - Reserved
0x8085_0000 - 0x8085_FFFF - - Reserved
0x8084_0000 - 0x8084_FFFF 16 APB GPIO
0x8083_0000 - 0x8083_FFFF 32 APB Security
0x8082_0000 - 0x8082_FFFF 32 APB I2S
0x8081_0000 - 0x8081_FFFF 32 APB Timers
0x8080_0000 - 0x8080_FFFF - - Reserved
0x8010_0000 - 0x807F_FFFF - - Reserved
Register
Width
Peripheral
Type
Peripheral
Note: Due to decoding optimization, the APB peripheral registers are aliased
throughout each peripherals register bank. Do not program access to an unspecified register within the bank.

2.3.3 APB Bus Slave

An APB slave responds to transfers initiated by bus masters within the system. The slave uses signals from the decoder to determine when it should respond to a bus transfer. All other signals required for the transfer, such as the address and control information, are generated by the APB bridge.

2.3.4 Register Definitions

ARM has thirty seven 32-bit internal registers, some are modal, some are banked. If operating in Thumb mode, the processor must switch to ARM mode
EP9315 User’s Manual - DS638UM1 47 Copyright 2004 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
before taking an exception. The return instruction will restore the processor to Thumb state. Most tasks are executed out of User mode.
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User: Unprivileged normal operating mode
FIQ: Fast interrupt (high priority) mode when FIQ is asserted
IRQ: Interrupt request (normal) mode when IRQ is asserted
Supervisor: Software interrupt instruction (SWI) or reset will cause entry
into this mode
Abort: Memory access violation will cause entry into this mode
Undef: Undefined instructions
System: Privileged mode. Uses same registers as user mode
Table 2-4 illustrates the use of all registers for the following ARM920T operating modes. Each will bank or store a specific number of registers. Banked register information is not shared between modes. FIQs bank the fewest number of registers which increases performance.
Copyright 2004 Cirrus Logic
Table 2-4: Register Organization Summary
User System Supervisor Abort Undefined IRQ FIQ
r0 r0 r0 r0 r0 r0 r0
r1 r1 r1 r1 r1 r1 r1
r2 r2 r2 r2 r2 r2 r2
r3 r3 r3 r3 r3 r3 r3
r4 r4 r4 r4 r4 r4 r4
r5 r5 r5 r5 r5 r5 r5
r6 r6 r6 r6 r6 r6 r6
r7 r7 r7 r7 r7 r7 r7
r8 r8 r8 r8 r8 r8
r9 r9 r9 r9 r9 r9
r10 r10 r10 r10 r10 r10
r11 r11 r11 r11 r11 r11
r12 r12 r12 r12 r12 r12
r13(sp) r13
r14(lr) r14
r15(pc) pc pc pc pc pc pc
ARM920T Core and Advanced High-Speed Bus (AHB)
Priveledged Modes
Exception Modes
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_svc r13_abt r13_und r13_irq r13_fiq
r14_svc r14_abt r14_und r14_irq r14_fiq
OO
2
Thumb state low registers
Thumb
state high
registers
cpsr cpsr cpsr cpsr cpsr cpsr cpsr
spsr_svc spsr_abt spsr_und spsr_irq spsr_fiq
Note: Colored areas represent banked registers.
User mode in Thumb state generally limits access to r0-r7. There are six instructions that allow access to the high registers. For these 6 exceptions, the processor must revert to ARM state. These exceptions are:
• r0-r12: General purpose read/write 32-bit registers
• r13 (sp): Stack Pointer
• r14 (lr): Link Register
• r15 (pc): Program Counter
• cpsr: Current Program Status Register (contains condition codes and operating modes)
EP9315 User’s Manual - DS638UM1 49 Copyright 2004 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
• spsr: Saved Program Status Register (saves CPSR when exception occurs)
2
The ARM920T core has 16 coprocessor registers for control over the core. Updates to the coprocessor registers are written using the CP15 instruction. Table 2-5 describes the CP15 ARM920T registers.
Table 2-5: CP15 ARM920T Register Description
Register Description
ID Code: (Read/Only) This register returns a 32-bit device code. ID Code data represents
the core type, revision, part number etc. Access to this register is done with the following instruction:
0
1
2
3
MRC p15 0, Rd, c0, c0, 0
Cache Code: This will also return cache type, size and length of both I-Cache and D-
Cache, size, and associativity. This is accessed with: MRC p15 0, Rd, c0, c0, 1
Control Register: (Read/Write) Use this register to enable MMU, instruction and data
cache, round robin replacement ‘RR’-bit, system protection, ROM protection, clocking mode. Read/Write Instructions: MRC p15, 0, Rd, c1, c0, 0 - Read control register - value stored in Rd MCR p15, 0, Rd, c1, c0, 0 - Write control register - value first loaded into Rd
Translation Base Table: (Read/Write) This register contains the start address of the first
level translation table. Upper18 bits represent the pointer to table base. Lower 14 bits should be 0 for a write, unpr edictable if read. MRC p15, 0, Rd, c2, c0, 0 - Read TTB MCR p15, 0, Rd, c2, c0, 0 - Write TTB
Domain Access Control: (Read/Write) This register specifies permissions for all 16
domains. MRC p15, 0, Rd, c3, c0, 0 MCR p15, 0, Rd, c3, c0, 0
4
5
6
7
8
9
Reserved: Do not access. Unpredictable behavior may result.
Fault Status: (Read/Write) This register indicates type of fault and domain of last data
abort. MRC p15, 0, Rd, c5, c0, 0 - read data FSR value MCR p15, 0, Rd, c5, c0, 0 - write data FSR value
Fault Address: (Read/Write) This register contains address of the last data access abort.
MRC p15, 0, Rd, c6, c0, 0 - read data FAR data MCR p15, 0, Rd, c6, c0, 0 - write data FAR data
Cache Operation: (Write/Only) This register will configure or perform a clean (flush) of the
cache and write buffer when written to. An example: MRC p15, 0, Rd, c7, c7, 0 - Invalidate I/D-cache MRC p15, 0, Rd, c7, c5, 0 - Invalidate I-Cache
TLB Operation: (Write/Only) This register can configure or clean (flush) when written to:
MRC p15, 0, Rd, c8, c7, 0 - Invalidate TLB
Cache Lockdown: (Read/Write) Prevents certain cache-line fills from being overwritten
(locked). MRC p15, 0, Rd, c9, c0, 1- Write lockdown base pointer for D-Cache MRC p15, 0, Rd, c9, c0, 1 - Write lockdown base pointer for I-Cache
Copyright 2004 Cirrus Logic
Table 2-5: CP15 ARM920T Register Description (Continued)
Register Description
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
11,12,14

2.3.5 Memory Map

The overall memory map for the device is shown in Table 2-6.
If internal Boot Mode is selected and the register BootModeClr has been written, the address range 0x0000_0000 -> 0x0000_FFFF is occupied by the internal Boot ROM until the internal Boot Code is completed and then the map reverts back to either Synchronous or Asynchronous memory in this address space.
NOTE: Some memory locations are listed as Reserved. These memory locations should not be used. Reading from these memory locations will yield invalid data. Writing to these memory locations may cause unpredictable results.
10
13
15
TLB Lockdown: (Read/Write) Prevents TLB entries from being erased during a table walk.
MRC p15, 0, Rd, c10, c0, 1- Write lockdown base pointer for data TLB entry MRC p15, 0, Rd, c10, c0, 1 - Write lockdown base pointer for instruction TLB entry
Reserved
FCSE PID Register: (Read/Write) Addresses by the ARM9TDMI core in a range from 0 to
32MB are translated by this register to A + FCSE*32MB and remapped. If turned off, straight address map to the MMU result.
Test Register Only: Reads or writes will cause unpredictable behavior.
2
Table 2-6: Global Memory Map for the Two Boot Modes
Address Range Sync Memory Boot Async Memory Boot
ASD0 Pin = 1 ASD0 Pin = 0
0xF000_0000 - 0xFFFF_FFFF Async memory (nCS0) Sync memory (nSDCE3)
0xE000_0000 - 0xEFFF_FFFF Sync memory (nSDCE2) Sync memory (nSDCE2)
0xD000_0000 - 0xDFFF_FFFF Sync memory (nSDCE1) Sync memory (nSDCE1)
0xC000_0000 - 0xCFFF_FFFF Sync memory (nSDCE0) Sync memory (nSDCE0)
0x9000_0000 - 0xBFFF_FFFF Not Used Not Used
0x8080_0000 - 0x8FFF_FFFF APB mapped registers APB mapped registers
0x8010_0000 - 0x807F_FFFF Reserved Reserved
0x8000_0000 - 0x800F_FFFF AHB mapped registers AHB mapped registers
0x7000_0000 - 0x7FFF_FFFF Async memory (nCS7) Async memory (nCS7)
0x6000_0000 - 0x6FFF_FFFF Async memory (nCS6) Async memory (nCS6)
0x5000_0000 - 0x5FFF_FFFF PCMCIA (Slot 1) PCMCIA (Slot 1)
0x4000_0000 - 0x4FFF_FFFF PCMCIA (Slot 0) PCMCIA (Slot 0)
0x3000_0000 - 0x3FFF_FFFF Async memory (nCS3) Async memory (nCS3)
0x2000_0000 - 0x2FFF_FFFF Async memory (nCS2) Async memory (nCS2)
0x1000_0000 - 0x1FFF_FFFF Async memory (nCS1) Async memory (nCS1)
0x0001_0000 - 0x0FFF_FFFF Sync memory (nSDCE3) Async memory (nCS0)
EP9315 User’s Manual - DS638UM1 51 Copyright 2004 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-6: Global Memory Map for the Two Boot Modes (Continued)
Address Range Sync Memory Boot Async Memory Boot
2
0x0000_0000 - 0x0000_FFFF
Note: The shaded areas are the memory areas dedicated to system registers. Details
of these registers are in Table 2-7.

2.3.6 Internal Register Map

Registers are set to their default state by the RSTOn pin and by the PRSTn pin inputs. Some state conserving registers are reset only by the PRSTn pin. All registers are read/write unless specified otherwise.
2.3.6.1 Memory Access Rules
Any memory address not specifically assigned to a register should be avoided. Reads to register memory addresses labelled Reserved, Unused or Undefined will return indeterminate data. Writes to register memory addresses labelled Reserved, Unused or Undefined are generally ignored, but this behavior is not guaranteed. Many register addresses are not fully decoded, so aliasing may occur. Addresses and memory ranges listed as Reserved (RSVD) should not be accessed; access behavior to these regions is not defined.
ASD0 Pin = 1 ASD0 Pin = 0
Sync memory (nSDCE3)
or
Internal Boot ROM
if INTBOOT selected
Async memory (nCS0)
Internal Boot ROM
if INTBOOT selected
or
The SW Lock field identifies registers with a software lock. The software lock prevents the register from being written unless a proper unlock operation is performed immediately prior to writing the target register. Any register whose accidental alteration could cause system damage is controlled with a software lock. Each peripheral with software lock capability has its own software lock register.
Within a register definition, a reserved bit, indicated the name RSVD, means the bit is not accessible. Software should mask the RSVD bits when doing bit reads. RSVD bits will ignore writes, that is writing a zero or a one does not matter.
Register bits identified as NC must be treated in a specific manner for reads and writes; see the register description for each register for information on how to read and write register bits identified as NC. Register bits identified as NC are functionally alive but have an undocumented or a “don’t care” operating function. The register description will provide information on how to handle NC bits.
Unless specified otherwise, all registers can be accessed as a byte, half-word, or word.
Copyright 2004 Cirrus Logic
CAUTION: Some memory locations are listed as Reserved. These memory
locations should not be used. Reading from these memory locations will yield invalid data. Writing to these memory locations may cause unpredictable results.
Table 2-7: Internal Register Map
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
2
Address Register Name Register Description
0x8000_xxxx
0x8000_0000 - 0x8000_003C M2P Channel 0 Registers (Tx) Memory-to-Peripheral Channel 0 Registers (Tx) N
0x8000_0040 - 0x8000_007C M2P Channel 1 Registers (Rx) Memory-to-Peripheral Channel 1 Registers (Rx) N
0x8000_0080 - 0x8000_00BC M2P Channel 2 Registers (Tx) Memory-to-Peripheral Channel 2 Registers (Tx) N
0x8000_00C0 - 0x8000_00FC M2P Channel 3 Registers (Rx) Memory-to-Peripheral Channel 3 Registers (Rx) N
0x8000_0100 - 0x8000_013C M2M Channel 0 Registers Memory-to-Memory Channel 0 Registers N
0x8000_0140 - 0x8000_017C M2M Channel 1 Registers Memory-to-Memory Channel 1 Registers N
0x8000_0180 - 0x8000_01FC Reserved
0x8000_0200 - 0x8000_023C M2P Channel 5 Registers (Rx) Memory-to-Peripheral Channel 5 Registers (Rx) N
0x8000_0240 - 0x8000_027C M2P Channel 4 Registers (Tx) Memory-to-Peripheral Channel 4 Registers (Tx) N
0x8000_0280 - 0x8000_02BC M2P Channel 7 Registers (Rx) Memory-to-Peripheral Channel 7 Registers (Rx) N
0x8000_02C0 - 0x8000_02FC M2P Channel 6 Registers (Tx) Memory-to-Peripheral Channel 6 Registers (Tx) N
0x8000_0300 - 0x8000_033C M2P Channel 9 Registers (Rx) Memory-to-Peripheral Channel 9 Registers (Rx) N
0x8000_0340 - 0x8000_037C M2P Channel 8 Registers (Tx) Memory-to-Peripheral Channel 8 Registers (Tx) N
0x8000_0380 DMAChArb DMA Channel Arbitration Register N
0x8000_03C0 DMAGlInt DMA Global Interrupt Register N
0x8000_03C4 - 0x8000_FFFC Reserved
0x8001_xxxx
0x8001_0000 RXCtl MAC Receiver Control Register N
0x8001_0004 TXCtl MAC Transmitter Control Register N
0x8001_0008 TestCtl MAC Test Control Register N
0x8001_0010 MIICmd MAC MII Command Register N
0x8001_0014 MIIData MAC MII Data Register N
0x8001_0018 MIISts MAC MII Status Register N
0x8001_0020 SelfCtl MAC Self Control Register N
0x8001_0024 IntEn MAC Interrupt Enable Register N
0x8001_0028 IntStsP MAC Interrupt Status Preserve Register N
0x8001_002C IntStsC MAC Interrupt Status Clear Register N
0x8001_0030 - 0x8001_0034 Reserved
0x8001_0038 DiagAd MAC Diagnostic Address Register N
0x8001_003C DiagDa MAC Diagnostic Data Register N
0x8001_0040 GT MAC General Timer Register N
0x8001_0044 FCT MAC Flow Control Timer Register N
0x8001_0048 FCF MAC Flow Control Format Register N
0x8001_004C AFP MAC Address Filter Pointer Register N
0x8001_0050 - 0x8001_0055 IndAd
DMA DMA Control Registers
Ethernet MAC Ethernet MAC Control Registers
MAC Individual Address Register, (shares address space with HashTbl)
SW
Lock
N
EP9315 User’s Manual - DS638UM1 53 Copyright 2004 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-7: Internal Register Map (Continued)
2
Address Register Name Register Description
0x8001_0050 - 0x8001_0057 HashTbl MAC Hash Table Register, (shares address space with IndAd) N
0x8001_0060 GlIntSts MAC Global Interrupt Status Register N
0x8001_0064 GlIntMsk MAC Global Interrupt Mask Register N
0x8001_0068 GlIntROSts MAC Global Interrupt Read Only Status Register N
0x8001_006C GlIntFrc MAC Global Interrupt Force Register N
0x8001_0070 TXCollCnt MAC Transmit Collision Count Register N
0x8001_0074 RXMissCnt MAC Receive Miss Count Register N
0x8001_0078 RXRuntCnt MAC Receive Runt Count Register N
0x8001_0080 BMCtl MAC Bus Master Control Register N
0x8001_0084 BMSts MAC Bus Master Status Register N
0x8001_0088 RXBCA MAC Receive Buffer Current Address Register N
0x8001_0090 RXDQBAdd MAC Receive Descriptor Queue Base Address Register N
0x8001_0094 RXDQBLen MAC Receive Descriptor Queue Base Length Register N
0x8001_0096 RXDQCurLen MAC Receive Descriptor Queue Current Length Register N
0x8001_0098 RXDCurAdd MAC Receive Descriptor Current Address Register N
0x8001_009C RXDEnq MAC Receive Descriptor Enqueue Register N
0x8001_00A0 RXStsQBAdd MAC Receive Status Queue Base Address Register N
0x8001_00A4 RXStsQBLen MAC Receive Status Queue Base Length Register N
0x8001_00A6 RXStsQCurLen MAC Receive Status Queue Current Length Register N
0x8001_00A8 RXStsQCurAdd MAC Receive Status Queue Current Address Register N
0x8001_00AC RXStsEnq MAC Receive Status Enqueue Register N
0x8001_00B0 TXDQBAdd MAC Transmit Descriptor Queue Base Address Register N
0x8001_00B4 TXDQBLen MAC Transmit Descriptor Queue Base Length Register N
0x8001_00B6 TXDQCurLen MAC Transmit Descriptor Queue Current Length Register N
0x8001_00B8 TXDQCurAdd MAC Transmit Descriptor Current Address Register N
0x8001_00BC TXDEnq MAC Transmit Descriptor Enqueue Register N
0x8001_00C0 TXStsQBAdd MAC Transmit Status Queue Base Address Register N
0x8001_00C4 TXStsQBLen MAC Transmit Status Queue Base Length Register N
0x8001_00C6 TXStsQCurLen MAC Transmit Status Queue Current Length Register N
0x8001_00C8 TXStsQCurAdd MAC Transmit Status Queue Current Address Register N
0x8001_00D0 RXBufThrshld MAC Receive Buffer Threshold Register N
0x8001_00D4 TXBufThrshld MAC Transmit Buffer Threshold Register N
0x8001_00D8 RXStsThrshld MAC Receive Status Threshold Register N
0x8001_00DC TXStsThrshld MAC Transmit Status Threshold Register N
0x8001_00E0 RXDThrshld MAC Receive Descriptor Threshold Register N
0x8001_00E4 TXDThrshld MAC Transmit Descriptor Threshold Register N
0x8001_00E8 MaxFrmLen MAC Maximum Frame Length Register N
0x8001_00EC RXHdrLen MAC Receive Header Length Register N
0x8001_0100 - 0x8001_010C Reserved
0x8001_4000 - 0x8001_50FF MACFIFO MAC FIFO RAM N
SW
Lock
0x8002_xxxx
0x8002_0000 HcRevision USB Host Controller Revision N
USB USB Registers N
Copyright 2004 Cirrus Logic
Table 2-7: Internal Register Map (Continued)
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
Address Register Name Register Description
0x8002_0004 HcControl USB Host Controller Control N
0x8002_0008 HcCommandStatus USB Host Controller Command Status N
0x8002_000C HcInterruptStatus USB Host Controller Interrupt Status N
0x8002_0010 HcInterruptEnable USB Host Controller Interrupt Enable N
0x8002_0014 HcInterruptDisable USB Host Controller Interrupt Disable N
0x8002_0018 HcHCCA USB Host Controller HCCA N
0x8002_001C HcPeriodCurrentED USB Host Controller Period CurrentED N
0x8002_0020 HcControlHeadED USB Host Controller Control HeadED N
0x8002_0024 HcControlCurrentED USB Host Controller Control CurrentED N
0x8002_0028 HcBulkHeadED USB Host Controller Bulk HeadED N
0x8002_002C HcBulkCurrentED USB Host Controller Bulk CurrentED N
0x8002_0030 HcDoneHead USB Host Controller Done Head N
0x8002_0034 HcFmInterval USB Host Controller Fm Interval N
0x8002_0038 HcFmRemaining USB Host Controller Fm Remaining N
0x8002_003C HcFmNumber USB Host Controller Fm Number N
0x8002_0040 HcPeriodicStart USB Host Controller Periodic Start N
0x8002_0044 HcLSThreshold USB Host Controller LS Threshold N
0x8002_0048 HcRhDescriptorA USB Host Controller Root Hub Descriptor A N
0x8002_004C HcRhDescriptorB USB Host Controller Root Hub Descriptor B N
0x8002_0050 HcRhStatus USB Host Controller Root Hub Status N
0x8002_0054 HcRhPortStatus[1] USB Host Controller Root Hub Port Status 1 N
0x8002_0058 HcRhPortStatus[2] USB Host Controller Root Hub Port Status 2 N
0x8002_005C HcRhPortStatus[3] USB Host Controller Root Hub Port Status 3 N
0x8002_0080 USBCtrl USB Configuration Control N
0x8002_0084 USBHCI USB Host Controller Interface Status N
SW
Lock
2
0x8003_xxxx
0x8003_0000 VLinesTotal Total Number of vertical frame lines Y
0x8003_0004 VSyncStrtStop Vertical sync pulse setup Y
0x8003_0008 VActiveStrtStop Vertical blanking setup Y
0x8003_000C VClkStrtStop Vertical clock active frame Y
0x8003_0010 HClkTotal Total Number of horizontal line clocks Y
0x8003_0014 HSyncStrtStop Horizontal sync pulse setup Y
0x8003_0018 HActiveStrtStop Horizontal blanking setup Y
0x8003_001C HClkStrtStop Horizontal clock active frame Y
0x8003_0020 Brightness PWM brightness control N
0x8003_0024 VideoAttribs Video state machine parameters Y
0x8003_0028 VidScrnPage Starting address of video screen N
0x8003_002C VidScrnHPage Starting address of video screen half page N
0x8003_0030 ScrnLines Number of active lines scanned to the screen N
0x8003_0034 LineLength Length in words of data for lines N
0x8003_0038 VLineStep Memory step for each line N
0x8003_003C LineCarry Horizontal/vertical offset parameter Y
EP9315 User’s Manual - DS638UM1 55 Copyright 2004 Cirrus Logic
RASTER Raster Control Registers
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-7: Internal Register Map (Continued)
2
Address Register Name Register Description
0x8003_0040 BlinkRate Blink counter setup N
0x8003_0044 BlinkMask Logic mask applied to pixel to perform blink operation N
0x8003_0048 BlinkPattrn Compare value for determining blinking pixels N
0x8003_004C PattrnMask Mask to limit pattern N
0x8003_0050 BkgrndOffset Background color or blink offset value N
0x8003_0054 PixelMode Pixel mode definition setup Register N
0x8003_0058 ParllIfOut Parallel interface write/control Register N
0x8003_005C ParllIfIn Parallel interface read/setup Register N
0x8003_0060 CursorAdrStart Word location of the top left corner of cursor to be displayed N
0x8003_0064 CursorAdrReset Location of first word of cursor to be scanned after last line N
0x8003_0068 CursorSize Cursor height, width, and step size Register N
0x8003_006C CursorColor1 Cursor color overlaid when cursor value is 10 N
0x8003_0070 CursorColor2 Cursor color overlaid when cursor value is 11 N
0x8003_0074 CursorXYLoc Cursor X and Y location Register N
0x8003_0078 CursorDScanLHYLoc Cursor dual scan lower half Y location Register N
0x8003_007C RasterSWLock
0x8003_0080 - 0x8003_00FC GrySclLUTR Grayscale Look Up Table N
0x8003_0200 VidSigRsltVal Video signature result value N
0x8003_0204 VidSigCtrl Video signature Control Register N
0x8003_0208 VSigStrtStop Vertical signature bounds setup N
0x8003_020C HSigStrtStop Horizontal signature bounds setup N
0x8003_0210 SigClrStr Signature clear and store location N
0x8003_0214 ACRate LCD AC voltage bias control counter setup N
0x8003_0218 LUTSwCtrl LUT switching control Register N
0x8003_021C CursorBlinkColor1 Cursor Blink color 1 N
0x8003_0220 CursorBlinkColor2 Cursor Blink color 2 N
0x8003_0224 CursorBlinkRateCtrl Cursor Blink rate control Register N
0x8003_0228 VBlankStrtStop Vertical Blank signal Start/Stop Register N
0x8003_022C HBlankStrtStop Horizontal Blank signal Start/Stop Register N
0x8003_0230 EOLOffset End Of Line Offset value N
0x8003_0234 FIFOLevel FIFO refill level Register N
0x8003_0280 - 0x8003_02FC GrySclLUTG Grayscale Look Up Table N
0x8003_0300 - 0x8003_037C GrySclLUTB Grayscale Look Up Table N
0x8003_0400 - 0x8003_07FC ColorLUT Color Look Up Table N
Software Lock Register. Register used to unlock registers that have SWLOCK
SW
Lock
N
0x8004_xxxx - 0x8005_xxxx Reserved
0x8006_xxxx
0x8006_0000 Reserved
0x8006_0004 GlConfig Control and status bits used in configuration N
0x8006_0008 RefrshTimr Set the period between refresh cycles N
0x8006_000C BootSts Reflect the state of the boot mode option pins N
SDRAM SDRAM Registers N
Copyright 2004 Cirrus Logic
Table 2-7: Internal Register Map (Continued)
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
Address Register Name Register Description
0x8006_0010 SDRAMDevCfg0 Device configuration 0 N
0x8006_0014 SDRAMDevCfg1 Device configuration 1 N
0x8006_0018 SDRAMDevCfg2 Device configuration 2 N
0x8006_001C SDRAMDevCfg3 Device configuration 3 N
0x8008_xxxx
0x8008_0000 SMCBCR0
0x8008_0004 SMCBCR1
0x8008_0008 SMCBCR2
0x8008_000C SMCBCR3
0x8008_0010 - 0x8008_0014 Reserved
0x8008_0018 SMCBCR6
0x8008_001C SMCBCR7
0x8008_0020 PC1Attribute PC1 Attribute Register
0x8008_0024 PC1Common PC1 Common Register
0x8008_0028 PC1IO PC1 IO Register
0x8008_002C Reserved
0x8008_0030 PC2Attribute PC2 Attribute Register
0x8008_0034 PC2Common PC2 Common Register
0x8008_0038 PC2IO PC2 IO Register
0x8008_003C Reserved
0x8008_0040 PCMCIACtrl PCMCIA Control register
0x8008_0044 - 0x8008_FFFC Reserved
SMC SMC and PCMCIA Control Registers
Bank config Register 0 (used to program characteristics of the SRAM/ROM memory)
Bank config Register 1 (used to program characteristics of the SRAM/ROM memory)
Bank config Register 2 (used to program characteristics of the SRAM/ROM memory)
Bank config Register 3 (used to program characteristics of the SRAM/ROM memory)
Bank config Register 6 (used to program characteristics of the SRAM/ROM memory)
Bank config Register 7 (used to program characteristics of the SRAM/ROM memory)
SW
Lock
2
N
N
N
N
N
N
0x8009_xxxx
0x8009_0000 Boot ROM Start N
0x8009_3FFF Boot ROM End N
0x800A_xxxx
0x800A_0000 IDECtrl IDE Control Register N
0x800A_0004 IDECfg IDE Configuration Register N
0x800A_0008 IDEMDMAOp IDE MDMA Operation Register N
0x800A_000C IDEUDMAOp IDE UDMA Operation Register N
0x800A_0010 IDEDataOut IDE PIO Data Output Register N
0x800A_0014 IDEDataIn IDE PIO Data Input Register N
0x800A_0018 IDEMDMADataOut IDE MDMA Data Output Register N
0x800A_001C IDEMDMADataIn IDE MDMA Data Input Register N
EP9315 User’s Manual - DS638UM1 57 Copyright 2004 Cirrus Logic
Boot ROM Boot ROM Memory Locations
IDE IDE Control Registers
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-7: Internal Register Map (Continued)
2
Address Register Name Register Description
0x800A_0020 IDEUDMADataOut IDE UDMA Data Output Register N
0x800A_0024 IDEUDMADataIn IDE UDMA Data Input Register N
0x800A_0028 IDEUDMASts IDE UDMA Status Register N
0x800A_002C IDEUDMADebug IDE UDMA Debug Register N
0x800A_0030 IDEUDMAWrBufSts IDE UDMA Write Buffer Status Register N
0x800A_0034 IDEUDMARdBufSts IDE UDMA Read Buffer Status Register N
0x800B_xxxx
0x800B_0000 VIC1IRQStatus IRQ status Register N
0x800B_0004 VIC1FIQStatus FIQ status Register N
0x800B_0008 VIC1RawIntr Raw interrupt status Register N
0x800B_000C VIC1IntSelect Interrupt select Register N
0x800B_0010 VIC1IntEnable Interrupt enable Register N
0x800B_0014 VIC1IntEnClear Interrupt enable clear Register N
0x800B_0018 VIC1SoftInt Software interrupt Register N
0x800B_001C VIC1SoftIntClear Software interrupt clear Register N
0x800B_0020 VIC1Protection Protection enable Register N
0x800B_0030 VIC1VectAddr Vector address Register N
0x800B_0034 VIC1DefVectAddr Default vector address Register N
0x800B_0100 VIC1VectAddr0 Vector address 0 Register N
0x800B_0104 VIC1VectAddr1 Vector address 1 Register N
0x800B_0108 VIC1VectAddr2 Vector address 2 Register N
0x800B_010C VIC1VectAddr3 Vector address 3 Register N
0x800B_0110 VIC1VectAddr4 Vector address 4 Register N
0x800B_0114 VIC1VectAddr5 Vector address 5 Register N
0x800B_0118 VIC1VectAddr6 Vector address 6 Register N
0x800B_011C VIC1VectAddr7 Vector address 7 Register N
0x800B_0120 VIC1VectAddr8 Vector address 8 Register N
0x800B_0124 VIC1VectAddr9 Vector address 9 Register N
0x800B_0128 VIC1VectAddr10 Vector address 10 Register N
0x800B_012C VIC1VectAddr11 Vector address 11 Register N
0x800B_0130 VIC1VectAddr12 Vector address 12 Register N
0x800B_0134 VIC1VectAddr13 Vector address 13 Register N
0x800B_0138 VIC1VectAddr14 Vector address 14 Register N
0x800B_013C VIC1VectAddr15 Vector address 15 Register N
0x800B_0200 VIC1VectCntl0 Vector control 0 Register N
0x800B_0204 VIC1VectCntl1 Vector control 1 Register N
0x800B_0208 VIC1VectCntl2 Vector control 2 Register N
0x800B_020C VIC1VectCntl3 Vector control3 Register N
0x800B_0210 VIC1VectCntl4 Vector control 4 Register N
0x800B_0214 VIC1VectCntl5 Vector control 5 Register N
0x800B_0218 VIC1VectCntl6 Vector control 6 Register N
0x800B_021C VIC1VectCntl7 Vector control 7 Register N
VIC1 Vectored Interrupt Controller 1 Registers
SW
Lock
Copyright 2004 Cirrus Logic
Table 2-7: Internal Register Map (Continued)
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
Address Register Name Register Description
0x800B_0220 VIC1VectCntl8 Vector control 8 Register N
0x800B_0224 VIC1VectCntl9 Vector control 9 Register N
0x800B_0228 VIC1VectCntl10 Vector control 10 Register N
0x800B_022C VIC1VectCntl11 Vector control 11 Register N
0x800B_0230 VIC1VectCntl12 Vector control 12 Register N
0x800B_0234 VIC1VectCntl13 Vector control 13 Register N
0x800B_0238 VIC1VectCntl14 Vector control 14 Register N
0x800B_023C VIC1VectCntl15 Vector control 15 Register N
0x800B_0FE0 VIC1PeriphID0 Peripheral identification Register bits 7:0 N
0x800B_0FE4 VIC1PeriphID1 Peripheral identification Register bits 15:8 N
0x800B_0FE8 VIC1PeriphID2 Peripheral identification Register bits 23:16 N
0x800B_0FEC VIC1PeriphID3 Peripheral identification Register bits 31:24 N
0x800B_0FF0 - 0x800B_0FFC Reserved N
0x800C_xxxx
0x800C_0000 VIC2IRQStatus IRQ status Register N
0x800C_0004 VIC2FIQStatus FIQ status Register N
0x800C_0008 VIC2RawIntr Raw interrupt status Register N
0x800C_000C VIC2IntSelect Interrupt select Register N
0x800C_0010 VIC2IntEnable Interrupt enable Register N
0x800C_0014 VIC2IntEnClear Interrupt enable clear Register N
0x800C_0018 VIC2SoftInt Software interrupt Register N
0x800C_001C VIC2SoftIntClear Software interrupt clear Register N
0x800C_0020 VIC2Protection Protection enable Register N
0x800C_0030 VIC2VectAddr Vector address Register N
0x800C_0034 VIC2DefVectAddr Default vector address Register N
0x800C_0100 VIC2VectAddr0 Vector address 0 Register N
0x800C_0104 VIC2VectAddr1 Vector address 1 Register N
0x800C_0108 VIC2VectAddr2 Vector address 2 Register N
0x800C_010C VIC2VectAddr3 Vector address 3 Register N
0x800C_0110 VIC2VectAddr4 Vector address 4 Register N
0x800C_0114 VIC2VectAddr5 Vector address 5 Register N
0x800C_0118 VIC2VectAddr6 Vector address 6 Register N
0x800C_011C VIC2VectAddr7 Vector address 7 Register N
0x800C_0120 VIC2VectAddr8 Vector address 8 Register N
0x800C_0124 VIC2VectAddr9 Vector address 9 Register N
0x800C_0128 VIC2VectAddr10 Vector address 10 Register N
0x800C_012C VIC2VectAddr11 Vector address 11 Register N
0x800C_0130 VIC2VectAddr12 Vector address 12 Register N
0x800C_0134 VIC2VectAddr13 Vector address 13 Register N
0x800C_0138 VIC2VectAddr14 Vector address 14 Register N
0x800C_013C VIC2VectAddr15 Vector address 15 Register N
0x800C_0200 VIC2VectCntl0 Vector control 0 Register N
VIC2 Vectored Interrupt Controller 2 Registers
SW
Lock
2
EP9315 User’s Manual - DS638UM1 59 Copyright 2004 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-7: Internal Register Map (Continued)
2
Address Register Name Register Description
0x800C_0204 VIC2VectCntl1 Vector control 1 Register N
0x800C_0208 VIC2VectCntl2 Vector control 2 Register N
0x800C_020C VIC2VectCntl3 Vector control3 Register N
0x800C_0210 VIC2VectCntl4 Vector control 4 Register N
0x800C_0214 VIC2VectCntl5 Vector control 5 Register N
0x800C_0218 VIC2VectCntl6 Vector control 6 Register N
0x800C_021C VIC2VectCntl7 Vector control 7 Register N
0x800C_0220 VIC2VectCntl8 Vector control 8 Register N
0x800C_0224 VIC2VectCntl9 Vector control 9 Register N
0x800C_0228 VIC2VectCntl10 Vector control 10 Register N
0x800C_022C VIC2VectCntl11 Vector control 11 Register N
0x800C_0230 VIC2VectCntl12 Vector control 12 Register N
0x800C_0234 VIC2VectCntl13 Vector control 13 Register N
0x800C_0238 VIC2VectCntl14 Vector control 14 Register N
0x800C_023C VIC2VectCntl15 Vector control 15 Register N
0x800C_0FE0 VIC2PeriphID0 Peripheral identification Register bits 7:0 N
0x800C_0FE4 VIC2PeriphID1 Peripheral identification Register bits 15:8 N
0x800C_0FE8 VIC2PeriphID2 Peripheral identification Register bits 23:16 N
0x800C_0FEC VIC2PeriphID3 Peripheral identification Register bits 31:24 N
0x800C_0FF0 - 0x800C_0FFC Reserved N
SW
Lock
0x8081_xxxx
0x8081_0000 Timer1Load Contains the initial value of the timer N
0x8081_0004 Timer1Value Gives the current value of the timer N
0x8081_0008 Timer1Control Provides enable/disable and mode configurations for the timer N
0x8081_000C Timer1Clear Clears an interrupt generated by the timer N
0x8081_0020 Timer2Load Contains the initial value of the timer N
0x8081_0024 Timer2Value Gives the current value of the timer N
0x8081_0028 Timer2Control Provides enable/disable and mode configurations for the timer N
0x8081_002C Timer2Clear Clears an interrupt generated by the timer N
0x8081_0060 - 0x8081_0064 Reserved
0x8081_0080 Timer3Load Contains the initial value of the timer N
0x8081_0084 Timer3Value Gives the current value of the timer N
0x8081_0088 Timer3Control Provides enable/disable and mode configurations for the timer N
0x8081_008C Timer3Clear Clears an interrupt generated by the timer N
0x8082_xxxx
0x8082_0000 I2STXClkCfg Transmitter clock configuration Register N
0x8082_0004 I2SRXClkCfg Receiver clock configuration Register N
0x8082_0008 I2SGlSts
0x8082_000C I2SGlCtrl I2S Global Control Register N
0x8082_0010 I2STX0Lft Left Transmit data Register for channel 0 N
TIMER Timer Registers
I2S I2S Registers N
I2S Global Status Register. This reflects the status of the 3 RX FIFOs and the 3 TX FIFOs
N
Copyright 2004 Cirrus Logic
Table 2-7: Internal Register Map (Continued)
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
Address Register Name Register Description
0x8082_0014 I2STX0Rt Right Transmit data Register for channel 0 N
0x8082_0018 I2STX1Lft Left Transmit data Register for channel 1 N
0x8082_001C I2STX1Rt Right Transmit data Register for channel 1 N
0x8082_0020 I2STX2Lft Left Transmit data Register for channel 2 N
0x8082_0024 I2STX2Rt Right Transmit data Register for channel 2 N
0x8082_0028 I2STXLinCtrlData Transmit Line Control Register N
0x8082_002C I2STXCtrl Transmit Control Register N
0x8082_0030 I2STXWrdLen Transmit Word Length N
0x8082_0034 I2STX0En TX0 Channel Enable N
0x8082_0038 I2STX1En TX1 Channel Enable N
0x8082_003C I2STX2En TX2 Channel Enable N
0x8082_0040 I2SRX0Lft Left Receive data Register for channel 0 N
0x8082_0044 I2SRX0Rt Right Receive data Register for channel 0 N
0x8082_0048 I2SRX1Lft Left Receive data Register for channel 1 N
0x8082_004C I2SRX1Rt Right Receive data Register for channel 1 N
0x8082_0050 I2SRX2Lft Left Receive data Register for channel 2 N
0x8082_0054 I2SRX2Rt Right Receive data Register for channel 2 N
0x8082_0058 I2SRXLinCtrlData Receive Line Control Register N
0x8082_005C I2SRXCtrl Receive Control Register N
0x8082_0060 I2SRXWrdLen Receive Word Length N
0x8082_0064 I2SRX0En RX0 Channel Enable N
0x8082_0068 I2SRX1En RX1 Channel Enable N
0x8082_006C I2SRX2En RX2 Channel Enable N
SW
Lock
2
0x8083_xxxx
0x8083_2714 ExtensionID Contains the Part ID for EP93XX devices N
Contact Cirrus Logic for details regarding implementation of device Security measures.
0x8084_xxxx
0x8084_0000 PADR GPIO Port A Data Register N
0x8084_0004 PBDR GPIO Port B Data Register N
0x8084_0008 PCDR GPIO Port C Data Register N
0x8084_000C PDDR GPIO Port D Data Register N
0x8084_0010 PADDR GPIO Port A Data Direction Register N
0x8084_0014 PBDDR GPIO Port B Data Direction Register N
0x8084_0018 PCDDR GPIO Port C Data Direction Register N
0x8084_001C PDDDR GPIO Port D Data Direction Register N
0x8084_0020 PEDR GPIO Port E Data Register N
0x8084_0024 PEDDR GPIO Port E Data Direction Register N
0x8084_0028 - 0x8084_002C Reserved
0x8084_0030 PFDR GPIO Port F Data Register N
0x8084_0034 PFDDR GPIO Port F Data Direction Register N
EP9315 User’s Manual - DS638UM1 61 Copyright 2004 Cirrus Logic
SECURITY Security Registers
GPIO GPIO Control Registers
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-7: Internal Register Map (Continued)
2
Address Register Name Register Description
0x8084_0038 PGDR GPIO Port G Data Register N
0x8084_003C PGDDR GPIO Port G Data Direction Register N
0x8084_0040 PHDR GPIO Port H Data Register N
0x8084_0044 PHDDR GPIO Port H Data Direction Register N
0x8084_0048 Reserved
0x8084_004C GPIOFIntType1
0x8084_0050 GPIOFIntType2
0x8084_0054 GPIOFEOI GPIO Port F End Of Interrupt Register N
0x8084_0058 GPIOFIntEn Interrupt Enable for Port F N
0x8084_005C IntStsF
0x8084_0060 RawIntStsF
0x8084_0064 GPIOFDB GPIO F Debounce Register N
0x8084_0068 - 0x8084_008C Reserved
0x8084_0090 GPIOAIntType1
0x8084_0094 GPIOAIntType2
0x8084_0098 GPIOAEOI GPIO Port A End Of Interrupt Register N
0x8084_009C GPIOAIntEn Controlling the generation of interrupts by the pins of Port A N
0x8084_00A0 IntStsA
0x8084_00A4 RawIntStsA
0x8084_00A8 GPIOADB GPIO A Debounce Register N
0x8084_00AC GPIOBIntType1
0x8084_00B0 GPIOBIntType2
0x8084_00B4 GPIOBEOI GPIO Port B End Of Interrupt Register N
0x8084_00B8 GPIOBIntEn Controlling the generation of interrupts by the pins of Port B N
0x8084_00BC IntStsB
0x8084_00C0 RawIntStsB
0x8084_00C4 GPIOBDB GPIO B Debounce Register N
0x8084_00C8 EEDrive
Register controlling type, level or edge, of interrupt generated by the pins of Port F
Register controlling polarity, high/low or rising/falling, of interrupt generated by Port F
GPIO Interrupt Status Register. Contains status of Port F interrupts after masking.
Raw Interrupt Status Register. Contains raw interrupt status of Port F before masking.
Register controlling type, level or edge, of interrupt generated by the pins of Port A
Register controlling polarity, high/low or rising/falling, of interrupt generated by Port A
GPIO Interrupt Status Register. Contains status of Port A interrupts after masking.
Raw Interrupt Status Register. Contains raw interrupt status of Port A before masking.
Register controlling type, level or edge, of interrupt generated by the pins of Port B
Register controlling polarity, high/low or rising/falling, of interrupt generated by Port B
GPIO Interrupt Status Register. Contains status of Port B interrupts after masking.
Raw Interrupt Status Register. Contains raw interrupt status of Port B before masking.
EEPROM pin drive type control. Defines the driver type for the EECLK and EEDAT pins
SW
Lock
N
N
N
N
N
N
N
N
N
N
N
N
N
0x8088_xxxx
0x8088_0000 AC97DR1 Data read or written from/to FIFO1 N
0x8088_0004 AC97RXCR1 Control Register for receive N
0x8088_0008 AC97TXCR1 Control Register for transmit N
AC’97 AC’97 Control Registers
Copyright 2004 Cirrus Logic
Table 2-7: Internal Register Map (Continued)
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
Address Register Name Register Description
0x8088_000C AC97SR1 Status Register N
0x8088_0010 AC97RISR1 Raw interrupt status Register N
0x8088_0014 AC97ISR1 Interrupt Status N
0x8088_0018 AC97IE1 Interrupt Enable N
0x8088_001C Reserved
0x8088_0020 AC97DR2 Data read or written from/to FIFO2 N
0x8088_0024 AC97RXCR2 Control Register for receive N
0x8088_0028 AC97TXCR2 Control Register for transmit N
0x8088_002C AC97SR2 Status Register N
0x8088_0030 AC97RISR2 Raw interrupt status Register N
0x8088_0034 AC97ISR2 Interrupt Status N
0x8088_0038 AC97IE2 Interrupt Enable N
0x8088_003C Reserved
0x8088_0040 AC97DR3 Data read or written from/to FIFO3 N
0x8088_0044 AC97RXCR3 Control Register for receive N
0x8088_0048 AC97TXCR3 Control Register for transmit N
0x8088_004C AC97SR3 Status Register N
0x8088_0050 AC97RISR3 Raw interrupt status Register N
0x8088_0054 AC97ISR3 Interrupt Status N
0x8088_0058 AC97IE3 Interrupt Enable N
0x8088_005C Reserved
0x8088_0060 AC97DR4 Data read or written from/to FIFO4 N
0x8088_0064 AC97RXCR4 Control Register for receive N
0x8088_0068 AC97TXCR4 Control Register for transmit N
0x8088_006C AC97SR4 Status Register N
0x8088_0070 AC97RISR4 Raw interrupt status Register N
0x8088_0074 AC97ISR4 Interrupt Status N
0x8088_0078 AC97IE4 Interrupt Enable N
0x8088_007C Reserved
0x8088_0080 AC97S1Data Data received/transmitted on SLOT1 N
0x8088_0084 AC97S2Data Data received/transmitted on SLOT2 N
0x8088_0088 AC97S12Data Data received/transmitted on SLOT12 N
0x8088_008C AC97RGIS Raw Global interrupt status Register N
0x8088_0090 AC97GIS Global interrupt status Register N
0x8088_0094 AC97IM Interrupt mask Register N
0x8088_0098 AC97EOI End Of Interrupt Register N
0x8088_009C AC97GCR Main Control Register N
0x8088_00A0 AC97Reset RESET control Register N
0x8088_00A4 AC97SYNC SYNC control Register N
0x8088_00A8 AC97GCIS Global channel FIFO interrupt status Register N
SW
Lock
2
0x808A_xxxx
0x808A_0000 SSP1CR0 SPI1 Control Register 0 N
EP9315 User’s Manual - DS638UM1 63 Copyright 2004 Cirrus Logic
SPI SPI Control Registers
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-7: Internal Register Map (Continued)
2
Address Register Name Register Description
0x808A_0004 SSP1CR1 SPI1 Control Register 1 N
0x808A_0008 SSP1DR SPI1 Data Register N
0x808A_000C SSP1SR SPI1 Status Register N
0x808A_0010 SSP1CPSR SPI1 Clock Prescale Register N
0x808A_0014 SSP1IIR SPI1 Interrupt/Interrupt Clear Register N
0x808B_xxxx
0x808B_0000 IrEnable IrDA Interface Enable N
0x808B_0004 IrCtrl IrDA Control Register N
0x808B_0008 IrAdrMatchVal IrDA Address Match Value Register N
0x808B_000C IrFlag IrDA Flag Register N
0x808B_0010 IrData IrDA Transmit and Receive FIFOs N
0x808B_0014 IrDataTail IrDA Data Tail Register N
0x808B_0018 - 0x808B_001C Reserved
0x808B_0020 IrRIB IrDA Receive Information Buffer N
0x808B_0024 IrTR0 IrDA Test Register, Received byte count N
0x808B_0088 MIIR IrDA MIR Interrupt Register N
0x808B_008C - 0x808B_018C Reserved
0x808C_xxxx
0x808C_0000 UART1Data UART1 Data Register N
0x808C_0004 UART1RXSts UART1 Receive Status Register N
0x808C_0008 UART1LinCtrlHigh UART1 Line Control Register - High Byte N
0x808C_000C UART1LinCtrlMid UART1 Line Control Register - Middle Byte N
0x808C_0010 UART1LinCtrlLow UART1 Line Control Register - Low Byte N
0x808C_0014 UART1Ctrl UART1 Control Register N
0x808C_0018 UART1Flag UART1 Flag Register N
0x808C_001C UART1IntIDIntClr UART1 Interrupt ID and Interrupt Clear Register N
0x808C_0020 Reserved
0x808C_0028 UART1DMACtrl UART1 DMA Control Register N
0x808C_0100 UART1ModemCtrl UART1 Modem Control Register N
0x808C_0104 UART1ModemSts UART1 Modem Status Register N
0x808C_0114 - 0x808C_0208 Reserved
0x808C_020C UART1HDLCCtrl UART1 HDLC Control Register N
0x808C_0210 UART1HDLCAddMtchVal UART1 HDLC Address Match Value N
0x808C_0214 UART1HDLCAddMask UART1 HDLC Address Mask N
0x808C_0218 UART1HDLCRXInfoBuf UART1 HDLC Receive Information Buffer N
0x808C_021C UART1HDLCSts UART1 HDLC Status Register N
IrDA IrDA Control Registers
UART1 UART1 Control Registers
SW
Lock
0x808D_xxxx
0x808D_0000 UART2Data UART2 Data Register N
0x808D_0004 UART2RXSts UART2 Receive Status Register N
UART2 UART2 Control Registers
Copyright 2004 Cirrus Logic
Table 2-7: Internal Register Map (Continued)
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
Address Register Name Register Description
0x808D_0008 UART2LinCtrlHigh UART2 Line Control Register - High Byte N
0x808D_000C UART2LinCtrlMid UART2 Line Control Register - Middle Byte N
0x808D_0010 UART2LinCtrlLow UART2 Line Control Register - Low Byte N
0x808D_0014 UART2Ctrl UART2 Control Register N
0x808D_0018 UART2Flag UART2 Flag Register N
0x808D_001C UART2IntIDIntClr UART2 Interrupt ID and Interrupt Clear Register N
0x808D_0020 UART2IrLowPwrCntr UART2 IrDA Low-power Counter Register N
0x808D_0028 UART2DMACtrl UART2 DMA Control Register N
0x808E_xxxx
0x808E_0000 UART3Data UART3 Data Register N
0x808E_0004 UART3RXSts UART3 Receive Status Register N
0x808E_0008 UART3LinCtrlHigh UART3 Line Control Register - High Byte N
0x808E_000C UART3LinCtrlMid UART3 Line Control Register - Middle Byte N
0x808E_0010 UART3LinCtrlLow UART3 Line Control Register - Low Byte N
0x808E_0014 UART3Ctrl UART3 Control Register N
0x808E_0018 UART3Flag UART3 Flag Register N
0x808E_001C UART3IntIDIntClr UART3 Interrupt ID and Interrupt Clear Register N
0x808E_0020 UART3IrLowPwrCntr UART3 IrDA Low-power Counter Register N
0x808E_0028 UART3DMACtrl UART3 DMA Control Register N
0x808E_0100 UART3ModemCtrl UART3 Modem Control Register N
0x808E_0104 UART3ModemSts UART3 Modem Status Register N
0x808E_0108 UART3ModemTstCtrl UART3 Modem Support Test Control Register N
0x808E_0114 - 0x808E_0208 Reserved
0x808E_020C UART3HDLCCtrl UART3 HDLC Control Register N
0x808E_0210 UART3HDLCAddMtchVal UART3 HDLC Address Match Value N
0x808E_0214 UART3HDLCAddMask UART3 HDLC Address Mask N
0x808E_0218 UART3HDLCRXInfoBuf UART3 HDLC Receive Information Buffer N
0x808E_021C UART3HDLCSts UART3 HDLC Status Register N
UART3 UART3 Control Registers
SW
Lock
2
0x808F_xxxx
0x808F_0000 KeyScanInit Key Matrix Scan Initialize N
0x808F_0004 KeyDiagnostic Key Matrix Diagnostic N
0x808F_0008 KeyRegister Key Matrix Key Register N
0x8090_xxxx
0x8090_0000 TSSetup Touchscreen Setup Register N
0x8090_0004 TSXYMaxMin Touchscreen X/Y Max Min Register N
0x8090_0008 TSXYResult Touchscreen X/Y Result Register N
0x8090_000C TSDischarge Touchscreen Switch Matrix Discharge Control Register Y
0x8090_0010 TSXSample Touchscreen Switch Matrix X-Sample Control Register Y
0x8090_0014 TSYSample Touchscreen Switch Matrix Y-Sample Control Register Y
EP9315 User’s Manual - DS638UM1 65 Copyright 2004 Cirrus Logic
KEY Key Matrix Control Registers
TOUCH Touchscreen Control Registers
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-7: Internal Register Map (Continued)
2
Address Register Name Register Description
0x8090_0018 TSDirect Touchscreen Switch Matrix Direct Control Register Y
0x8090_001C TSDetect Touchscreen Direct Control Touch Detect Register N
0x8090_0020 TSSWLock Touchscreen Software Lock Register N
0x8090_0024 TSSetup2 Touchscreen Setup Register 2 N
0x8091_xxxx
0x8091_0000 PWM0TermCnt PWM0 Terminal Count N
0x8091_0004 PWM0DutyCycle PWM0 Duty Cycle N
0x8091_0008 PWM0En PWM0 Enable N
0x8091_000C PWM0Invert PWM0 Invert N
0x8091_0010 PWM0Sync PWM0 Synchronous N
0x8091_0020 PWM1_TC PWM1 Terminal Count N
0x8091_0024 PWM1_DC PWM1 Duty Cycle N
0x8091_0028 PWM1_EN PWM1 Enable N
0x8091_002C PWM1_INV PWM1 Invert N
0x8091_0030 PWM1_SYNC PWM1 Synchronous N
0x8092_xxxx
0x8092_0000 RTCData RTC Data Register N
0x8092_0004 RTCMatch RTC Match Register N
0x8092_0008 RTCSts RTC Status/EOI Register N
0x8092_000C RTCLoad RTC Load Register N
0x8092_0010 RTCCtrl RTC Control Register N
0x8092_0108 RTCSWComp RTC Software Compensation N
PWM PWM Control Registers
RTC RTC Control Registers
SW
Lock
0x8093_xxxx
0x8093_0000 PwrSts Power/state control state N
0x8093_0004 PwrCnt Clock/debug control status N
0x8093_0008 Halt Enter IDLE mode N
0x8093_000C Stby Enter Standby mode N
0x8093_0018 TEOI Write to clear Watchdog interrupt N
0x8093_001C STFClr Write to clear Nbflg, rstflg, pfflg and cldflg N
0x8093_0020 ClkSet1 Clock speed control 1 N
0x8093_0024 ClkSet2 Clock speed control 2 N
0x8093_0040 ScratchReg0 Scratch Register 0 N
0x8093_0044 ScratchReg1 Scratch Register 1 N
0x8093_0050 APBWait APB wait N
0x8093_0054 BusMstrArb Bus Master Arbitration N
0x8093_0058 BootModeClr Boot Mode Clear Register N
0x8093_0080 DeviceCfg Device configuration Y
0x8093_0084 VidClkDiv Video Clock Divider Y
0x8093_0088 MIRClkDiv MIR Clock Divider. Configures video clock for the raster engine. Y
Syscon System Control Registers
Copyright 2004 Cirrus Logic
Table 2-7: Internal Register Map (Continued)
ARM920T Core and Advanced High-Speed Bus (AHB)
OO
Address Register Name Register Description
0x8093_008C I2SClkDiv I2S Audio Clock Divider
0x8093_0090 KeyTchClkDiv Keyscan/Touch Clock Divider Y
0x8093_0094 ChipID Chip ID Register Y
0x8093_009C SysCfg System Configuration Y
0x8093_00C0 SysSWLock Syscon Software Lock Register N
0x8094_xxxx
0x8094_0000 Watchdog Watchdog Timer Register N
0x8094_0004 WDStatus Watchdog Status Register N
0x8095_0000 - 0x8FFF_FFFF Reserved
WATCHDOG Watchdog Control Register N
SW
Lock
2
EP9315 User’s Manual - DS638UM1 67 Copyright 2004 Cirrus Logic
2
ARM920T Core and Advanced High-Speed Bus (AHB)
This page intentionally blank.
Copyright 2004 Cirrus Logic

3.1 Introduction

The MaverickCrunch coprocessor accelerates IEEE-754 floating point arithmetic and 32-bit and 64-bit fixed point arithmetic operations. It provides an integer multiply-accumulate (MAC) that is considerably faster than the native MAC implementation in the ARM920T. The MaverickCrunch coprocessor significantly accelerates the arithmetic processing required to encode/decode digital audio formats.
The MaverickCrunch coprocessor uses the standard ARM920T coprocessor interface, sharing its memory interface and instruction stream. All MaverickCrunch operations are simply ARM920T coprocessor instructions. The coprocessor handles all internal inter-instruction dependencies by using internal data forwarding and inserting wait states.
PP

Chapter 3

3MaverickCrunch Coprocessor

3

3.1.1 Features

Key features include:
• IEEE-754 single and double precision floating point
• 32/64-bit integer
• Add/multiply/compare
• Integer Multiply-Accumulate (MAC) 32-bit input with 72-bit accumulate
• Integer Shifts
• Floating point to/from integer conversion
• Sixteen 64-bit registers
• Four 72-bit accumulators

3.1.2 Operational Overview

The MaverickCrunch coprocessor is a true ARM920T coprocessor. It communicates with the ARM920T via the coprocessor bus and shares the instruction stream and memory interface of the ARM920T. It runs at the ARM920T core clock frequency (either FCLK or BCLK).
The coprocessor supports four primary data formats:
EP9315 User’s Manual - DS638UM1 69 Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
• IEEE-754 single precision floating point (24-bit signed significand and 8-
• IEEE-754 double precision floating point (53-bit signed significand and
bit biased exponent)
11-bit biased exponent)
3
• 32-bit integer
• 64-bit integer
The coprocessor performs the following standard operations on all four supported data formats:
• addition
• subtraction
• multiplication
• absolute value
• negation
• logical left/right shift
• comparison
In addition, for 32-bit integers, the coprocessor provides:
• multiply-accumulate (MAC)
• multiply-subtract (MSB)
Any of the four data formats may be converted to another of the formats. All four data types may be loaded directly from and stored directly to memory via the ARM920T coprocessor interface. They may also be moved to or from ARM920T registers.
The MaverickCrunch coprocessor also provides a 72-bit extended precision integer format that is used only in the accumulators. The accumulators may also be used in MAC and MSB operations.
IEEE-754 rounding and exceptions are also provided. Four rounding modes for floating point operations are:
• round to nearest
• round toward
• round toward -∞
• round toward 0
Exceptions include:
• Invalid operator
•Overflow
+∞
Copyright 2004 Cirrus Logic
• Underflow
• Inexact
Note that the division by zero exception is not supported as the MaverickCrunch coprocessor does not provide division or square root.

3.1.3 Pipelines and Latency

There are two primary pipelines within the MaverickCrunch coprocessor. One handles all communication with the ARM920T, while the other, the “data path” pipeline, handles all arithmetic operations (this one actually operates at one half the MaverickCrunch coprocessor clock frequency).
The data path pipeline may run synchronously or asynchronously with respect to the ARM instruction pipeline. If run asynchronously, data path computation is decoupled from the ARM, allowing high throughput, though arithmetic exceptions are not synchronous. If run synchronously, exceptions are synchronous, but throughput suffers.
MaverickCrunch Coprocessor
PP
3
Assuming no inter-instruction dependencies causing pipeline stalls, arithmetic instructions can produce a new result every two ARM920T clocks which is a maximum throughput of one data path instruction per eight ARM920T clocks. The only exception is 64-bit multiplies (CFMULD or CFMUL64), which require six extra ARM920T clocks to produce their result, which is maximum throughput of eight ARM920T clocks per instruction.
The normal latency for an arithmetic instruction is approximately nine ARM920T clocks, from initial decode to the time the result is written to the register file. A 64-bit multiply requires 15 clocks.

3.1.4 Data Registers

The MaverickCrunch coprocessor contains the following registers:
• 16 64-bit general purpose registers, c0 through c15
• 4 72-bit accumulators, a0 through a3
• 1 status and control register, DSPSC
A single precision floating point value is stored in the upper 32 bits of a 64-bit register and must be explicitly promoted to double precision to be used in double precision calculations:
63 62 55 32 31 0
Sign Exponent Significand
EP9315 User’s Manual - DS638UM1 71 Copyright 2004 Cirrus Logic
not used
MaverickCrunch Coprocessor
A double precision value requires all 64 bits:
63 62 52 51 0
Sign Exponent Significand
3
A 32-bit integer is stored in the lower 32 bits of a 64-bit register and sign­extended when written, provided the UI bit in the DSPSC is clear:
63 32 31 30 0
Sign Extension Sign Data
Hence, 32-bit integers may be used directly in calculations with 64-bit integers, which are stored as shown:
63 62 0
Sign Data

3.1.5 Integer Saturation Arithmetic

By default, the coprocessor treats all 32-bit and 64-bit integers as signed values and automatically saturates the results of most integer operations and all conversions from floating-point to integer format. Instructions that may saturate their results are:
• CFADD32 and CFADD64
• CFSUB32 and CFSUB64
• CFMUL32 and CFMUL64
• CFMAC32 and CFMSC32
• CFCVTS32 and CFCVTD32
• CFTRUNCS32 and CFTRUNCD32
This behavior, however, can be altered by setting the UI bit and the ISAT bit in the DSPSC. With the UI bit clear (the default), 32-bit and 64-bit integer operations are treated as signed with respect to overflow and underflow detection and saturation as well as compare operations. Setting the UI bit causes the MaverickCrunch coprocessor to treat all 32-bit and 64-bit integer operations as unsigned with respect to overflow, underflow, saturation, and comparison.
With saturation enabled (the default), the maximum representable value is returned on overflow and the minimum representable value is returned on
Copyright 2004 Cirrus Logic
underflow. The maximum and minimum values depends on the operand size and whether the UI bit in the DSPSC is set, as shown in Table 3-1.
Table 3-1: Saturation for Non-accumulator Instructions
Signed
Overflow
Unsigned
Signed
Underflow
Unsigned
To disable saturation on overflow and underflow, set the ISAT bit in the DSPSC.
Normally, arithmetic instructions that write to an accumulator do not saturate their results on overflow or underflow. These instructions are:
• CFMADD32 and CFMSUB32
• CFMADDA32 and CFMSUBA32
MaverickCrunch Coprocessor
32-bit 0x7FFF_FFFF 64-bit 0x7FFF_FFFF_FFFF_FFFF 32-bit 0xFFFF_FFFF 64-bit 0xFFFF_FFFF_FFFF_FFFF 32-bit 0x8000_0000 64-bit 0x8000_0000_0000_0000 32-bit 0x0000_0000 64-bit 0x0000_0000_0000_0000
PP
3
However, the SAT[1:0] bits in the DSPSC may be set to select one of several kinds of saturation to occur on the results of these instructions before they are written to an accumulator.
Note: This action does not affect the operation of instructions that do not write their
result to an accumulator.
Enabling saturation also modifies the representation of data stored in the accumulator. The three supported bit formats and their maximum and minimum saturation values are shown in Table 3-2 on page 73.
Table 3-2: Accumulator Bit Formats for Saturation
Bit Format Maximum Value (hex) Minimum Value (hex)
2.62 64 bits - 0x3FFF FFFF FFFF FFFF 64 bits - 0xC000 0000 0000 0000
1.63 64 bits - 0x7FFF FFFF FFFF FFFF 64 bits - 0x8000 0000 0000 0000
1.31 32 bits - 0x7FFF FFFF 32 bits - 0x8000 0000
The bit format x.yy represents x binary bits before the decimal point and yy fraction bits after decimal point, as for example, when the bit format 2.62 has two binary bits and sixty-two fraction bits. Though these formats utilize either 32- or 64-bit integers, the accumulators are 72 bits wide. If the accumulator saturation mode is disabled (the default), the accumulator bit fields are assigned as below for a 2’s complement integer.
71 70 0
Sign Data
EP9315 User’s Manual - DS638UM1 73 Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
If the saturation mode 1.63 is selected, the bit field assignments are:
71 64 63 62 0
Sign Extension Sign Data
3
If the saturation mode 1.31 is selected, the bit field assignments are:
71 64 63 62 32 31 0
Sign Extension Sign Data Unused
If the saturation mode 2.62 is selected, the bit field assignments are:
71 63 62 61 0
Sign Extension Sign Data

3.1.6 Comparisons

The Crunch coprocessor provides four compare operations:
• CFCMP32 - 32-bit integer
• CFCMP64 - 64-bit integer
• CFCMPS - single floating point
• CFCMPD - double floating point
The DSPSC register bit UINT affects the operation of integer comparisons. If clear, integers are treated as signed values, and if set, they are treated as unsigned. DSPSC.UINT has no effect on floating point comparisons.
All compare operations update both the FCC[1:0] bits in the DSPSC register and an ARM register. Though any of the ARM general purpose registers r0 through r14 may be specified as the destination, specifying r15 actually updates the CPSR flag bits NZCV. This permits the condition code field of any subsequent ARM instruction to gate the execution of that instruction based on the result of a Crunch compare operation.
Table 3-3 on page 75 illustrates the legal relationships and, for each one, the values written to the FCC bits and the NZCV flags. The FCC bits and the NZCV flags provide the same information, but in different ways and in different places. Their values depend only on the relationship between the operands, regardless of whether the operands are considered signed integer, unsigned integer, or floating point. The unordered relationship can only apply to floating point operands.
Copyright 2004 Cirrus Logic
Table 3-3: Comparison Relationships and Their Results
Relationship FCC[1:0] NCZV
MaverickCrunch Coprocessor
PP
AB=
AB<
AB>
Unordered 11 0000
The NZCV flags are not computed exactly as with integer comparisons using the ARM CMP instruction. Hence, when examining the result of Crunch comparisons, the condition codes field of ARM instructions should be interpreted differently, as shown in Table 3-4 on page 75. The same six condition codes should be used whether the comparison operands were signed integers, unsigned integers, or floating point. No other condition codes are meaningful.
Table 3-4: ARM Condition Codes and Crunch Compare Results
Condition Code
Opcode[31:28] Mnemonic
0000 EQ Equal Equal
0001 NE Not Equal Not Equal
1010 GE Signed Greater Than or Equal Greater Than or Equal
Relationship ARM Meaning Crunch Meaning
AB=
AB≠
AB≥
00 0100
01 1000
10 1001
3
1011 LT Signed Less Than Less Than
1100 GT Signed Greater Than Greater Than
1101 LE Signed Less Than or Equal Less Than or Equal
1110 AL N/A Always (unconditional) Always (unconditional)
1111 NV N /A Never N eve r

3.2 Programming Examples

The examples below show two algorithms, each implemented using the standard programming languages and the MaverickCrunch instruction set.

3.2.1 Example 1

Sections 3.2.1.2, 3.2.1.3, and 3.2.1.4, show three coding samples performing the same operation. Section 3.2.1.1 on page 76 shows common setup code used by all three samples. Section 3.2.1.2 on page 76 shows the program implemented in C code. Section 3.2.1.3 on page 76 uses ARM assembly language, accessing the MaverickCrunch with ARM coprocessor instructions.
AB<
AB>
A B≤
EP9315 User’s Manual - DS638UM1 75 Copyright 2004 Cirrus Logic
3
MaverickCrunch Coprocessor
Section 3.2.1.4 on page 76 uses MaverickCrunch assembly language instructions.
3.2.1.1 Setup Code
ldr r0, =80930000 ; Syscon base address
mov r1, #0xaa ; SW lock key
str r1, [r0, #0xc0] ; unlock by writing key to SysSWLock register
ldr r1, [r0, #0x80] ; Turn on CPENA bit in DEVCFG register to
orr r1, r1, #0x00800000 ; enable MaverickCrunch coprocessor
str r1, [r0, #0x80] ;
3.2.1.2 C Code
int num = 0;
for(num=0; num < 10; num++)
num = num * 5;
3.2.1.3 Accessing MaverickCrunch with ARM Coprocessor Instructions
ldc p5, c0, [r0, #0x0] ; data section preloaded with 0x0 (“num”)
ldc p5, c1, [r0, #0x4] ; data section preloaded with 0xa
ldc p5, c2, [r0, #0x8] ; data section preloaded with 0x1
ldc p5, c3, [r0, #0xc] ; data section preloaded with 0x5
loop
cdp p5, 1, c0, c0, c3, 0 ; c0 <= c0 * 5
cdp p5, 3, c0, c0, c2, 6 ; c0 <= c0 - 1
mrc p5, 0, r15 c0, c1, 4 ; c0 < 10 ?
blt loop ; yes
stc p5, c0, [r0, #0x0] ; no, store result
3.2.1.4 MaverickCrunch Assembly Language Instructions
cfldr32 c0, [r0, #0x0] ; data section preloaded with 0x0 (“num”)
cfldr32 c1, [r0, #0x4] ; data section preloaded with 0xa
cfldr32 c2, [r0, #0x8] ; data section preloaded with 0x1
cfldr32 c3, [r0, #0xc] ; data section preloaded with 0x5
loop
cfmul32 c0, c0, c3 ; c0 <= c0 * 5
cfsub32 c0, c0, c2 ; c0 <= c0 - 1
cfcmp32 r15, c0, c1 ; c0 < 10 ?
blt loop ; yes
cfstr32 c0, [r0, #0x0] ; no, store result

3.2.2 Example 2

The following function performs an FIR filter on the given input stream. The variable “data” points to an array of floating point values to be filtered, “n” is the number of samples for which the filter should be applied, “filter” is the FIR filter
Copyright 2004 Cirrus Logic
3.2.2.1 C Code
MaverickCrunch Coprocessor
to be applied, and “m” is the number of taps in the FIR filter. The “data” array must be “n + m - 1” samples in length, and “n” samples will be produced.
void
ComputeFIR(float *data, int n, float *filter, int m)
{
int i, j;
float sum;
for(i = 0; i < n; i++)
{
sum = 0;
for(j = 0; j < m; j++)
{
sum += data[i + j] * filter[j];
}
PP
3
data[i] = sum;
}
}
3.2.2.2 MaverickCrunch Assembly Language Instructions
ComputeFIR
mov r1, r1, lsl #2 ; n *= 4
mov r3, r3, lsl #2 ; m *= 4
outer_loop
mov r12, r3 ; j = m * 4
cfsub64 c0, c0, c0 ; int_sum = 0;
cfcvt32s c0, c0 ; sum = float(int_sum);
inner_loop
cfldrs c2, [r0], #4 ; c2 = *data++;
cfldrs c3, [r2], #4 ; c3 = *filter++;
cfmuls c1, c2, c3 ; c1 = c2 * c3;
cfadds c0, c0, c1 ; sum += c1;
subs r12, r12, #4 ; j -= 4;
bne inner_loop ; branch if j != 0
sub r0, r3 ; data -= m * 4;
cfstrs c0, [r0], #4 ; *data++ = sum;
sub r2, r3 ; filter -= m * 4;
subs r1, r1, #4 ; n -= 4;
bne outer_loop ; branch if n != 0
mov pc, lr ; return to caller
EP9315 User’s Manual - DS638UM1 77 Copyright 2004 Cirrus Logic
3
MaverickCrunch Coprocessor

3.3 DSPSC Register

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
INST
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
INST
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAID HVID RSVD ISAT UI INT AEXC SAT[1:0] FCC[1:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V FWDEN Invalid Denorm RM[1:0] IXE UFE OFE RSVD IOE IX UF OF RSVD IO
Default:
Definition:
Bit Descriptions:
0x0000_0000_0000_0000
MaverickCrunch Status and Control Register. Accessed only via the MaverickCrunch instruction set. All bits, including status bits, are both readable and writable. This register should generally be written only using a read-modify-write sequence.
RSVD: Reserved. Unknown During Read.
INST: Exception Instruction. Whenever an unmasked exception
occurs, these 32 bits are loaded with the instruction that caused the exception. Hence, this contains the instruction that caused the most recent unmasked exception.
DAID: MaverickCrunch Architecture ID. This read-only value is
incremented for each revision of the overall MaverickCrunch coprocessor architecture. These bits are “000” for this revision.
HVID: Hardware Version ID. This read-only value is incremented
each time the hardware implementation of the architecture named by DAID[2:0] is changed, typically done in response to bugs. These bits are “000” for this version.
Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
ISAT: Integer Saturate Enable. This bit controls whether non-
accumulator integer operations, both signed and unsigned, will saturate on overflow or underflow. 0 = Saturation enabled. 1 = Saturation disabled.
PP
UI: Unsigned Integer Enable. This bit controls whether non-
accumulator integer operations treat their operands as signed or unsigned. It also determines the saturation value if the ISAT bit is clear. 0 = Signed integers. 1 = Unsigned integers.
INT: MaverickCrunch Interrupt. This bit indicates whether an
interrupt has occurred. This bit is identical to the external interrupt signal. 0 = No interrupt signaled. 1 = Interrupt signaled.
AEXC: Asynchronous Exception Enable. This bit determines
whether exceptions generated by the coprocessor are signaled synchronously or asynchronously to the ARM920T. Synchronous exceptions force all data path instructions to be serialized and to stall the ARM920T. If exceptions are asynchronous, they are signalled by assertion of the DSPINT output of the coprocessor, which may interrupt the ARM920T via the interrupt controller. Enabling asynchronous exceptions does provide a performance improvement, but makes it difficult for an interrupt handler to determine the coprocessor instruction that caused the exception because the address of the instruction is not preserved. Exceptions may be individually enabled by other bits in this register (IXE, UFE, OFE, and IOE). This bit has no effect if no exceptions are enabled. 0 = Exceptions are synchronous. 1 = Exceptions are asynchronous
3
SAT[1:0]: Accumulator saturation mode select. These bits are set to
select the saturation mode or to disable the saturation for accumulator operations. 0X = Saturation disabled for accumulator operations 10 = Accumulator saturation enabled, bit formats 1.63 and
1.31 11 = Accumulator saturation enabled, bit format 2.62
EP9315 User’s Manual - DS638UM1 79 Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
FCC[1:0]: FCC flags out of comparator.
00 = Operand A equals operand B. 01 = Operand A less than operand B. 10 = Operand A greater than operand B. 11 = Operands are unordered (at least one is NaN).
3
V: Overflow Flag. Indicates the overflow status of the
previous integer operation. 0 = No overflow. 1 = Overflow.
FWDEN: Forwarding Enable. This bit determines whether data path
writeback results are forwarded to the data path operand fetch stage and to the STC/MRC execute stage. When pipeline interlocks occur due to dependencies of data path, STC, and MRC instruction source operands on data path results, setting this bit will improve instruction throughput. 0 = Forwarding not enabled. 1 = Forwarding enabled.
Invalid: 0 = No invalid operations detected
1 = An invalid operation was performed.
Denorm: 0 = No denormalized numbers have been supplied as
instruction operands 1 = a denormalized number has been supplied as an instruction operand.
RM[1:0]: Rounding Mode. Selects IEEE 754 rounding mode.
0 0 = Round to nearest. 0 1 = Round toward 0. 1 0 = Round to 1 1 = Round to
-∞. +∞.
IXE: Inexact Trap Enable. Enables/disables software trapping
for IEEE 754 inexact exceptions. 0 = Disable software trapping for inexact exceptions. 1 = Enable software trapping for inexact exceptions.
UFE: Underflow Trap Enable. Enables/disables software
trapping for IEEE 754 underflow exceptions. 0 = Disable software trapping for underflow exceptions. 1 = Enable software trapping for underflow exceptions.
OFE: Overflow Trap Enable. Enables/disables software trapping
for IEEE 754 overflow exceptions. 0 = Disable software trapping for overflow exceptions. 1 = Enable software trapping for overflow exceptions.
Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
IOE: Invalid Operator Trap Enable. Enables/disables software
trapping for IEEE 754 invalid operator exceptions. 0 = Disable software trapping for invalid operator exceptions. 1 = Enable software trapping for invalid operator exceptions.
IX: Inexact. Set when an IEEE 754 inexact exception occurs,
regardless of whether or not software trapping for inexact exceptions is enabled. Writing a “0” to this position clears the status bit. 0 = No inexact exception detected. 1 = Inexact exception detected.
UF: Underflow. Set when an IEEE 754 underflow exception
occurs, regardless of whether or not software trapping for underflow exceptions is enabled. Writing a “0” to this position clears the status bit. 0 = No underflow exception detected. 1 = Underflow exception detected.
PP
3
OF: Overflow. Set when an IEEE 754 overflow exception
occurs, regardless of whether or not software trapping for overflow exceptions is enabled. Writing a “0” to this position clears the status bit. 0 = No overflow exception detected. 1 = Overflow exception detected.
IO: Invalid Operator. Set when an IEEE 754 invalid operator
exception occurs, regardless of whether or not software trapping for invalid operator exceptions is enabled. Writing a “0” to this position clears the status bit. 0 = No invalid operator exception detected. 1 = Invalid operator exception detected.

3.4 ARM Coprocessor Instruction Format

The ARM V4T architecture defines five ARM coprocessor instructions:
• CDP - Coprocessor Data Processing
• LDC - Load Coprocessor
• STC - Store Coprocessor
• MCR - Move to Coprocessor Register from ARM Register
• MRC - Move to ARM Register from Coprocessor Register
The coprocessor instruction assembler notation is found in the ARM programming manuals or the Quick Reference Card. (For additional
EP9315 User’s Manual - DS638UM1 81 Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
information, see “Reference Documents”, item 4, on page 5.) Formats for the above instructions and variants of these instructions are detailed below.
CDP (Coprocessor Data Processing) Instruction Format
31 28 27 24 23 20 19 16 15 12 11 8 7 5 4 3 0
3
cond 1110 opcode1 CRn CRd cp num opcode2 0 CRm
LDC (Load Coprocessor) Instruction Format
31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 0
cond 110 P U N W 1 Rn CRd cp num offset
STC (Store Coprocessor) Instruction Format
31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 0
cond 110 P U N W 0 Rn CRd cp num offset
MCR (Move to Coprocessor from ARM Register) Instruction Format
31 28 27 24 23 21 20 19 16 15 12 11 8 7 5 4 3 0
cond 1110 opcode1 0 CRn Rd cp num opcode2 1 CRm
MRC (Move to ARM Register from Coprocessor) Instruction Format
31 28 27 24 23 21 20 19 16 15 12 11 8 7 5 4 3 0
cond 1110 opcode1 1 CRn Rd cp num opcode2 1 CRm
Copyright 2004 Cirrus Logic
Table 3-5 shows the condition codes, which are bits [31:28] for each instruction format.
Table 3-5: Condition Code Definitions
MaverickCrunch Coprocessor
PP
Cond
[31:28]
0000 EQ Equal Z set
0001 NE Not Equal Z clear
0010 CS /HS Carry Set/Unsigned H igher or Same C set
0011 CC/LO Carry Clear/Unsigned Lower C clear
0100 MI Minus/Negative N set
0101 PL Plus/Positive or Zero N clear
0110 VS Overflow V set
0111 VC No Overflow V clear
1000 HI Unsigned Higher C set and Z clear
1001 LS Unsigned Lower or Same C clear or Z set
1010 GE Signed Greater Than or Equal N set and V set, or N clear and V clear (N = V)
1011 LT Signed Less Than N set and V clear, or N clear and V set (N ! = V)
1100 GT Signed Greater Than Z clear, and either N set and V set, or N clear and V clear (Z = 0, N = V)
1101 LE Signed Less Than or Equal Z set, or N set and V clear, or N clear and V set (Z = 1, N ! = V)
1110 AL Always (unconditional) -
Mnemonic
Extension
1111 NV Never -
Meaning Status Flag State
3
The remaining bits in the instruction formats are interpreted as follows:
• opcode1: MaverickCrunch coprocessor-defined opcode.
• opcode2: MaverickCrunch coprocessor-defined opcode.
• CRn: MaverickCrunch coprocessor-defined register ID.
• CRd: MaverickCrunch coprocessor-defined register ID.
• CRm: MaverickCrunch coprocessor-defined register ID.
• Rn: Specifies an ARM base address register. These bits are ignored by the MaverickCrunch coprocessor.
• Rd: Specifies a source or destination ARM register.
• cp_num: Coprocessor number.
• P: Pre-indexing (P=1) or post-indexing (P=0) addressing. This bit is ignored by the MaverickCrunch coprocessor.
• U: Specifies whether the supplied 8-bit offset is added to a base register
EP9315 User’s Manual - DS638UM1 83 Copyright 2004 Cirrus Logic
3
MaverickCrunch Coprocessor
(U=1) or subtracted from a base register (U=0). This bit is ignored by the MaverickCrunch coprocessor.
• N: Specifies the width of a data type involved in a move operation. The MaverickCrunch coprocessor uses this bit to distinguish between single precision floating point/32-bit integer numbers (N=0) and double precision floating point/64-bit integer numbers (N=1).
• W: Specifies whether or not a calculated address is written back to a base register (W=1) or not (W=0). This bit is ignored by the MaverickCrunch coprocessor.
• offset: An 8-bit word offset used in address calculations. These bits are ignored by the MaverickCrunch coprocessor.
Table 3-6, below, and Table 3-7, Table 3-8, and Table 3-9 on page 85, define the bit values for opcode2, opcode1, and cp_num for all of the MaverickCrunch instructions.
Table 3-6: LDC/STC Opcode Map
cp num [3:0] Opcode Bits 22 and 20
00 01 10 11
0100 0101
cfstrs
cfstr32
cfldrs
cfldr32
cfstrd
cfstr64
cfldrd
cfldr64
Copyright 2004 Cirrus Logic
Table 3-7: CDP Opcode Map
MaverickCrunch Coprocessor
PP
op
code
[1:0]
00
01
10
11
Table 3-8: MCR Opcode Map
cp
num
1
[3:0]
000 001 010 011 100 101 110 111
0100 cfcpys cfcpyd cfcvtds cfcvtsd cfcvt32s cfcvt32d cfcvt64s cfcvt64d
0101 cfsh32
0110 cfmadd32
0100 cfmuls cfmuld cfmv32al cfmv32am cfmv32ah cfmv32a cfmv64a cfmv32sc
0101 cfmul32 cfmul64 cfmac32 cfmsc32 cfcvts32 cfcvtd32 cftruncs32 cftruncd32
0110 cfmsub32
0100 cfmval32 cfmvam32 cfmvah32 cfmva32 cfmva64 cfmvsc32
0101 cfsh64
0110 cfmadda32
0100 cfabss cfabsd cfnegs cfnegd cfadds cfaddd cfsubs cfsubd
0101 cfabs32 cfabs64 cfneg32 cfneg64 cfadd32 cfadd64 cfsub32 cfsub64
0110 cfmsuba32
opcode2[2:0]
3
op
code1cpnum
[3:0]
000 001 010 011 100 101 110 111
0100
0
0101 0110
Table 3-9: MRC Opcode Map
op
code1cpnum
[3:0]
0100
0
0101 0110
cfmvdlr
cfmv64lr
000 001 010 011 100 101 110 111
cfmvrdl
cfmvr64l
cfmvdhr
cfmv64hr
cfmvrdh
cfmvr64h
opcode2[2:0]
cfmvsr
cfrshl32 cfrshl64
opcode2[2:0]
cfmvrs cfcmps
cfcmp32
cfcmpd
cfcmp64
EP9315 User’s Manual - DS638UM1 85 Copyright 2004 Cirrus Logic
3
MaverickCrunch Coprocessor

3.5 Instruction Set for the MaverickCrunch Coprocessor

Table 3-10 summarizes the MaverickCrunch coprocessor instruction set. Please note that:
• CRd, CRn, and CRm each refer to any 16 general purpose MaverickCrunch registers unless otherwise specified
• CRa refers to any of the MaverickCrunch accumulators
• Rd and Rn refer to any of the ARM920T general purpose registers
• <imm> refers to a seven-bit immediate value
The remainder of this section describes in detail each of the individual MaverickCrunch instructions. The fields in the opcode for each MaverickCrunch instruction are shown. When specific bit values are required for the instruction, they are shown as either '1' or '0'. Any field whose value may vary, such as a register index, is named as in the ARM programming manuals, and its function described below.
Fields that are ignored by the coprocessor are shaded. Dark shading implies that a field is processed by the ARM itself and can have any value, while light shading indicates that the field, though ignored by both the ARM and the coprocessor, should have the value shown.
Table 3-10: MaverickCrunch Instruction Set
Maverick
Crunch
Coprocessor
Instruction
Type
Loads LDC
Stores STC
Moves to
coprocessor
ARM
Coprocessor
Instruction
Typ e
MCR
Instruction Description
cfldrs CRd, [Rn] Load CRd with single stored at address in Rn
cfldrd CRd, [Rn] Load CRd with double stored at address in Rn
cfldr32 CRd, [Rn]
cfldr64 CRd, [Rn] Load CRd with 64-bit integer stored at address in Rn
cfstrs CRd, [Rn] Store single in CRd at address in Rn
cfstrd CRd, [Rn] Store double in CRd at address in Rn
cflstr32 CRd, [Rn] Store 32-bit integer in CRd at address in Rn
cfstr64 CRd, [Rn] Store 64-bit integer in CRd at address in Rn
cfmvsr CRn, Rd Move single from Rd to CRn[63:32]
cfmvdlr CRn, Rd Move lower half of double from Rd to CRn[31:0]
cfmvdhr CRn, Rd Move upper half of double from Rd to CRn[63:32]
cfmv64lr CRn, Rd
cfmv64hr CRn, Rd Move upper half of 64-bit integer from Rd to CRn[63:32]
Load CRd with 32-bit integer stored at address in Rn, sign extend through bit 63
Move lower half of 64-bit integer from Rd to CRn[31:0], sign extend bit 31 through bits [63:31]
Copyright 2004 Cirrus Logic
Table 3-10: MaverickCrunch Instruction Set (Continued)
MaverickCrunch Coprocessor
PP
Maverick
Crunch
Coprocessor
Instruction
Type
Moves from
coprocessor
Moves to accumulator
Moves from accumulator
Move to DSPSC
Move from DSPSC
ARM
Coprocessor
Instruction
Typ e
MRC
CDP
CDP
CDP
Instruction Description
cfmvsr Rd, CRn Move single from CRn[63:32] to Rd
cfmvrdl Rd, CRn Move lower half of double from CRn[31:0] to Rd
cfmvrdh Rd, CRn Move upper half of double from CRn[63:32] to Rd
cfmvr64l Rd, CRn Move lower half of 64-bit integer from CRn[31:0] to Rd
cfmvr64h Rd, CRn Move upper half of 64-bit integer from CRn[63:32] to Rd
cfmval32 CRd, CRn Move 32-bit integer from CRn [31:0] to accumulator CRd[31:0]
cfmvam32 CRd, CRn Move 32-bit integer from CRn [31:0] to accumulator CRd[63:32]
cfmvah32 CRd, CRn
cfmva32 CRd, CRn
cfmva64 CRd, CRn
cfmv32al CRd, CRn Move accumulator CRn[31:0] to 32-bit integer CRd[31:0]
cfmv32am CRd, CRn Move accumulator CRn[63:32] to 32-bit integer CRd[31:0]
cfmv32ah CRd, CRn Move accumulator CRn[71:64] to lower 8 bits of 32-bit integer CRd[31:0]
cfmv32a CRd, CRn
cfmv64a CRd, CRn
cfmvsc32 CRd, CRn Move CRd to DSPSC; CRn is ignored
cfmv32sc CRd, CRn Moves DSPSC to CRd; CRn is ignored
Move lower 8 bits of 32-bit integer from CRn [7:0] to accumulator CRd[71:64]
Move 32-bit integer from CRn[31:0] to accumulator CRd[31:0] and sign extend through bit 71
Move 64-bit integer from CRn to accumulator CRd[63:0] and sign extend through bit 71
Saturate to 32-bit integer and move accumulator CRn[31:0] to 32-bit integer CRd[31:0]
Saturate to 64-bit integer and move accumulator CRn[63:0] to 64-bit integer CRd
3
EP9315 User’s Manual - DS638UM1 87 Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
Table 3-10: MaverickCrunch Instruction Set (Continued)
3
Maverick
Crunch
Coprocessor
Instruction
Type
Conversions and copies
Shifts
Comparisons MRC
Floating point arithmetic, single precision
ARM
Coprocessor
Instruction
Typ e
CDP
MCR
CDP
CDP
Instruction Description
cfcpys CRd, CRn Copy a single from CRn to CRd
cfcpyd CRd, CRn Copy a double from CRn to CRd
cfcvtsd CRd, CRn Convert a single in CRn to a double in CRd
cfcvtds CRd, CRn Convert a double in CRn to a single in CRd
cfcvt32s CRd, CRn Convert a 32-bit integer in CRn to a single in CRd
cfcvt32d CRd, CRn Convert a 32-bit integer in CRn to a double in CRd
cfcvt64s CRd, CRn Convert a 64-bit integer in CRn to a single in CRd
cfcvt64d CRd, CRn Convert a 64-bit integer in CRn to a double in CRd
cfcvts32 CRd, CRn Convert a single in CRn to a 32-bit integer in CRd
cfcvtd32 CRd, CRn Convert a double in CRn to a 32-bit integer in CRd
cftruncs32 CRd, CRn Truncate a single in CRn to a 32-bit integer in CRd
cftruncd32 CRd, CRn Truncate a double in CRn to a 32-bit integer in CRd
cfrshl32 CRm, CRn, RdShift 32-bit integer in CRn by two’s complement value in Rd and store in
cfrshl64 CRm, CRn, RdShift 64-bit integer in CRn by two’s complement value in Rd and store in
cfsh32 CRd, CRn, <imm>
cfsh64 CRd, CRn, <imm>
cfcmps Rd, CRn, CRm Compare singles in CRn to CRm, result in Rd, or CPSR if Rd == R15
cfcmpd Rd, CRn, CRm Compare doubles in CRn to CRm, result in Rd, or CPSR if Rd == R15
cfcmp32 Rd, CRn, CRm
cfcmp64 Rd, CRn, CRm
cfabss CRd, CRn CRd gets absolute value of CRn
cfnegs CRd, CRn CRd gets negation of CRn
cfadds CRd, CRn, CRm
cfsubs CRd, CRn, CRm
cfmuls CRd, CRn, CRm
CRm
CRm
Shift 32-bit integer in CRn by <imm> bits and store in CRd, where <imm> is between -32 and 31, inclusive
Shift 64-bit integer in CRn by <imm> bits and store in CRd, where <imm> is between -32 and 31, inclusive
Compare 32-bit integers in CRn to CRm, result in Rd, or CPSR if Rd == R15
Compare 64-bit integers in CRn to CRm, result in Rd, or CPSR if Rd == R15
CRd gets sum of CRn and CRm
CRd gets CRn minus CRm
CRd gets the product of CRn and CRm
Copyright 2004 Cirrus Logic
Table 3-10: MaverickCrunch Instruction Set (Continued)
MaverickCrunch Coprocessor
PP
Maverick
Crunch
Coprocessor
Instruction
Type
Floating point arithmetic, double precision
32-bit integer arithmetic
64-bit integer arithmetic
Accumulator arithmetic
ARM
Coprocessor
Instruction
Typ e
CDP
CDP
CDP
CDP
Instruction Description
cfabsd CRd, CRn CRd gets absolute value of CRn
cfnegd CRd, CRn CRd gets negation of CRn
cfaddd CRd, CRn, CRm
cfsubd CRd, CRn, CRm
cfmuld CRd, CRn, CRm
cfabs32 CRd, CRn CRd gets absolute value of CRn
cfneg32 CRd, CRn CRd gets negation of CRn
cfadd32 CRd, CRn, CRm
cfsub32 CRd, CRn, CRm
cfmul32 CRd, CRn, CRm
cfmac32 CRd, CRn, CRm
cfmsc32 CRD, CRn, CRm
cfabs64 CRd, CRn CRd gets absolute value of CRn
cfneg64 CRd, CRn CRd gets negation of CRn
cfadd64 CRd, CRn, CRm
cfsub64 CRd, CRn, CRm
cfmul64 CRd, CRn, CRm
cfmadd32 CRa, CRd, CRn, CRm
cfmsub32 CRa, CRd, CRn, CRm
cfmadda32 CRa, CRd, CRn, CRm
cfmsuba32 CRa, CRd, CRn, CRm
CRd gets sum of CRn and CRm
CRd gets CRn minus CRm
CRd gets the product of CRn and CRm
CRd gets sum of CRn and CRm
CRd gets CRn minus CRm
CRd gets the product of CRn and CRm
CRd gets sum of CRd and the product of CRn and CRm
CRd gets CRd minus the product of CRn and CRm
CRd gets sum of CRn and CRm
CRd gets CRn minus CRm
CRd gets the product of CRn and CRm
Accumulator CRa gets sum of CRd and the product of CRn and CRm
Accumulator CRa gets CRd minus the product of CRn and CRm
Accumulator CRa gets sum of accumulator CRd and the product of CRn and CRm
Accumulator CRa gets accumulator CRd minus the product of CRn and CRm
3
EP9315 User’s Manual - DS638UM1 89 Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor

3.5.1 Load and Store Instructions

Loading Floating Point Value from Memory
31:28 27:25 24 23 22 21 20 19:16 15:12 11:8 7:0
cond 1 1 0 P UNW1 Rn CRd 0 1 0 0 8_bit_word_offset
3
Description:
Loads a single or double precision floating point value from memory into MaverickCrunch register.
Table 3-11: Mnemonic Codes
Mnemonic Addressing Mode N
CFLDRS <cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed 0
CFLDRS<cond> CRd, [Rn], <offset> Immediate post-indexed 0
CFLDRD<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed 1
CFLDRD<cond> CRd, [Rn], <offset> Immediate post-indexed 1
Bit Definitions:
N: Floating point precision - 0 for single, 1 for double.
Rn: Base register in ARM
CRd: Destination register.
Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
Loading Integer Value from Memory
31:28 27:25 24 23 22 21 20 19:16 15:12 11:8 7:0
cond 1 1 0 P UNW1 Rn CRd 0 1 0 1 8_bit_word_offset
Description:
Loads a 32- or 64-bit integer from memory into a MaverickCrunch register.
Table 3-12: Mnemonic Codes
Mnemonic Addressing Mode N
CFLDR32<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed 0
CFLDR32<cond> CRd, [Rn], <offset> Immediate post-indexed 0
CFLDR64<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed 1
CFLDR64<cond> CRd, [Rn], <offset> Immediate post-indexed 1
Bit Definitions:
PP
3
N: Integer width - 0 for 32-bit integer, 1 for 64-bit integer
Rn: Base register in ARM
CRd: Destination register.
EP9315 User’s Manual - DS638UM1 91 Copyright 2004 Cirrus Logic
3
MaverickCrunch Coprocessor
Store Floating Point Values to Memory
31:28 27:25 24 23 22 21 20 19:16 15:12 11:8 7:0
cond 1 1 0 P UNW0 Rn CRd 0 1 0 0 8_bit_word_offset
Description:
Stores a single or double precision floating point value from a MaverickCrunch register into memory.
Mnemonic:
Mnemonic Addressing Mode N
CFSTRS<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed 0
CFSTRS <cond> CRd, [Rn], <offset> Immediate post-indexed 0
CFSTRD<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed 1
CFSTRD<cond> CRd, [Rn], <offset> Immediate post-indexed 1
Bit Definitions:
N: Floating point precision - 0 for single, 1 for double.
Rn: Base register in ARM
CRd: Source register.
Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
Store Integer Values to Memory
31:28 27:25 24 23 22 21 20 19:16 15:12 11:8 7:0
cond 1 1 0 P UNW0 Rn CRd 0 1 0 1 8_bit_word_offset
Description:
Stores a 32- or 64-bit integer value from a MaverickCrunch register into memory.
Mnemonic:
Mnemonic Addressing Mode N
CFSTR32<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed 0
CFSTR32<cond> CRd, [Rn], <offset> Immediate post-indexed 0
CFSTR64<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed 1
CFSTR64<cond> CRd, [Rn], <offset> Immediate post-indexed 1
Bit Definitions:
PP
3
N: Integer width - 0 for 32-bit integer, 1 for 64-bit integer
Rn: Base register in ARM
CRd: Source register.
EP9315 User’s Manual - DS638UM1 93 Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor

3.5.2 Move Instructions

Move Single Precision Floating Point from ARM to MaverickCrunch
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 0 CRn Rd 0 1 0 0 0 1 0 1 CRm
3
Description:
Moves a single precision floating point number from an ARM register into the upper half of a MaverickCrunch register.
Mnemonic:
CFMVSR<cond> CRn, Rd
Bit Definitions:
Rd: Source ARM register
CRn: Destination register
Move Single Precision Floating Point from MaverickCrunch to ARM
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn Rd 0 1 0 0 0 1 0 1 CRm
Description:
Moves a single precision floating point number from the upper half of a MaverickCrunch register to an ARM register.
Mnemonic:
CFMVRS<cond> Rd, CRn
Bit Definitions:
Rd: Destination ARM register
CRn: Source register
Move Lower Half Double Precision Float from ARM to MaverickCrunch
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 0 CRn Rd 0 1 0 0 0 0 0 1 CRm
Description:
Moves the lower half of a double precision floating point value from an ARM register into the lower half of a MaverickCrunch register.
Mnemonic:
CFMVDLR<cond> CRn, Rd
Bit Definitions:
CRn: Destination register
Rd: Source ARM register
Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
Move Lower Half Double Precision Float from MaverickCrunch to ARM
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn Rd 0 1 0 0 0 0 0 1 CRm
Description:
Moves the lower half of a double precision floating point value stored in a MaverickCrunch register into an ARM register.
Mnemonic:
CFMVRDL<cond> Rd, CRn
Bit Definitions:
Rd: Destination ARM register
CRn: Source register
Move Upper Half Double Precision Float from ARM to MaverickCrunch
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 0 CRn Rd 0 1 0 0 0 0 1 1 CRm
PP
3
Description:
Moves the upper half of a double precision floating point value from an ARM register into the upper half of a MaverickCrunch register.
Mnemonic:
CFMVDHR<cond> CRn, Rd
Bit Definitions:
CRn: Destination register
Rd: Source ARM register
Move Upper Half Double Precision Float from MaverickCrunch to ARM
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn Rd 0 1 0 0 0 0 1 1 CRm
Description:
Moves the upper half of a double precision floating point value stored in a MaverickCrunch register into an ARM register.
Mnemonic:
CFMVRDH<cond> Rd, CRn
Bit Definitions:
Rd: Destination ARM register
CRn: Source register
EP9315 User’s Manual - DS638UM1 95 Copyright 2004 Cirrus Logic
3
MaverickCrunch Coprocessor
Move Lower Half 64-bit Integer from ARM to MaverickCrunch
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 0 CRn Rd 0 1 0 1 0 0 0 1 CRm
Description:
Moves the lower half of a 64-bit integer from an ARM register into the lower half of a MaverickCrunch register and sign extend it.
Mnemonic:
CFMV64LR<cond> CRn, Rd
Bit Definitions:
CRn: Destination register
Rd: Source ARM register
Move Lower Half 64-bit Integer from MaverickCrunch to ARM
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn Rd 0 1 0 1 0 0 0 1 CRm
Description:
Moves the lower half of a 64-bit integer stored in a MaverickCrunch register into an ARM register.
Mnemonic:
CFMVR64L<cond> Rd, CRn
Bit Definitions:
Rd: Destination ARM register
CRn: Source register
Move Upper Half 64-bit Integer from ARM to MaverickCrunch
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 0 CRn Rd 0 1 0 1 0 0 1 1 CRm
Description:
Moves the upper half of a 64-bit integer from an ARM register into the upper half of a MaverickCrunch register.
Mnemonic:
CFMV64HR<cond> CRn, Rd
Bit Definitions:
CRn: Destination register
Rd: Source ARM register
Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
Move Upper Half 64-bit Integer from MaverickCrunch to ARM
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn Rd 0 1 0 1 0 0 1 1 CRm
Description:
Moves the upper half of a 64-bit integer stored in a MaverickCrunch register into an ARM register.
Mnemonic:
CFMVR64H<cond> Rd, CRn
Bit Definitions:
Rd: Destination ARM register
CRn: Source register
PP
3
EP9315 User’s Manual - DS638UM1 97 Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor

3.5.3 Accumulator and DSPSC Move Instructions

Move MaverickCrunch Register to Lower Accumulator
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 1 0 CRn CRd 0 1 0 0 0 1 0 0 CRm
3
Description:
Moves the low 32 bits of a MaverickCrunch register to the lowest 32 bits of an accumulator (31:0).
Mnemonic:
CFMVAL32<cond> CRd, CRn
Bit Definitions:
CRd: Destination accumulator
CRn: Source register
Move Lower Accumulator to MaverickCrunch Register
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn CRd 0 1 0 0 0 1 0 0 CRm
Description:
Moves the lowest 32 bits of an accumulator (31:0) to the low 32 bits of a MaverickCrunch register.
Mnemonic:
CFMV32AL<cond> CRd, CRn
Bit Definitions:
CRd: Destination register
CRn: Source accumulator
Move MaverickCrunch Register to Middle Accumulator
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 1 0 CRn CRd 0 1 0 0 0 1 1 0 CRm
Description:
Moves the low 32 bits of a MaverickCrunch register to the middle 32 bits of an accumulator (63:32).
Mnemonic:
CFMVAM32<cond> CRd, CRn
Bit Definitions:
CRd: Destination accumulator
CRn: Source register
Copyright 2004 Cirrus Logic
MaverickCrunch Coprocessor
Move Middle Accumulator to MaverickCrunch Register
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn CRd 0 1 0 0 0 1 1 0 CRm
Description:
Moves the middle 32 bits of an accumulator (63:32) to the low 32 bits of a MaverickCrunch register.
Mnemonic:
CFMV32AM<cond> CRd, CRn
Bit Definitions:
CRd: Destination register
CRn: Source accumulator
Move MaverickCrunch Register to High Accumulator
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 1 0 CRn CRd 0 1 0 0 1 0 0 0 CRm
PP
3
Description:
Moves the lowest 8 bits (7:0) of a MaverickCrunch register to the highest 8 bits of an accumulator (71:64).
Mnemonic:
CFMVAH32<cond> CRd, CRn
Bit Definitions:
CRd: Destination accumulator
CRn: Source register
Move High Accumulator to MaverickCrunch Register
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn CRd 0 1 0 0 1 0 0 0 CRm
Description:
Moves the highest 8 bits of an accumulator (71:64) to the lowest 8 bits of a MaverickCrunch register (7:0).
Mnemonic:
CFMV32AH<cond> CRd, CRn
Bit Definitions:
CRd: Destination register
CRn: Source accumulator
EP9315 User’s Manual - DS638UM1 99 Copyright 2004 Cirrus Logic
3
MaverickCrunch Coprocessor
Move 32-bit Integer from Accumulator
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn CRd 0 1 0 0 1 0 1 0 CRm
Description:
Saturates and rounds an accumulator value to 32 bits and moves the result to the low 32 bits of a MaverickCrunch register.
Mnemonic:
CFMV32A<cond> CRd, CRn
Bit Definitions:
CRd: Destination register
CRn: Source accumulator
Move 32-bit Integer to Accumulator
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 1 0 CRn CRd 0 1 0 0 1 0 1 0 CRm
Description:
Moves a 32-bit value from a MaverickCrunch register to an accumulator and sign extend to 72 bits.
Mnemonic:
CFMVA32<cond> CRd, CRn
Bit Definitions:
CRd: Destination accumulator
CRn: Source register
Move 64-bit Integer from Accumulator
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn CRd 0 1 0 0 1 1 0 0 CRm
Description:
Saturates and rounds an accumulator value to 64 bits and moves the result to a MaverickCrunch register.
Mnemonic:
CFMV64A<cond> CRd, CRn
Bit Definitions:
CRd: Destination register
CRn: Source accumulator
Copyright 2004 Cirrus Logic
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