Cirrus Logic EP9312 User's Guide

EP9312 User’s Guide

http://www.cirrus.com

FEB ‘04

DS515UM2

s s

Revision Date Changes

1 23 September 2001 Initial Release 2 2 February 2004

Update d ChipID and S y sCfg regist er in for m a tion. Added ExtensionID information to the Security section.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com

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2 EP9312 User’s Manual - DS515UM2

About the EP9312 User’s Guide

This Gui de describes the archit ecture, ha rdware, and operation of the Cirru s Logic EP9312. It is intended to be used in conjunction with the EP9312 Datasheet, which contains the full electrical specifications for the device.

How to Use this Guide

Subject Matter Location

AC’97 Chapter 21 - AC’97 Controlle r

ARM920T Processor

Boot ROM, Hardware and Software Chapter 4- Boot ROM Booting From SROM or SyncFlash Chapter 12 - SDRAM, SyncR O M, and SyncFLASH Contro ller

Buses - AMBA, AHB, APB

Coprocessor Unit Chapter 3 - MaverickCrunch Coprocessor DMA Controller Chapter 9 - DMA Controller

EP9312 Block Diagram

Ethernet Chapter 8 - 1/10/100 Mbps Ethernet LAN Controller GPIO Chapter 27 - GPIO Interface

HDLC

S IDE Chapter 26 - IDE Interface Infra- Red Int erface Chapter 16 - IrDA Interr upt Regi sters Chapter 6- Vectored Interrupt Controller Interr upts Chapter 6- Vectored Interrupt Controll er IrDA Chapter 16 - IrDA Key Pad Matrix Chapter 25 - Keypad Interface

LCD Interface

MAC Chapter 8- 1/10/100 Mbp s Ethernet LAN Co ntroller Memory Map Chapter 1 - Introduction

Chapter 2 - ARM920T Core and Advanced High-Speed Bus (AHB)

Chapter 13 - UART1 With HDLC and Modem Control Signals Chapter 15 - UART3 With HDLC Encoder

Chapter 20 - I2S Controller

Chapter 7 - Raster Engine With Analog/LCD Integrated Timing and Interface

Preface

Subject Matter Location

Modem Chapter 13 - UART1 With HDLC and Modem Control Signals Power Management Chapter 5- System Controller Programming Clocks Chapter 5- System Controller PWM Chapter 23 - Pulse Width Modulator

Raster Graphics

Real Time Clock Chapter 19 - Real Time Clock With Software T rim Register List Chapter 1 - Introduction RTC Chapter 19 - Real Time Clock With Software T rim SDRAM Chapter 12 - SDRAM, Syn c ROM, and SyncFLASH Controller Security Chapter 28 - Security SMC Chapter 11- Static Memory Controll er SSP Chapter 22 - Synchronous Serial Port Static Memory Controller Chapter 11 - Static Memory Controller System Co nfiguration Chapter 5- Syst em Controller System Registers Chapter 5- Syst em Controller Timers Chapter 17 - Timers Touc h Screen Chapter 24 - Analog Touch Screen Interface

UART

USB Chapter 10 - Universal Serial Bus Host Controller Vectored Interrupt Registers Chapter 6- Vectored Interrupt Controller Vectored Interrupts Chapter 6 - Vectored Interrupt Controller Watchdog Timer Chapter 18 - Watchdog Timer

Chapter 7 - Raster Engine With Analog/LCD Integrated Timing and Interface

Chapter 13 - UART1 With HDLC and Modem Control Signals Chapter 14 - UART2 Chapter 15 - UART3 With HDLC Encoder

Reference Document s

1. ARM920T Technic al R eference M anual

2. AMBA Specification (Rev. 2.0), ARM IHI 001 1A, ARM Limited.

3. AHB Example AMBA System (Addendum 01), ARM DDI 0170A, ARM Limited.

4 EP9312 User’s Manual - DS515UM2

4. The coprocess or instruction assembler notation can be referenc ed from ARM programming manuals or the Quick Reference Card, document number AR M QRC 0001D .

5. The MAC engine is compliant with the requirements of ISO/IEC 8802-3 (1993), Sections 3 an d 4.

6. OpenHCI - Open Host Controller interface Specification for USB, Release

1.0a; Com paq, Microsoft, National Sem iconduct or.

7. ARM Coproces sor Quick Ref erence Card, document number ARM QRC 0001D.

8. Information Technology, AT Attachment with Packet Interface - 5 (ATA/ATAPI-5) ANSI NCITS document T13 1321D, Revision 3, 29 February 2000

9. OpenHCI - Open Host Controller Interface Specification for USB, Release : 1 .0 a, R eleased - 09 /1 4/ 99 2:33 PM

10. ARM PrimeCell PL190-Rel1v1 Revision 1.7 Technical Reference Manual DDI0181C

11. Audio Codec ‘97, Revision 2.3, April 2002, Intel Corporation

Notational Conventions

This docum ent uses the following convent ions:

• Internal and e xternal Sig nal Nam es, and P in Name s use mixe d uppe r and lower case alphanumeric, and are sho w n in bold fo nt: RDLED .

• Register Bit Fie lds are named u sing upper and lo wer case alphan umeric: that is, SBO OT, LC Sn1.

• Registers are named using mixed upper and lower case alphanumeric: that is, SysCfg or PxDDR. (Where there are multiple registers with similar names, a lower case “x” is used as a place holder. For example, in the PxDDR registers, x represents a letter between A and H, indicating the specific port being discussed.)

Caution: In the Internal Register Map in Table 2-7 on page 7-51, some

memory locations are listed as Reserved. These memory locations should not be used. Reading from these memory locatio ns will yield inva lid data. Writing to these mem ory location s may caus e unpredictable results.

(An exam ple reg ister descript ion is sh own b elow. This de scriptio n is use d for the following examples.)

A specific bit m ay be specified in one of two way s :

By register name[bit number] : SysCfg[29],

or by register name.bit f ield[bit num ber] : SysCfg.REV[1] Both of thes e represen tations refer to th e s am e bit. The following:

SysCfg[8], or

SysCfg.SBOOT

also refer to the same bit. Hexi decimal number s are referred to as 0x0000_0000. Binary num bers are re fe rred to as 0000_0000b.

Note: This is only and example. For actual SysCfg register information, see “SysCfg”

on page 160.

SysCfg

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

REV RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD SBOOT LCSn7 LCSn6 LASDO LEEDA LEECLK RSVD LCSn2 LCSn1

Address:

0x8093_009C - Read/Write, Softw are locked

Default:

0x0000_0000

Definition:

System Configuration Register. Provides various system configuration options.

Bit Descriptions:

RSVD: Reserved. Unknown During Read. REV: Revision, reads chip Version number: 0 - Rev A, 1 - Rev B,

2 - Rev C, 3 - Rev D.

SBOOT: Serial Bo ot Fl ag. T his bit is read -only.

1 hardware dete c te d Serial Boot se lection, 0 hardware dete c te d N ormal Boo t.

6 EP9312 User’s Manual - DS515UM2

LCSn7, LCSn6: Latched version of CSn7 and CSn6 respectively. These

are used to define the extern al bus w idth for the boo t code boot.

LASDO: Latched v ersion o f ASDO pin. Used t o select s y nchronou s

versus asynchronous boot device. LEEDA: Latched ve rs ion of EEDAT pin. LEECLK: Define Int ernal or external boot:

1 Internal

0 External LCSn2, LCSn1: Define Watchdog startup action:

0 0 Watchdog disabled, Reset duration disabled

0 1 Watchdog disabled, Reset duration active

1 0 Watchdog active, Reset duration disabled

1 1 Watchdog active, Reset duration active

This page int entionally blank.

8 EP9312 User’s Manual - DS515UM2

Preface............................................................................................................. 3

About the EP9312 User’s Guide ......................................................................... ....... ....... .......... ...........3

How to Use this Guide...........................................................................................................................3

Related Documents from Cirrus Logic...................................................................................................4

Reference Doc ume nt s... ........................................................................................................................4

Notational Conventions. ......................................................................................................................... 5

Chapter 1 Introduction............................................................................... 27

1.1 Introduction .................................................................................................. .................................27

1.2 EP9312 Features..........................................................................................................................28

1.3 EP9312 Applications.....................................................................................................................29

1.4 Overview of EP9312 Features......................................................................................................30

1.4.1 High-Performance ARM920T Processor Core ....................................................................30

1.4.2 MaverickCrunch™ Coprocessor for Ultra-Fast Math Processing ........................................30

1.4.3 MaverickKey™ Unique ID Secures Digital Content and OEM Designs ..............................30

1.4.4 Integrated Three-port USB 2.0 Full Speed Host with Transceivers.....................................31

1.4.5 Integrated Ethernet MAC Reduces BOM Costs .. ................................................................31

1.4.6 8x8 Keypad Interface Reduces BOM Costs........................................................................31

1.4.7 Multiple Booting Mechanisms Increase Flexibility...............................................................31

1.4.8 Abundant General Purpose I/Os Build Flexible Systems ....................................................32

1.4.9 General-Purpose Memory Interface (SDRAM, SRAM, ROM and FLASH) .........................32

1.4.10 12-Bit Analog-to-Digital Converter (ADC) Provides an Integrated

Touch-Screen Interface or General ADC Functionality.............................................. 32

Chapter 2 ARM920T Core and Advanced High-Speed Bus (AHB)......... 33

2.1 Introduction .................................................................................................. .................................33

2.2 Overview: ARM920T Processor Core...........................................................................................33

2.2.1 Features .............................................................................................................................. 33

2.2.2 Block Diagram ..................................................................................................................... 34

2.2.3 Operations...........................................................................................................................34

2.2.3.1 ARM9TDMI Cor e..... ..................................................................................... ..............35

2.2.3.2 Memory Management Unit.........................................................................................36

2.2.3.3 Cache and Write Buffer...................................... ........................................................37

2.2.4 Coprocessor Interface......................................................................................................... 38

2.2.5 AMBA AHB Bus Interface Overview....................................................................................39

2.2.6 EP9312 AHB Implementation Details..................................................................................40

2.2.7 Memory and Bus Access Errors..........................................................................................41

2.2.8 Bus Arbitration.....................................................................................................................42

2.2.8.1 Main AHB Bus Arb it e r........... ........................................... ..........................................42

2.2.8.2 SDRAM Slave Arbi te r................. ................................................................................43

2.2.8.3 EBI Bus Arbiter...........................................................................................................43

2.3 AHB Decoder................................................................................................................................43

2.3.1 AHB Bus Slave....................................................................................................................44

2.3.2 AHB to APB Bridge..............................................................................................................44

2.3.2.1 Function and Operation of APB Bridge......................................................................45

2.3.3 APB Bus Slave....................................................................................................................45

2.3.4 Register Definitions .............................................................................................................46

2.3.5 Memory Map........................................................................................................................49

2.3.6 Internal Register Map.......................................................................................................... 50

2.3.6.1 Memory Access Rules............................................................................................... 50

Chapter 3 MaverickCrunch Coprocessor .................................................67

3.1 Introduction................................................................................................... ................................ 67

3.1.1 Features .............................................................................................................................. 67

3.1.2 Operational Overview..........................................................................................................67

3.1.3 Pipelines and Latency......................................................................................................... 69

3.1.4 Data Registers .................................................................................................................... 69

3.1.5 Integer Saturation Arithmetic............................................................................................... 70

3.1.6 Comp arisons....................................................................................................................... 72

3.2 Programming Exa mples ............................................................................................................... 73

3.2.1 Example 1........................................................................................................................... 73

3.2.1.1 Setup Code................................................................................................................ 74

3.2.1.2 C Code ...................................................................................................................... 74

3.2.1.3 Accessing MaverickCrunch with ARM Coprocessor Instru ctions.............................. 74

3.2.1.4 MaverickCrunch Assembly Language Instructions.................................................... 74

3.2.2 Example 2...........................................................................................................................74

3.2.2.1 C Code ......................................................................................................................75

3.2.2.2 MaverickCrunch Assembly Language Instructions.................................................... 75

3.3 DSPSC Register...........................................................................................................................76

3.4 ARM Coprocessor Instruction F ormat .......................................................................................... 79

3.5 Instruction Set for the MaverickCrunch Coprocessor...................................................................84

3.5.1 Load and Store Instructions................................................................................................88

3.5.2 Move Instructions................................................................................................................92

3.5.3 Accumulator and DSPSC Move Instructions....................................................................... 96

3.5.4 Copy and Conversion Instructions....................................................................................100

3.5.5 Shift Instructions................................................................................................................ 104

3.5.6 Comp are Instructions........................................................................................................106

3.5.7 Floating Point Arithmetic Instructions................................................................................ 108

3.5.8 Integer Arithmetic Instructions........................................................................................... 112

3.5.9 Accumulator Arithmetic Instructions..................................................................................116

Chapter 4 Boot ROM.................................................................................119

4.1 Introduction................................................................................................... .............................. 119

4.1.1 Boot ROM Hardware Operational Overview.....................................................................119

4.1.1.1 Memory Map....... ...................................................................................... ...............119

4.1.2 Boot ROM Software Operational Overview....................................................................... 119

4.1.2.1 Image Header..........................................................................................................120

4.1.2.2 Boot Algorithm.........................................................................................................120

4.1.2.3 Flowchart................................................................................................................. 122

4.2 Boot Options............................................................................................................................... 123

4.2.1 UART Boot........................................................................................................................ 123

4.2.2 SPI Boot ............................................................................................................................ 124

4.2.3 FLASH Boot...................................................................................................................... 124

4.2.4 SDRAM or SyncFLASH Boot............................................................................................125

4.2.5 Synchronous Memory Operation ...................................................................................... 1 25

10 EP9312 User’s Manual - DS515UM2

Chapter 5 System Controller................................................................... 127

5.1 Introduction .................................................................................................. ...............................127

5.1.1 System Startup..................................................................................................................127

5.1.2 System Reset....................................................................................................................1 27

5.1.3 Hardware Configuration Control........................................................................................1 28

5.1.4 Software Syste m Configuration Options............................................................................ 1 30

5.1.5 Clock Control.....................................................................................................................130

5.1.5.1 Oscillators and Programmable PLLs... .....................................................................130

5.1.5.2 Bus and Peripheral Clock Generation......................................................................131

5.1.5.3 Steps for Clock Co nf iguration................................................. .................................135

5.1.6 Power Management ..........................................................................................................1 36

5.1.6.1 Clock Gatings........................................................................................................... 1 36

5.1.6.2 System Power States...............................................................................................136

5.1.7 Interrupt Generation . .........................................................................................................1 38

5.2 Registers..... ....................................................................... .........................................................140

Chapter 6 Vectored Interrupt Controller................................................. 163

6.1 Introduction .................................................................................................. ...............................163

6.1.1 Interrupt Priority .................................................................................................................164

6.1.2 Interrupt Descriptions ........................................................................................................1 66

6.2 Registers..... ....................................................................... .........................................................171

Chapter 7 Raster Engine With Analog/LCD Integrated Timing and

Interface....................................................................................................... 181

7.1 Introduction .................................................................................................. ...............................181

7.2 Features................................................................................................ ......................................183

7.3 Raster Engine Featu re s Ov erview ..............................................................................................183

7.3.1 Hardware Blinking .............................................................................................................1 83

7.3.2 Color Look-Up Tables........................................................................................................184

7.3.3 Grayscale/Color Generation for Monochrome/Passive Low Color Displays .....................184

7.3.4 Frame Buffer O rganization................................................................................................184

7.3.5 Frame Buffer Me mor y Size..................................... ...........................................................186

7.3.6 Pulse Width Modulated Brightness....................................................................................186

7.3.7 Hardware Cursor...............................................................................................................1 87

7.4 Functional Det a il s.............. ..................................................................................... .....................1 88

7.4.1 VILOSATI (Video Image Line Output Scanner and Transfer Interface) ............................188

7.4.2 Video FIFO ........................................................................................................................190

7.4.3 Video Pixel MUX................................................................................................................190

7.4.4 Blink Function ....................................................................................................................190

7.4.5 Color Look-Up-Tables .......................................................................................................191

7.4.6 Color RGB Mux .................................................................................................................1 92

7.4.7 Pixel Shift Logic.................................................................................................................192

7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays.......................196

7.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters ..................................... ..... .. ..... .. ..... ..... .. .....197

7.4.8.2 VERT_CNT3, VERT_CNT4 Counters................................ ..... ....... .. ..... .. .......... .. .....197

7.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters....... .........................................................197

7.4.8.4 HORZ_CNTx (pixel) timing......................................................................................197

7.4.8.5 VERT_CNTx (li n e ) timing........................................................................................ 197

7.4.8.6 FRAME_CNTx ti mi n g..... ......................................................... ................................ 197

7.4.8.7 Grays ca le L ook-Up Table (GrySclL UT)................................................................... 198

7.4.8.8 GryScl L U T Timi n g Diagr am...... ............................................................................... 199

7.4.9 Hardware Cursor...............................................................................................................208

7.4.9.1 Re gisters Used for Cursor....................................................................................... 2 10

7.4.10 Video Timing ...................................................................................................................211

7.4.10.1 Setting the Video Memory Parameters.................................................................. 214

7.4.10.2 PixelMode.............................................................................................................. 216

7.4.11 Blink Logic .......................................................................................................................216

7.4.11.1 BlinkRate............................................................................................................... 216

7.4.11.2 Defining Blink Pixels..............................................................................................217

7.4.11.3 Types of Blinking ...................................................................................................217

7.4.12 Color Mode Definition...................................................................................................... 219

7.4.12.1 Pixel Look-u p Table............................................................................................... 219

7.4.12.2 Triple 8-bit Mode.................................................................................................... 220

7.4.12.3 16-bit 565 Mode..................................................................................................... 220

7.4.12.4 16-bit 555 Mode..................................................................................................... 220

7.5 Registers ........ ......................................................... ................................................................... 221

Chapter 8 1/10/100 Mbps Ethernet LAN Controller................................263

8.1 Introduction................................................................................................... .............................. 263

8.1.1 Deta iled Description .......................................................................................................... 263

8.1.1.1 Host Inter face and Descriptor Pro ce sso r..... ............................................................ 263

8.1.1.2 Reset and Initialization ............................................................................................264

8.1.1.3 Powerd own Mod es......... .............. ........................................................................... 264

8.1.1.4 Address Space ........................................................................................................265

8.1.2 MAC Engine...................................................................................................................... 265

8.1.2.1 Da ta Encapsulation ................................................................................................. 265

8.1.3 Packet Transmission Process...........................................................................................266

8.1.3.1 Carri er Defe r e n ce......... ........................................................................................... 267

8.1.4 Transmit Back-Off............................................................................................................. 269

8.1.4.1 Transmission...........................................................................................................269

8.1.4.2 The FCS Field ......................................................................................................... 270

8.1.4.3 Bit Orde r................ ..................................................................................... .............270

8.1.4.4 De stination Address (DA) Filter............................................................................... 270

8.1.4.5 Perfect Address Filtering ......................................................................................... 270

8.1.4.6 Ha sh Filter...............................................................................................................271

8.1.4.7 Flow Control ............................................................................................................ 272

8.1.4.8 Receive Fl o w Contro l..............................................................................................272

8.1.4.9 Transmit Flow Control ............................................................................................. 273

8.1.4.10 Rx Missed and Tx Collisi o n Counters........ ............................................................ 273

8.1.4.11 Accessing the MII.................................................................................................. 274

8.2 Descriptor Proc e sso r.................................................................................................................. 275

8.2.1 Receive Descriptor Processor Queues.............................................................................275

8.2.2 Receive Descriptor Queue................................................................................................ 276

8.2.3 Receive Status Queue...................................................................................................... 278

12 EP9312 User’s Manual - DS515UM2

8.2.3.1 Receive Sta tus Format.......................................................................... ...................281

8.2.3.2 Receive Fl o w.. ..........................................................................................................2 84

8.2.3.3 Receive Er ro r s................................ .........................................................................285

8.2.3.4 Re ceive Descriptor Data/Status Flow ......................................................................286

8.2.3.5 Receive Des cr iptor Example........ ............................................................................287

8.2.3.6 Receive Fra me Pre-Proces sing.......... .....................................................................287

8.2.3.7 Transmit Descriptor Processor.................................................................................2 88

8.2.3.8 Transmit Descriptor Queue......................................................................................288

8.2.3.9 Transmit Descriptor Format.....................................................................................2 91

8.2.3.10 Transmit Status Queue ..........................................................................................292

8.2.3.11 Transmit Status Format..........................................................................................2 94

8.2.3.12 Transmit Flow.........................................................................................................296

8.2.3.13 Transmit Erro rs ......................................................................................................297

8.2.3.14 Transmit Descriptor Data/Status Flow ...................................................................298

8.2.4 Interrupts ........................................................................................................................... 2 99

8.2.4.1 Interrupt Processing.................................................................................................299

8.2.5 Initialization........................................................................................................................299

8.2.5.1 Interrupt Processing.................................................................................................300

8.2.5.2 Receive Queue Processing............................................................ ......... .......... .......300

8.2.5.3 Transmit Queue Processing.....................................................................................300

8.2.5.4 O ther Processing.....................................................................................................301

8.2.5.5 Transmit Restart Process.........................................................................................301

8.3 Registers..... ....................................................................... .........................................................3 03

Chapter 9 DMA Controller........................................................................ 357

9.1 Introduction .................................................................................................. ...............................357

9.1.1 DMA Features List.............................................................................................................3 57

9.1.2 Managing Data Transfers Using a DMA Channel .............................................................358

9.1.3 DMA Operations................................................................................................................ 3 60

9.1.3.1 Memory-to-Memory Channels..................................................................................360

9.1.3.2 Memory-to-Peripheral Channels............................................... ....... ....... ..... ....... .....361

9.1.4 Internal M2P or P2M AHB Master Inte rface Functional Description..................................361

9.1.5 M2M AHB Master Interface Functional Description. ..........................................................362

9.1.5.1 Software Trigger Mode............................................................................ .......... .. .....362

9.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and

for External Peripherals without Handshaking Signals ..................................................... 3 62

9.1.5.3 Hardware Trigger Mode for External Peripherals with Handshaking Signals .......... 3 63

9.1.6 AHB Slave Interface Limitations........................................................................................363

9.1.7 Interrupt Interface .............................................................................................................. 3 63

9.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description....................................3 63

9.1.9 Internal M2P/P2M DMA Functional Description .. ..............................................................3 64

9.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine..................................3 64

9.1.9.2 Data Tran sfe r In itiation and Termination......... ............................. ............................366

9.1.10 M2 M DMA Functional Description...................................................................................3 67

9.1.10.1 M2M DMA Control Finite State Machine................................................................367

9.1.10.2 M2M Buffer Control Finite State Machine..............................................................369

9.1.10.3 Data Transfer Initia tion ...........................................................................................371

9.1.10.4 Data Transfer Termination..................................................................................... 3 73

9.1.10.5 Memory Block Transfer .........................................................................................374

9.1.10.6 Bandwidth Control ................................................................................................. 3 74

9.1.10.7 External Peripheral DMA Request (DREQ) Mode.. ...............................................374

9.1.11 DMA Data Transfer Size Determinatio n.......................................................................... 376

9.1.11.1 Software Initiated M2M and M2P/P2M Transfe rs... ............................................... 376

9.1.11.2 Hardware Initiated M2M Transfers........................................................................ 376

9.1.12 Buffer Des cr iptors........................................................................................................... 377

9.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors................................................ 377

9.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors. . ...............................................377

9.1.12.3 M2M Channel Buffer Descriptors........................................................................... 377

9.1.13 Bu s Arbitration................................................................................................................. 377

9.2 Registers ........ ......................................................... ................................................................... 379

9.2.1 DMA Controller Memory Map............................................................................................ 379

9.2.2 Internal M2P/P2M Channel Register Map......................................................................... 379

Chapter 10 Universal Serial Bus Host Controller ..................................407

10.1 Introduc tion...................................................................................................... .........................407

10.1.1 Feature s..................... ...................................................................................... ...............407

10.2 Overview................... ..................................................................................... ...........................407

10.2.1 Data Transf e r Type s..... ..................................................................................................408

10.2.2 Host Controller Interface................................................................................................. 409

10.2.2.1 Communication Channels .....................................................................................409

10.2.2.2 Data Structures...................................................................................................... 410

10.2.3 Host Controller Driver Responsibilities............................................................................ 412

10.2.3.1 Host Controller Management . ................................................................................412

10.2.3.2 Bandwidth All ocation.............................................................................................412

10.2.3.3 List Management................................................................................................... 413

10.2.3.4 Root Hub ............................................................................................................... 414

10.2.4 Host Controlle r Responsibilities ............ ...... ....... ...... ....... ..... ....... ....... ..... ....... ....... ..... ..... 414

10.2.4.1 USB States............................................................................................................414

10.2.4.2 Frame manageme nt . . ............................................................................................ 414

10.2.4.3 List Processing ......................................................................................................414

10.2.5 USB Host Control ler Bl o cks............................................................................................ 415

10.2.5.1 AHB Slave.............................................................................................................415

10.2.5.2 AHB Master...........................................................................................................415

10.2.5.3 HCI Slave Block..................................................................................................... 415

10.2.5.4 HCI Master Bl ock ................................................................................................... 416

10.2.5.5 USB State Control................................................................................................. 416

10.2.5.6 Data FIFO.............................................................................................................. 416

10.2.5.7 List Processor........................................................................................................416

10.2.5.8 Root Hub and Host SIE .........................................................................................416

10.3 Registers................................................ .................................................................................. 417

Chapter 11 Static Memory Controller......................................................445

11.1 Introduc tion...................................................................................................... .........................445

11.2 Static Memory Controller Operation ......................................................................................... 446

11.3 Byte Lane Write / Read Control................................................................................................448

14 EP9312 User’s Manual - DS515UM2

11.4 Registers................................................................... ................................................................450

Chapter 12 SDRAM, SyncROM, and SyncFLASH Controller................ 453

12.1 Introduc tion ..................... ..................................................................................... .....................4 53

12.1.1 Booting ( fr o m SROM or SyncF LA SH). ............................................................................453

12.1.1.1 Address Pin Usa ge ................................................................................................4 54

12.1.1.2 SDRAM Initialization.............................................................................................. 4 56

12.1.1.3 Programming External Device Mode Register.......................................................457

12.1.1.4 SDRAM Self Refre sh .............................................................................................460

12.1.1.5 SROM and SyncFlash............................................................................................460

12.1.1.6 External Synchronous Memory System................................................................. 461

12.2 Registers................................................................... ................................................................465

Chapter 13 UART1 With HDLC and Modem Control Signals................ 473

13.1 Introduc tion ..................... ..................................................................................... .....................4 73

13.2 UART Overview........................................................................................................................473

13.2.1 UART Functional Description .......................................................................................... 4 74

13.2.1.1 AMBA APB Interface..............................................................................................474

13.2.1.2 DMA Block.............................................................................................................474

13.2.1.3 Register Block........................................................................................................475

13.2.1.4 Baud Rate Gene rator............................................................................................. 4 76

13.2.1.5 Transmit FIFO........................................................................................................476

13.2.1.6 Receive FIFO.........................................................................................................476

13.2.1.7 Transmit Logic........................................................................................................476

13.2.1.8 Receive Logic.........................................................................................................476

13.2.1.9 Interrupt Generation Logic .... .................................................................................476

13.2.1.10 Synchronizing Registers and Logic......................................................................477

13.2.2 UART Operation..............................................................................................................477

13.2.2.1 Error Bits................................................................................................................478

13.2.2.2 Disabling the FIFOs...............................................................................................4 78

13.2.2.3 System/diagnostic Loop back Testing . ....................................................................478

13.2.2.4 UART Character Frame.........................................................................................478

13.2.3 Interr u p ts.................................... .....................................................................................479

13.2.3.1 UARTMSINTR........................................................................................................479

13.2.3.2 UARTRXINTR ........................................................................................................4 79

13.2.3.3 UARTTXINTR........................................................................................................4 80

13.2.3.4 UARTRTINTR........................................................................................................480

13.2.3.5 UARTINTR.............................................................................................................480

13.3 Modem ......................................................................................................................................480

13.4 HDLC ........ ................................................................................................................................481

13.4.1 Overview of HDLC Modes............................................................................................... 4 81

13.4.2 Se lecting HDLC Modes...................................................................................................482

13.4.3 HDLC Transmit................................................................................................................483

13.4.4 HDLC Receive.................................................................................................................484

13.4.5 CRCs.... ...........................................................................................................................485

13.4.6 Ad dress Matching............................................................................................................ 4 85

13.4.7 Aborts............... ..................................................................................... ..........................486

13.4.8 DMA.................................................................................................................................486

13.4.9 Writing Configuration Registers...................................................................................... 487

13.5 UART1 Package Dependency ..................................................................................................487

13.5.1 Clocking Requirements...................................................................................................488

13.5.2 Bus Bandwidth Requirements.........................................................................................488

13.6 Registers................................................ .................................................................................. 490

Chapter 14 UART2 ....................................................................................511

14.1 Introduc tion...................................................................................................... .........................511

14.2 IrDA SIR Block..........................................................................................................................511

14.2.1 IrDA SIR Encoder/decoder Functional Description......................................................... 511

14.2.1.1 IrDA SIR Transmit Encoder................................................................................... 5 12

14.2.1.2 IrDA SIR Receive Decoder.................................................................................... 512

14.2.2 IrDA SIR Operation......................................................................................................... 513

14.2.2.1 System/diagnostic Loop back Tes ting....................................................................514

14.2.3 IrDA Data Modulation ......................................................................................................514

14.2.4 Enabling Infrared (Ir) Modes ............................................... ....... ....... ....... .......... .. ....... ....515

14.3 UART2 Package Dependency ..................................................................................................515

14.3.1 Clocking Requirements...................................................................................................515

14.3.2 Bus Bandwidth Requirements.........................................................................................516

14.4 Registers................................................ .................................................................................. 517

Chapter 15 UART3 With HDLC Encoder .................................................529

15.1 Introduc tion...................................................................................................... .........................529

15.2 Implement at ion Details............................................................................................................. 529

15.2.1 UART3 Package Dependency ........................................................................................ 529

15.2.2 Clocking Requirements...................................................................................................530

15.2.3 Bus Bandwidth Requirements.........................................................................................530

15.3 Registers................................................ .................................................................................. 531

Chapter 16 IrDA.........................................................................................549

16.1 Introduc tion...................................................................................................... .........................549

16.2 IrDA Interfaces..........................................................................................................................549

16.3 Shared IrDA Interface Feature ................................................................................................. 550

16.3.1 Overvie w......................... ..................................................................................... ........... 550

16.3.2 Functi o n al Des cr iption....... ............... ............................................................................... 550

16.3.2.1 General Configuration ........................................................................................... 551

16.3.2.2 Transmitting Data.................................................................................................. 551

16.3.2.3 Receiving Data......................................................................................................554

16.3.2.4 Special Conditions.................................................................................................556

16.3.3 Control Information Buffering.......................................................................................... 556

16.4 Medium IrDA Specific Features ................................................................................................557

16.4.1 Introduction ..................................................................................................................... 557

16.4.1.1 Bit Encoding ..........................................................................................................557

16.4.1.2 Frame Format........................................................................................................ 557

16.4.2 Functi o n al Des cr iption....... ............... ............................................................................... 559

16.4.2.1 Baud Rate Gene ration...........................................................................................559

16.4.2.2 Receive Operation.................................................................................................560

16.4.2.3 Transmit Operation................................................................................................561

16 EP9312 User’s Manual - DS515UM2

16.5 Fast IrDA Specific Features......................................................................................................562

16.5.1 Introduction....................... ................... ................... .............. ................... ....... .................562

16.5.1.1 4PPM Modulation................................................................................................... 5 62

16.5.1.2 4.0 Mbps FIR Frame Format..................................................................................5 64

16.5.2 Functi o n al Des cr iption........... ............................. ......................................................... ....565

16.5.2.1 Baud Rate Gene ration ........................................................................................... 5 66

16.5.2.2 Receive Operation.................................................................................................5 66

16.5.2.3 Transmit Operation ................................................................................................5 68

16.5.3 IrDA Connectivity.............................................................................................................569

16.5.4 IrDA Integration In formation ............................................................................................570

16.5.4.1 Enabling Infrared Modes........................................................................................ 570

16.5.4.2 Clocking Requirements..........................................................................................570

16.5.4.3 Bus Bandwidth Requirements................................................................................5 71

16.6 Registers................................................................... ................................................................572

Chapter 17 Timers .................................................................................... 587

17.1 Introduc tion ..................... ..................................................................................... .....................5 87

17.1.1 Feature s...... ..................................................................................... ...............................587

17.1.2 16 and 32-bit Timer Operation.........................................................................................587

17.1.2.1 Free Running Mode ...............................................................................................588

17.1.2.2 Pre-load Mode........................................................................................................588

17.1.3 40-bit Ti me r Ope r a ti o n.... .............. ................................................................................... 5 88

17.2 Registers................................................................... ................................................................589

Chapter 18 Watchdog Timer.................................................................... 595

18.1 Introduc tion ..................... ..................................................................................... .....................5 95

18.1.1 Watchdog Activation........................................................................................................596

18.1.2 Clocking Requirements ...................................................................................................596

18.1.3 Reset Requirements........................................................................................................596

18.1.4 Watchdog Status .............................................................................................................596

18.2 Registers................................................................... ................................................................598

Chapter 19 Real Time Clock With Software Trim .................................. 601

19.1 Introduc tion ..................... ..................................................................................... .....................6 01

19.1.1 So ftware Trim..................................................................................................................601

19.1.1.1 Software Compensation.........................................................................................602

19.1.1.2 Oscillator Frequency Calibration............................................................................602

19.1.1.3 RTCSWComp Value Determination.......................................................................602

19.1.1.4 Example - Measured Value Split Into Integer and Fractional Component .............6 03

19.1.1.5 Maximum Error Calculation vs. Real Time Clock Accuracy................................... 6 03

19.1.1.6 Real-Time Interrupt................................................................................................604

19.1.2 Reset Control...................................................................................................................6 04

19.2 Registers................................................................... ................................................................605

Chapt er 20 I2S Controller......................................................................... 609

20.1 Introduc tion ..................... ..................................................................................... .....................6 09

20.2 I

20.3 I

S Transmitter Channel Overview.................................................................. .. ....... .......... .. .....611

S Receiver Channel Overview................................................... .. .......... .. ....... ..... ....... ..... .. .....615

20.3.1 Receiver FIFO’s.............................................................................................................. 615

20.4 I

20.5 I

20.6 I

S Configuration and Status Registers.................................................................................... 617

S Master Clock Generation...... .............................................................................................. 617

S Bit Clock Rate Generat ion....... ........................................................................................... 619

20.6.1 Example of the Bit Cl ock Generation.............................................................................. 620

20.6.2 Example of Righ t Ju stified LRCK format........ ................................................................. 620

20.7 Interru p ts.................................. ................................................................................................ 621

20.8 Registers................................................ .................................................................................. 623

20.8.1 I

20.8.2 I

20.8.3 I

20.8.4 I

S TX Registers...... ........................................... ............................................................ 623

S RX Registers............................................................................................................. 630

S Configurat ion and Sta tu s Re gisters .......................................................................... 636

S Global Status Registers ............................................................................................640

Chapter 21 AC’97 Controller....................................................................643

21.1 Introduc tion...................................................................................................... .........................643

21.2 Interru p ts.................................. ................................................................................................ 645

21.2.1 Channel Interrupts.......................................................... .......... ....... ....... ....... ....... ........... 645

21.2.1.1 RIS......................................................................................................................... 645

21.2.1.2 TIS......................................................................................................................... 646

21.2.1.3 RTIS ...................................................................................................................... 646

21.2.1.4 TCIS ...................................................................................................................... 646

21.2.2 Global Interrupts.............................................................................................................. 646

21.2.2.1 CODECREADY..................................................................................................... 646

21.2.2.2 WINT ..................................................................................................................... 6 46

21.2.2.3 GPIOINT................................................................................................................ 647

21.2.2.4 GPIOTXCOMPLETE.............................................................................................647

21.2.2.5 SLOT2INT ............................................................................................................. 647

21.2.2.6 SLOT1TXCOMPLETE........................................................................................... 647

21.2.2.7 SLOT2TXCOMPLETE........................................................................................... 647

21.3 System Loopback Testing .......................................................................... ................... ........... 647

21.4 Registers................................................ .................................................................................. 648

Chapter 22 Synchronous Serial Port ......................................................667

22.1 Introduc tion...................................................................................................... .........................667

22.2 Features....... ..................................................................................... ....................................... 667

22.3 SSP Functionality ..................................................................................................................... 6 68

22.4 SSP Pin Multiplex.....................................................................................................................668

22.5 Configurin g th e SSP.................................................................................................................668

22.5.1 Enabli ng SSP Ope ra tion ................................................................................................. 669

22.5.2 Master/Slave Mode.. ........................................... ......................................................... ... 669

22.5.3 Serial Bit Rate Generation ..............................................................................................669

22.5.4 Frame Format............................................................. ................................................... 6 69

22.5.5 Texas Instruments® Synchronous Serial Frame Format ................................................ 6 70

22.5.6 Mo torola® SPI Frame Format.........................................................................................671

22.5.6.1 SPO Clock Polarity................................................................................................671

22.5.6.2 SPH Clock Phase..................................................................................................671

22.5.7 Motoro la SPI Format with SPO=0, SPH=0.............................................. ....................... 671

22.5.8 Motorola SPI Format with SPO=0, SPH=1 .................................................................... 673

18 EP9312 User’s Manual - DS515UM2

22.5.9 Motoro la SPI Format with SPO=1, SPH=0................................................... ...................674

22.5.10 Motoro la SPI Format with SPO=1, SPH=1....................................................................676

22.5.11 National Semiconductor® Microwire® Frame Format................................ .. ............ .....677

22.5.11.1 Setup and Hold Time Requirements on SFRMIN with

Respect to SCLKIN in Micro w ire Mode.............................................................................679

22.6 Registers................................................................... ................................................................680

Chapter 23 Pulse Width Modulator......................................................... 687

23.1 Introduc tion ..................... ..................................................................................... .....................6 87

23.2 Theory of Operation ..................................................................................................................687

23.2.1 PW M Programming Example s ........................................................................................6 88

23.2.1.1 Example.................................................................................................................688

23.2.1.2 Static Programming (PWM is Not Running) Example............................................688

23.2.1.3 Dynamic Programming (PWM is Running) Example............................................. 6 89

23.2.2 Program mi n g Rules............................................................................................. ............689

23.3 Registers................................................................... ................................................................690

Chapter 24 Analog Touch Screen Interface........................................... 695

24.1 Introduc tion ..................... ..................................................................................... .....................6 95

24.2 Touch Screen Controller Operation . .........................................................................................695

24.2.1 Touch Screen Scanning: Four-wire and Eight-wire Operation ........................................698

24.2.2 Five-wire and Seven-wire Operation ...............................................................................705

24.2.3 Direct Operation ..............................................................................................................708

24.2.4 Measuring Analog Input with the Touch Screen Controls Disabled ................................ 7 10

24.2.5 Me asuring Touch Scre en Resistance..............................................................................7 12

24.2.6 Polled and Interrupt-Driven Modes.................................................................................. 714

24.2.7 Touch Screen Package Dependency..............................................................................714

24.3 Registers................................................................... ................................................................715

Chapter 25 Keypad Interface................................................................... 723

25.1 Introduc tion ..................... ..................................................................................... .....................7 23

25.2 Theory of Operation ..................................................................................................................724

25.2.1 Apparent Ke y Det ection................................... ................................................................725

25.2.2 Scan and Debounce............................................................. ............ ............ .............. .....727

25.2.3 Interrupt Generation ............................................. ....... ....... ....... ....... ....... ....... .......... .......728

25.2.4 Low Power Mode.............................................................................................................728

25.2.5 Three-key Reset..............................................................................................................729

25.3 Registers................................................................... ................................................................730

Chapter 26 IDE Interface.......................................................................... 735

26.1 Introduc tion ..................... ..................................................................................... .....................7 35

26.2 Theory of Operation ..................................................................................................................735

26.2.1 Diagrams and Sta te Mach ines ........................................................................................736

26.2.2 PIO Operations ................................................................................................................737

26.2.3 MDMA Operations...........................................................................................................739

26.2.4 UDMA Operations ...........................................................................................................739

26.2.5 Pe rformance Considerations...........................................................................................740

26.2.6 UDMA Example...............................................................................................................740

26.2.7 DMA Request Latency.................................................................................................... 742

26.2.7.1 DMA Request Deassertion.................................................................................... 742

26.2.7.2 DMA Request Latency Overview........................................................................... 742

26.2.7.3 IDE DMA Programming Considerations................................................................ 743

26.2.8 IDE Package Dependency..............................................................................................744

26.2.8.1 System Configuration Constraints.........................................................................744

26.2.8.2 Bus Bandwidth Requirements ............................................................................... 744

26.3 Registers................................................ .................................................................................. 746

Chapter 27 GPIO Interface .......................................................................757

27.1 Introduc tion...................................................................................................... .........................757

27.1.1 Me mory Map................................................................................................................... 758

27.1.2 Functi o n al Des cr iption....... ............... ............................................................................... 759

27.1.3 Reset............................................................................................................................... 7 61

27.1.4 GPIO Pin Map................................................................................................................. 7 61

27.2 Registers................................................ .................................................................................. 764

Chapter 28 Security ..................................................................................773

28.1 Introduc tion...................................................................................................... .........................773

28.2 Features....... ..................................................................................... ....................................... 773

28.3 Contact Information..................................................................................................................773

28.4 Registers................................................ .................................................................................. 774

Chapter 29 Glossary .................................................................................775

20 EP9312 User’s Manual - DS515UM2

List of Figures

Figure 1-1. EP9312 Block Diagram ..................................................................................27

Figure 2-1. ARM920T Block Diagram ................................................................................. 34

Figure 2-2. Typical AMBA AHB System ............................................................................39

Figure 2-3. EP9312 Main Data Paths..................................................................................40

Figure 4-1. Flow Chart of Boot ROM Software .............................................................. 122

Figure 4-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices .............................125

Figure 5-1. Phase Locked Loop (PLL) Structure ............................................................131

Figure 5-2. EP9312 Clock Generation System.................................................................. 132

Figure 5-3. Bus Clock Generation ................................................................................... 133

Figure 5-4. EP9312 Power States and Transitions .........................................................137

Figure 6-1. Vectored Interrupt Controller Block Diagram ................................................164

Figure 7-1. Raster Engine Block Diagram ......................................................................188

Figure 7-2. Video Buffer Diagram ...................................................................................189

Figure 7-3. Graphics Matrix for 50% Duty Cycle ............................................................. 202

Figure 7-4. Sample Matrix Causing Flickering ................................................................ 203

Figure 7-5. Sample Matrix That Avoids Flickering .......................................................... 204

Figure 7-6. Programming for One-third Luminous Intensity ............................................ 205

Figure 7-7. Creating Bit Patterns th at Move to the Right ................................................ 206

Figure 7-8. Three and Four Count Axis ..........................................................................207

Figure 7-9. Progressive/Dual Scan Video Signals ..........................................................213

Figure 7-10. Interlaced Video Signals ...............................................................................214

Figure 8-1. Block Diagram ................................................................................................263

Figure 8-2. Ethernet Frame / Packet Format (Type II only)...............................................266

Figure 8-3. Packet Transmission Process.........................................................................267

Figure 8-4. Carrier Deference State Diagram....................................................................268

Figure 8-5. Data Bit Transmission Order ..........................................................................270

Figure 8-6. CRC Logic ....................................................................................................271

Figure 8-7. Receive Descriptor Format and Data Fragments .........................................277

Figure 8-8. Receive Status Queue ..................................................................................280

Figure 8-9. Receive Flow Diagram .................................................................................284

Figure 8-10. Receive Descriptor Data/Status Flow ...........................................................286

Figure 8-11. Receive Descriptor Example ........................................................................287

Figure 8-12. Receive Frame Pre-processing ..................................................................288

Figure 8-13. Transmit Descriptor Format and Data Fragments ........................................290

Figure 8-14. Multi ple Fragments Per Transmit Frame ...................................................... 290

Figure 8-15. Transmit Status Queue ............................................................................... 293

Figure 8-16. Transmit Flow Diagram ..............................................................................296

Figure 8-17. Transmit Descriptor Data/Status Flow ........................................................298

Figure 9-1. DMA M2P/P2M Finite State Machine.............................................................. 364

Figure 9-2. M2M DMA Control Finite State Machine.........................................................367

Figure 9-3. M2M DMA Buffer Finite State Machine ..........................................................369

Figure 9-4. Edge-triggered DREQ Mode ...........................................................................375

Figure 10-1. USB Focus Areas..........................................................................................408

Figure 10-2. Communication Channels ............................................................................. 409

Figure 10-3. Typical List Structure .................................................................................... 4 10

Figure 10-4. Interrupt Endpoint Descriptor Structure ........................................................ 411

Figure 10-5. Sample Interrupt Endpoint Schedule ............................................................412

Figure 10-6. Frame Bandwidth Allocation ......................................................................... 413

Figure 10-7. USB Host Controller Block Diagram..............................................................415

Figure 11-1. 32-bit read, 32-bit Memory, 0 wait cycles, RBLE = 1,

WAITn Inactive.......... ......................................................................................................446

Figure 11-2. 32-bit wr ite , 32-bit Memo ry , 0 w ait cyc les, RBLE = 1,

WAITn Inactive............. .................................................................................................. 447

Figure 11-3. 16-bit read, 16-bit Memory, RBLE = 1, WAITn Active ...................................447

Figure 11-4. 16-bit write, 16-bit Memory, RBLE = 1, WAITn Active...................................448

Figure 13-1. UART Block Diagram ....................................................................................475

Figure 13-2. UART Character Frame ................................................................................479

Figure 14-1. IrDA SIR Encoder/decoder Block Diagram ............... ....................................512

Figure 14-2. IrDA Data Modulation (3/16) .........................................................................514

Figure 16-1. RZ1/NRZ Bit Encoding Example ..................................................................557

Figure 16-2. 4PPM Modulation Encoding .........................................................................563

Figure 16-3. 4PPM Modulation Example ..........................................................................563

Figure 16-4. IrDA (4.0 Mbps) Transmission Format...........................................................564

Figure 20-1. Architect ural Overview of the I

S Controller ...............................................610

Figure 20-2. Transmitter FIFO’s ...................................................................................... 6 12

Figure 20-3. Bit Clock Generation Example .................................................................6 20

Figure 20-4. Frame Format for Right Justified Data ....................................................621

Figure 22-1. Texas In struments Sy nc hronous S erial Frame F ormat (Si ngle Transfe r) .....670

Figure 22-2. TI S ynchronous Serial Frame Format (Continuous Transfer)........................671

Figure 22-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0....... 672

Figure 22-4. Motorol a SPI Frame Fo rm at (Contin uous Trans fe r)

with SPO=0 and SPH=0..................................................................................................672

Figure 22-5. Motorola SPI Frame Format with SPO=0 and SPH=1...................................673

Figure 22-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0....... 674

Figure 22-7. Motorol a SPI Frame Fo rm at (Contin uous Trans fe r)

with SPO=1 and SPH=0..................................................................................................675

Figure 22-8. Motorola SPI Frame Format with SPO=1 and SPH=1...................................676

Figure 22-9. Microwire Frame Format (Single Transfer)....................................................677

Figure 22-10. Microwire Frame Format (Continuous Transfers)........................................678

Figure 22-11. Mic row ire Frame F ormat, SF R M I N In put Setup and Hold Requiremen ts.... 679

Figure 23-1. PWM_INV Example.......................................................................................693

Figure 24-1. Different Types of Touch Screens ................................................................696

Figure 24-2. 8-Wire Resistive Interface Switching Diagram..............................................700

Figure 24-3. 4-Wire Analog Resistive Interface Switching Diagram .................................. 701

Figure 24-4. Analog Resistive Touch Screen Scan Flow Chart ........................................ 704

Figure 24-5. 5-Wire Analog Resistive Interface Switching Diagram ................................. 706

Figure 24-6. 5-Wire Fe edback (7-W ire) Analog Resistiv e I nt erf ace Switching Diagr am ... 707

22 EP9312 User’s Manual - DS515UM2

Figure 24-7. Power Down Detect Press Switching Diagram ............................................. 709

Figure 24-8. Other Switching Diagrams ............................................................................ 711

Figure 24-9. Measure Resistance Switching Diagram ......................................................713

Figure 25-1. Key Array Block Diagram .........................................................................723

Figure 25-2. 8 x 8 Key Array Diagram ............................................................................725

Figure 25-3. Apparent Key 00H ....................................................................................727

Figure 26-1. IDE Interface Signal Connections ................................................................. 736

Figure 27-1. System Level GPIO Connectivity ............................................................... 758

Figure 27-2. Signal Connections W it hin the Standard GPI O Port Contr ol Logic

(Ports C, D, E, G, H) .....................................................................................................760

Figure 27-3. Signal Connections W it hin the Enh anced GPIO Port Cont rol Logic

(Ports A, B, F) ..............................................................................................................761

List of Tables

Table 2-1: AHB Arbiter Priority Scheme ......................................................................... 42

Table 2-2: AHB Peripheral A ddress Range ...................................................................... 44

Table 2-3: APB Peripheral Address Range ..................................................................... 45

Table 2-4: Register Organization Summary ........................................................................47

Table 2-5: CP15 ARM920T Register Description................................................................ 48

Table 2-6: Global Memory Map for the Two Boot Modes....................................................49

Table 2-7: Internal Register Map ....................................................................................... 51

Table 3-1: Saturation fo r Non-accumulator Instructions ......................................................71

Table 3-2: Accumulator Bit Formats for Saturation.............................................................. 71

Table 3-3: Comparison Relationships and Their Results ...................................................73

Table 3-4: ARM Condition Codes and Crunch Compare Results .......................................73

Table 3-5: Condition Code Definitions ................................................................................ 81

Table 3-6: LDC/STC Opcode Map ......................................................................................82

Table 3-7: CDP Opcode Map ..............................................................................................83

Table 3-8: MCR Opcode Map .......................................................................................... 83

Table 3-9: MRC Opcode Map ............................................................................................. 83

Table 3-10: MaverickCrunch Instruction Set ....................................................................... 84

Table 3-11: Mnemonic Codes..............................................................................................88

Table 3-12: Mnemonic Codes ........................................................................................... 89

Table 4-1: Boot Configuration Options (Normal Boot) ......................................................123

Table 5-1: Boot Configuration Options ............................................................................. 129

Table 5-2: Clock Speeds and Sources ........................................................................... 135

Table 5-3: Peripherals with PCLK gating ........................................................................136

Table 5-4: Syscon Register List .......................................................................................140

Table 5-5: Audio Interfaces Pin Assignment .....................................................................153

Table 6-1: Interrupt Configuration...................................................................................... 165

Table 6-2: VICx Register Summary................................................................................... 171

Table 7-1: Raster Engine Video Mode Output Examples ............................................... 182

Table 7-2: Byte Oriented Frame Buffer Organization ..................................................... 1 85

Table 7-3: Output Pixel Tr ansfer Modes ........................................................................... 194

Table 7-4: Grayscale Lookup Table (GrySclLUT) ...........................................................198

Table 7-5: Grayscale Timing Diagram............................................................................... 200

Table 7-6: Programming Format ..................................................................................... 201

Table 7-7: Programming 50% Duty Cycle Into Lookup Tab le .........................................205

Table 7-8: Programming 33% Duty Cycle into the Lookup Table ...................................207

Table 7-9: Programming 33% Duty Cycle into the Lookup Table ...................................208

Table 7-10: Cursor Memory Organization..........................................................................208

Table 7-11: Bits P[2:0] in the PixelMode Register .............................................................216

Table 7-12: Registe r List ................................................................................................. 221

Table 7-13: Color Mode Definition Table ........................................................................241

Table 7-14: Blink Mode Definition Table ......................................................................... 241

Table 7-15: Output Shift Mode Table .............................................................................. 241

Table 7-16: Bits per Pixel Scanned Out ............................................................................242

Table 7-17: Grayscale Look-Up-Table (LUT) ....................................................................255

Table 8-1: FIFO RAM Address Map .................................................................................265

Table 8-2: RXCtl.MA and RXCtl.IAHA[0] Relationships ..................................................272

Table 8-3: Ethernet Register List .................................................................................... 303

Table 8-4: Individual A ccept, RxFlow Control Enable and Pause Accept Bits ................ 305

Table 8-5: Address Filter Pointer .................................................................................... 315

Table 9-1: Data Transfer Size............................................................................................376

Table 9-2: M2P DMA Bus Arbitration.................................................................................378

Table 9-3: DMA Memory Map............................................................................................ 379

Table 9-4: Internal M2P/P2M Channel Register Map........................................................ 380

Table 9-5: PPALLOC Register Bits Decode for a Transmit Channel ............................ 383

Table 9-6: PPALLOC Register Bits Decode for a Receive Channel ................................. 383

Table 9-7: PPALLOC Register Reset Values ................................................................... 383

Table 9-8: M2M Channel Register Map ......................................................................... 389

Table 9-9: BWC Decode Values........................................................................................ 392

Table 9-10: DMA Global Interrupt (DMAGlInt) Register ....................................................404

Table 10-1: OpenHCI Register Addresses ....................................................................... 417

Table 11-1: nXBLS[3:0] Multiplexing..................................................................................448

Table 11-2: WRITING to an External Memory System......................................................449

Table 11-3: SMC Register Map ......................................................................................... 4 50

Table 12-1: Boot Device Selection..................................................................................... 454

Table 12-2: Synchronous Memory Address Decoding ..................................................... 456

Table 12-3: General SDRAM Initialization Sequence........................................................457

Table 12-4: Mode Register Command Decoding............................................................... 458

Table 12-5: Sync Memory CAS Settings ...........................................................................458

Table 12-6: Sync Memory RAS, (Write) Burst Typ e Settings ............................................459

Table 12-7: Burst L ength Settings .....................................................................................459

Table 12-8: Chip Select Decoding..................................................................................... 461

Table 12-9: Memory System Examples.............................................................................462

Table 12-10: Memory Address Decoding for 256 Mbit, 16-Bit Wide, and

13-Row x 9-Column x 2-Bank Device .............................................................................462

Table 12-11: 32-Bit Wide Data Systems............................................................................ 4 63

Table 12-12: 16-Bit Wide Data Systems............................................................................ 4 64

Table 12-13: Synchronous Memory Controller Registers..................................................465

Table 12-14: Synchronous Memory Command Encoding.................................................467

Table 13-1: Receive FIFO Bit Functions............................................................................ 478

Table 13-2: Legal HDLC Mode Configurations ...............................................................483

Table 13-3: HDLC Receive Address Matching Modes ...................................................... 486

Table 13-4: UART1 Pin Functionality ................................................................................ 488

Table 13-5: DeviceCfg Register Bit Functions ..................................................................488

Table 14-1: UART2 / IrDA Modes .....................................................................................515

Table 14-2: IonU2 Pin Function ........................................................................................ 515

Table 15-1: UART3 Pin Functionality ................................................................................ 529

Table 15-2: DeviceCfg Register Bit Functions ..................................................................529

Table 16-1: Bit Values to Select Ir Module ........................................................................ 551

Table 16-2: Address Offsets for End-of-frame Data ..........................................................553

Table 16-3: MIR Frame Format..........................................................................................558

Table 16-4: DeviceCfg.IonU2 Pin Function ................................................................... 569

Table 16-5: UART2 / IrDA Modes .....................................................................................570

Table 16-6: IrDA Service Memory Accesses / S econd ...................................................571

Table 17-1: Timers Register Map.......................................................................................589

Table 18-1: Register Memory Map .................................................................................598

Table 19-1: Register Memory Map ..................................................................................605

Table 20-1: I

S Controller Input and Output Signals .........................................................610

Table 20-2: Audio Interfaces Pin Assignment ................................................................... 611

Table 20-3: I2SClkDiv SYSCON Register Effect on I2S Clock Generation ...................619

Table 20-4: Bit Clock Rate Generation ...........................................................................619

Table 20-5: FIFO Flags .....................................................................................................622

Table 20-6: I Table 20-7: I Table 20-8: I

S TX Registers .......................................................................................... 623

S RX Registers .......................................................................................... 630

S Configuration and Status Registers .........................................................636

Table 21-1: Register Memory Map ..................................................................................648

Table 21-2: Interaction Between RSIZE and CM ......................................................... 651

Table 21-3: Interaction Between RSIZE and CM Bits ...................................................653

Table 22-1: SSP Register Memory Map Description ......................................................... 680

Table 23-1: Static Programming Steps.............................................................................. 688

Table 23-2: Dynamic Programming Steps.........................................................................689

Table 23-3: PWM Registers Map ..................................................................................690

Table 24-1: Sw itch Definit ions and Lo gic al Safegu ards to Preve nt Physical Damage ..... 698

Table 24-2: Touch Screen Switch Register Configurations .........................................702

Table 24-3: External Signal Functions ............................................................................714

Table 24-4: Register Memory Map ..................................................................................715

Table 25-1: Register Memory Map ..................................................................................730

Table 26-1: IDE Host to IDE Interface Definition ............................................................737

Table 26-2: IDE Cycle Times and Data Transfer Rates ....................................................742

Table 26-3: Wait State Value for the DMA M2M Register Control.PWSC .......................743

Table 26-4: HCLK Cycles to Deassert DMA Request .......................................................743

Table 26-5: Maximum Theoretical Bandwidths fo r Various Operating Modes ..................744

Table 26-6: IDE Interface Register Map.............................................................................746

Table 27-1: GPIO Port to Pin Map ....................................................................................762

Table 27-2: GPIO Register Address Map..........................................................................764

Table 28-1: Security Register List .................................................................................774

26 EP9312 User’s Manual - DS515UM2

)

1.1 Introduction

The EP93 12 is a highly integr ated system-on -chip processor th at paves the way for a multitude of next-generation consumer and industrial electronic products. De signers of digital m edia se rvers and jukebo xes, te lematic control systems, thin client s, set-top boxes, point-of -sal e ter minals, industrial control s, biometric security systems, and GPS devices will benefit f rom the EP93 12’s integrated architecture and advanced features. In fact, with amazingly agile performance provided by a 200 MHz ARM920T processor, and featuring an incredibly wide breadth of perip heral interface s, the EP9312 is well suited to an even bro ade r rang e of hig h volu me a pp licatio ns. Furthe rmo re, by enab ling or disabling the EP9312’s peripheral interfaces, designers can reduce development costs and accelerate time-to-market by creating a single platform that can be easily mod if ied to deliver a v ariety of differe nt iated end p roducts.

Figure 1-1. EP9312 Block Diagram

Chapter 1 1Introduction

18-bit Raster LCD

SDRAM

SRAM/

FLASH/ROM

12 Channel DMA

Engine

1/10/100 Ethernet

MAC

JTAG

USB Host, 3 Ports

IDE

Boot ROM

UART1 w/ HDLC UART3 w/ HDLC

MaverickCrunch

Coprocessor

ARM920T

I-Cache

AMBA High-Speed Bus (AHB)

Vectored Interrupt

Controllers (2)

D-Cache

16KB

AHB/APB

16KB

MMU

Bridge

UART2 w/ IrDA

System Ctrl - PLLs (2

Touch Screen AD

8x8 Key Scan

PWM

S (IIS)

AMBA Peripheral Bu s (APB)

Enhanced GPIO EEPROM, LED (2)

SPI

AC’97

RTC with Trim

Watchdog Timer

Timers

Introduction

1 1.2 EP9312 Features

The EP9312 system-on-chip processor has the following features:

• 200 MHz ARM920T Processor

• 16 KByte data cache and 16 KByte instruction cache

• MMU enabling Linux

• 100 MHz system bus

• MaverickCrunch

• Floating point, intege r and signal p roc essing ins tr uc t ions

• Optimized for digital music compression algorith ms

• Hardwar e interlocks allow in-lin e c oding

• MaverickKey

• 32-bit unique ID

• 128-bit random ID

• Integrated Peripheral Interfa c es

• EIDE, up to 2 devices

• 1/10/10 0 M bps Et hernet MAC

• Three-port USB 2.0 Full Speed host (OHCI)

™

IDs for Digital Rights Management or Design IP Security

and Windows® CE

Coprocessor

–

• Three UA RTs (16550 Type)

• IrDA interface, slow and fast mode

• LCD interface

• Touch screen interface

•SPI port

• AC ‘97 inte rf ac e

• I2S interface, up to 6 channels

• 8x8 keypad scanner

• External Memory Options

• 32-bit SDRAM interface, up to four banks

• 32/16/8-bit SRAM/Flash/ROM interface (I/F)

• Serial EE PR OM interfa c e

• Internal P eripherals

• Real-Time clock with software trim

28 EP9312 User’s Manual - DS515UM2

Introduction

• 12 DMA channels for data transfer that maximizes syste m performance

•Boot ROM

• Dual PLLs c ont rol all clock dom ains

• Watchdog timer

• Two general purpose 16-bit timers

• General pu rpose 32-bit t im er

• 40-bit debug timer

• General-Purpose I/Os

• 16 enhanced GPIOs inc luding inte rrupt capability

• 31 additional optional GPIOs multiplexed on peripherals

• Available in 352-pin PBGA package

1.3 EP9312 Applications

The EP9312 can be used in a variety of applications, such as:

• Digital media servers

• Integrated home media gateways

• Digital audi o juk eboxes

• Portable audio/video players

• Streaming audio / v ideo players

• Telematic control syste ms

• Set-top boxes

• Point-of-sale terminals

• Thin clients

• Internet T Vs

• Biometric security systems

• Industrial controls

• GPS & fleet management systems

• Educational toys

• Voting machines

• Medical e quipment

Introduction

1 1.4 Overview of EP9312 Features

1.4.1 High-Performance ARM920T Processor Core

The EP9312 features an advanced ARM920T processor design with an MMU that supports Linux®, Windows® CE, and many other embedded operating systems . T he ARM920T’s 32-bit m ic rocontroller arch ite c tu re, with a f iv e-stage pipeline , del ivers impr ess ive perfo rma nce at ve ry lo w po wer. The in clud ed 16 KByte instruction cache and 16 KByte data cache provide zero-cycle latency to the cu rrent pr ogram and d ata, or c an be lo cked to pro vide gu arantee d nolatency access to critical instructions and data. For applications with instruction memory size restrictions, the ARM920T’s compressed Thumb instruction set provides a space-efficient design that maximizes external instruction memory usage.

1.4.2 MaverickCrunch™ Coprocessor for Ultra-Fast Math Processing

The MaverickCrunch coprocessor is an advanced, mixed-mode math coprocessor that greatly accelerates the single and double-precision integer and floating-point processing capabilities of the ARM920T processor core. The engi ne simplifies th e end-user ’s programmin g task by using predefin ed coprocessor instructions, by utilizing standard ARM compiler tools, and by requiring just one debugger session for the entire system. Furthermore, the integrate d design provides a single instructio n stream and the ad vantage of zero latency for cached instructions. To emulate this capability, competitors’ solutions add a DSP to the system, which requires separate compiler /l ink er/debug ger tool sets. Th is additional D SP requires program m ers to write two separate programs and debug them simultaneously, which can result in frus t ration and cos t ly delays.

The single-cycle integer multiply-accumulate instruction in the MaverickCrunch coprocessor allows the EP9312 to offer unique speed and performa nce whi le enco ding d igital aud io and v ideo f ormats, pr ocessin g data via Ethernet, and performing other math-intensive computing and dataprocessing functio ns in c onsumer and industrial electronics.

1.4.3 MaverickKey™ Unique I D Secures Di gital Content and OEM Designs

Maverick Key uni que hardw are prog ramm ed IDs pro vide an ex cellen t solution to the growing concern over secure Web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditiona l software method s are quickly beco ming unreliable. T he MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs for DRM (D igital Rights Ma nagemen t) me c hanisms.

30 EP9312 User’s Manual - DS515UM2

+ 746 hidden pages

Cirrus Logic EP9312 User's Guide

EP9312 User’s Guide

About the EP9312 User’s Guide

How to Use this Guide

Preface

Related Documents from Cirrus Logic

Reference Document s

Notational Conventions

Table of Contents

List of Figures

List of Tables

1.1 Introduction

Chapter 1

1Introduction

1 1.2 EP9312 Features

1.3 EP9312 Applications

1 1.4 Overview of EP9312 Features

1.4.1 High-Performance ARM920T Processor Core

1.4.2 MaverickCrunch™ Coprocessor for Ultra-Fast Math Processing

1.4.3 MaverickKey™ Unique I D Secures Di gital Content and OEM Designs