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EP9307
User's Guide
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Cirrus Logic EP9307 User's Guide

EP9307 User’s Guide

http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
AUG ‘04
DS667UM1
Revision Date Changes
1 August 2004 Initial Release
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterizati on data is not yet avai lable. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the i nformati on contained in this document is accurate and reliabl e. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest versi on of r elevant information to verify, before placing orders, that informati on being relied on is current and complete. All products are sold subject to the terms and condi tions of sale supplied at the ti me of order acknowledgment, incl uding those pertai ning to warrant y, patent infringement, and limitatio n of liabili ty. No responsi bility is assumed by Cirr us for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Ci rrus and by furni shing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, tr ademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gi ves consent for copies to be made of the information onl y for use with in your organizat ion with respect to Ci rrus integra ted circuit s or other product s of Cirrus. This consent does not extend to other copying such as copying for general distr ibution, advertisi ng or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USI NG SEMI CONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANT­ED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PROD­UCTS OR OTHER CRITICAL APPLICATIONS ( INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). I NCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA­TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTH­ER AGENTS FROM ANY AND ALL LIABILITY, I NCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE I N CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
Microsoft and Windows are registered trademarks of Microsoft Corporation. MicrowireTM is a trademark of National Semiconductor Corp. Nati onal Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola is a registered trademark of Motorola, Inc. LINUX is a registered trademark of Linus Torval ds.
Copyright 2004 Cirrus Logic

About the EP9307 User’s Guide

This Guide describes the architecture, hardware, and operation of the Cirrus Logic EP9307. It is intended to be used in conjunction with the EP9307 Datasheet, which contains the full electrical specifications for the device.

How to Use this Guide

Subject Matter Location
AC’97 Chapter 22 - AC’97 Controller
ARM920T Processor
Boot ROM, Hardware and Software Chapter 3 - Boot ROM
Booting From SROM or SyncFlash Chapter 12 - SDRAM, SyncROM, and SyncFLASH Controller
Buses - AMBA, AHB, APB
Coprocessor Unit Chapter 2 - MaverickCrunch Coprocessor
DMA Controller Chapter 9 - DMA Controller
EP9307 Block Diagram
Ethernet Chapter 8 - 1/10/100 Mbps Ethernet LAN Controller
GPIO Chapter 27 - GPIO Interface
Graphics Accelerator Chapter 7 - Graphics Accelerator
HDLC
2
I
S Chapter 21 - I2S Controller
Infra-Red Interface Chapter 17 - IrDA
Interrupt Registers Chapter 5 - Vectored Interrupt Controller
Interrupts Chapter 5 - Vectored Interrupt Controller
IrDA Chapter 17 - IrDA
Key Pad Matrix Chapter 26 - Keypad Interface
LCD Interface
MAC Chapter 8 - 1/10/100 Mbps Ethernet LAN Controller
Chapter 13 - ARM920T Core and Advanced High-Speed Bus (AHB)
Chapter 13 - ARM920T Core and Advanced High-Speed Bus (AHB)
Chapter 13 - ARM920T Core and Advanced High-Speed Bus (AHB)
Chapter 14 - UART1 With HDLC and Modem Control Signals Chapter 16 - UART3 With HDLC Encoder
Chapter 6 - Raster Engine With Analog/LCD Integrated Timing and Interface

Preface

EP9307 User’s Manual - DS667UM1 3 Copyright 2004 Cirrus Logic
Subject Matter Location
Memory Map
Modem Chapter 14 - UART1 With HDLC and Modem Control Signals
Power Management Chapter 4 - System Controller
Programming Clocks Chapter 4 - System Controller
PWM Chapter 24 - Pulse Width Modulator
Raster Graphics
Real Time Clock Chapter 20 - Real Time Clock With Software Trim
Register List Chapter 1 - Introduction
RTC Chapter 20 - Real Time Clock With Software Trim
SDRAM Chapter 12 - SDRAM, SyncROM, and SyncFLASH Controller
Security Chapter 28 - Security
SMC Chapter 11 - Static Memory Controller
SSP Chapter 23 - Synchronous Serial Port
Static Memory Controller Chapter 11 - Static Memory Controller
System Configuration Chapter 4 - System Controller
System Registers Chapter 4 - System Controller
Timers Chapter 18 - Timers
Touch Screen Chapter 25 - Analog Touch Screen Interface
UART
USB Chapter 10 - Universal Serial Bus Host Controller
Vectored Interrupt Registers Chapter 5 - Vectored Interrupt Controller
Vectored Interrupts Chapter 5 - Vectored Interrupt Controller
Watchdog Timer Chapter 19 - Watchdog Timer
Chapter 13 - ARM920T Core and Advanced High-Speed Bus (AHB)
Chapter 6 - Raster Engine With Analog/LCD Integrated Timing and Interface
Chapter 14 - UART1 With HDLC and Modem Control Signals Chapter 15 - UART2 Chapter 16 - UART3 With HDLC Encoder

Related Documents from Cirrus Logic

1. EP9307 Data Sheet, Document Number - DS667

Reference Documents

1. ARM920T Technical Reference Manual
2. AMBA Specification (Rev. 2.0), ARM IHI 0011A, ARM Limited.
3. AHB Example AMBA System (Addendum 01), ARM DDI 0170A, ARM Limited.
Copyright 2004 Cirrus Logic
4. The coprocessor instruction assembler notation can be referenced from ARM programming manuals or the Quick Reference Card, document number ARM QRC 0001D.
5. The MAC engine is compliant with the requirements of ISO/IEC 8802-3 (1993), Sections 3 and 4.
6. OpenHCI - Open Host Controller interface Specification for USB, Release
1.0a; Compaq, Microsoft, National Semiconductor.
7. ARM Coprocessor Quick Reference Card, document number ARM QRC 0001D.
8. Information Technology, AT Attachment with Packet Interface - 5 (ATA/ATAPI-5) ANSI NCITS document T13 1321D, Revision 3, 29 February 2000
9. OpenHCI - Open Host Controller Interface Specification for USB, Release: 1.0a, Released - 09/14/99 2:33 PM
10. ARM PrimeCell PL190-Rel1v1 Revision 1.7 Technical Reference Manual DDI0181C
11. Audio Codec ‘97, Revision 2.3, April 2002, Intel Corporation

Notational Conventions

This document uses the following conventions:
• Internal and external Signal Names, and Pin Names use mixed upper and lower case alphanumeric, and are shown in bold font: RDLED.
• Register Bit Fields are named using upper and lower case alphanumeric: that is, SBOOT, LCSn1.
• Registers are named using mixed upper and lower case alphanumeric: that is, SysCfg or PxDDR. (Where there are multiple registers with similar names, a lower case “x” is used as a place holder. For example, in the PxDDR registers, x represents a letter between A and H, indicating the specific port being discussed.)
Caution: In the Internal Register Map in Table 13-7 on page 18-491, some
memory locations are listed as Reserved. These memory locations should not be used. Reading from these memory locations will yield invalid data. Writing to these memory locations may cause unpredictable results.
(An example register description is shown below. This description is used for the following examples.)
A specific bit may be specified in one of two ways:
EP9307 User’s Manual - DS667UM1 5 Copyright 2004 Cirrus Logic
By
register name[bit number]: SysCfg[29]
or by
register name.bit field[bit number]: SysCfg.REV[1]
Both of these representations refer to the same bit.
The following:
,
SysCfg[8]
, or
SysCfg.SBOOT
also refer to the same bit.
Hexidecimal numbers are referred to as
Binary numbers are referred to as
0000_0000b
0x0000_0000
.
.
Register Example
Note: This is only an example. For actual SysCfg register information, see “SysCfg” on
page 128.
SysCfg
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD SBOOT LCSn7 LCSn6 LASDO LEEDA LEECLK RSVD LCSn2 LCSn1
Address:
0x8093_009C - Read/Write, Software locked
Default:
0x0000_0000
Definition:
System Configuration Register. Provides various system configuration options.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
REV: Revision, reads chip Version number: 0 - Rev A, 1 - Rev B,
2 - Rev C, 3 - Rev D.
SBOOT: Serial Boot Flag. This bit is read-only.
1 hardware detected Serial Boot selection, 0 hardware detected Normal Boot.
Copyright 2004 Cirrus Logic
LCSn7, LCSn6: Latched version of CSn7 and CSn6 respectively. These
are used to define the external bus width for the boot code boot.
LASDO: Latched version of ASDO pin. Used to select synchronous
versus asynchronous boot device.
LEEDA: Latched version of EEDAT pin.
LEECLK: Define Internal or external boot:
1 Internal 0 External
LCSn2, LCSn1: Define Watchdog startup action:
0 0 Watchdog disabled, Reset duration disabled 0 1 Watchdog disabled, Reset duration active 1 0 Watchdog active, Reset duration disabled 1 1 Watchdog active, Reset duration active
EP9307 User’s Manual - DS667UM1 7 Copyright 2004 Cirrus Logic
This page intentionally blank.
Copyright 2004 Cirrus Logic

Table of Contents

Preface............................................................................................................. 3
About the EP9307 User’s Guide ............................................................................................................ 3
How to Use this Guide ...........................................................................................................................3
Related Documents from Cirrus Logic ...................................................................................................4
Reference Documents ...........................................................................................................................4
Notational Conventions ..........................................................................................................................5
Chapter 1 Introduction ............................................................................... 29
1.1 Introduction ...................................................................................................................................29
1.2 EP9307 Features ..........................................................................................................................30
1.3 EP9307 Applications .....................................................................................................................31
1.4 Overview of EP9307 Features ...................................................................................................... 32
1.4.1 High-Performance ARM920T Processor Core ....................................................................32
1.4.2 MaverickCrunch™ Coprocessor for Ultra-Fast Math Processing........................................32
1.4.3 MaverickKey™ Unique ID Secures Digital Content and OEM Designs ..............................32
1.4.4 Integrated Three-port USB 2.0 Full Speed Host with Transceivers.....................................33
1.4.5 Integrated Ethernet MAC Reduces BOM Costs ..................................................................33
1.4.6 8x8 Keypad Interface Reduces BOM Costs ........................................................................33
1.4.7 Multiple Booting Mechanisms Increase Flexibility ...............................................................33
1.4.8 Abundant General Purpose I/Os Build Flexible Systems ....................................................34
1.4.9 General-Purpose Memory Interface (SDRAM, SRAM, ROM and FLASH) .........................34
1.4.10 12-Bit Analog-to-Digital Converter (ADC) Provides an Integrated
Touch-Screen Interface or General ADC Functionality..............................................34
1.4.11 Graphics Accelerator .........................................................................................................34
Chapter 2 MaverickCrunch Coprocessor ................................................. 35
2.1 Introduction ...................................................................................................................................35
2.1.1 Features ..............................................................................................................................35
2.1.2 Operational Overview..........................................................................................................35
2.1.3 Pipelines and Latency .........................................................................................................37
2.1.4 Data Registers.....................................................................................................................37
2.1.5 Integer Saturation Arithmetic ...............................................................................................38
2.1.6 Comparisons .......................................................................................................................40
2.2 Programming Examples................................................................................................................41
2.2.1 Example 1............................................................................................................................41
2.2.1.1 Setup Code ................................................................................................................42
2.2.1.2 C Code.......................................................................................................................42
2.2.1.3 Accessing MaverickCrunch with ARM Coprocessor Instructions...............................42
2.2.1.4 MaverickCrunch Assembly Language Instructions ....................................................42
2.2.2 Example 2............................................................................................................................42
2.2.2.1 C Code.......................................................................................................................43
2.2.2.2 MaverickCrunch Assembly Language Instructions ....................................................43
2.3 DSPSC Register ...........................................................................................................................44
2.4 ARM Coprocessor Instruction Format........................................................................................... 47
2.5 Instruction Set for the MaverickCrunch Coprocessor....................................................................52
2.5.1 Load and Store Instructions.................................................................................................56
2.5.2 Move Instructions ................................................................................................................60
2.5.3 Accumulator and DSPSC Move Instructions .......................................................................64
EP9307 User’s Manual - DS667UM1 9 Copyright 2004 Cirrus Logic
2.5.4 Copy and Conversion Instructions ...................................................................................... 68
2.5.5 Shift Instructions.................................................................................................................. 72
2.5.6 Compare Instructions.......................................................................................................... 74
2.5.7 Floating Point Arithmetic Instructions.................................................................................. 76
2.5.8 Integer Arithmetic Instructions............................................................................................. 80
2.5.9 Accumulator Arithmetic Instructions.................................................................................... 84
Chapter 3 Boot ROM ...................................................................................87
3.1 Introduction ................................................................................................................................... 87
3.1.1 Boot ROM Hardware Operational Overview ....................................................................... 87
3.1.1.1 Memory Map.............................................................................................................. 87
3.1.2 Boot ROM Software Operational Overview......................................................................... 87
3.1.2.1 Image Header ............................................................................................................ 88
3.1.2.2 Boot Algorithm ........................................................................................................... 88
3.1.2.3 Flowchart................................................................................................................... 90
3.2 Boot Options................................................................................................................................. 91
3.2.1 UART Boot.......................................................................................................................... 91
3.2.2 SPI Boot.............................................................................................................................. 92
3.2.3 FLASH Boot ........................................................................................................................ 92
3.2.4 SDRAM or SyncFLASH Boot.............................................................................................. 93
3.2.5 Synchronous Memory Operation ........................................................................................ 93
Chapter 4 System Controller .....................................................................95
4.1 Introduction ................................................................................................................................... 95
4.1.1 System Startup.................................................................................................................... 95
4.1.2 System Reset...................................................................................................................... 95
4.1.3 Hardware Configuration Control.......................................................................................... 96
4.1.4 Software System Configuration Options ............................................................................. 98
4.1.5 Clock Control....................................................................................................................... 98
4.1.5.1 Oscillators and Programmable PLLs ......................................................................... 98
4.1.5.2 Bus and Peripheral Clock Generation ....................................................................... 99
4.1.5.3 Steps for Clock Configuration.................................................................................. 103
4.1.6 Power Management .......................................................................................................... 104
4.1.6.1 Clock Gatings ..........................................................................................................104
4.1.6.2 System Power States .............................................................................................. 104
4.1.7 Interrupt Generation .......................................................................................................... 106
4.2 Registers .................................................................................................................................... 108
Chapter 5 Vectored Interrupt Controller ................................................. 131
5.1 Introduction ................................................................................................................................. 131
5.1.1 Interrupt Priority................................................................................................................. 132
5.1.2 Interrupt Descriptions ........................................................................................................ 134
5.2 Registers .................................................................................................................................... 139
Chapter 6 Raster Engine With Analog/LCD Integrated Timing and
Interface ....................................................................................................... 149
6.1 Introduction ................................................................................................................................. 149
6.2 Features ..................................................................................................................................... 151
Copyright 2004 Cirrus Logic
6.3 Raster Engine Features Overview ..............................................................................................151
6.3.1 Hardware Blinking .............................................................................................................151
6.3.2 Color Look-Up Tables........................................................................................................152
6.3.3 Grayscale/Color Generation for Monochrome/Passive Low Color Displays ..................... 152
6.3.4 Frame Buffer Organization ................................................................................................152
6.3.5 Frame Buffer Memory Size................................................................................................154
6.3.6 Pulse Width Modulated Brightness....................................................................................154
6.3.7 Hardware Cursor ...............................................................................................................155
6.4 Functional Details........................................................................................................................156
6.4.1 VILOSATI (Video Image Line Output Scanner and Transfer Interface) ............................ 156
6.4.2 Video FIFO ........................................................................................................................ 158
6.4.3 Video Pixel MUX................................................................................................................158
6.4.4 Blink Function .................................................................................................................... 158
6.4.5 Color Look-Up-Tables .......................................................................................................159
6.4.6 Color RGB Mux .................................................................................................................160
6.4.7 Pixel Shift Logic................................................................................................................. 160
6.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays .......................164
6.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters ....................................................................165
6.4.8.2 VERT_CNT3, VERT_CNT4 Counters......................................................................165
6.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters................................................................165
6.4.8.4 HORZ_CNTx (pixel) timing ...................................................................................... 165
6.4.8.5 VERT_CNTx (line) timing.........................................................................................165
6.4.8.6 FRAME_CNTx timing...............................................................................................165
6.4.8.7 Grayscale Look-Up Table (GrySclLUT) ...................................................................166
6.4.8.8 GrySclLUT Timing Diagram .....................................................................................167
6.4.9 Hardware Cursor ...............................................................................................................176
6.4.9.1 Registers Used for Cursor........................................................................................ 178
6.4.10 Video Timing....................................................................................................................179
6.4.10.1 Setting the Video Memory Parameters ..................................................................182
6.4.10.2 PixelMode ..............................................................................................................184
6.4.11 Blink Logic .......................................................................................................................184
6.4.11.1 BlinkRate................................................................................................................184
6.4.11.2 Defining Blink Pixels...............................................................................................185
6.4.11.3 Types of Blinking.................................................................................................... 185
6.4.12 Color Mode Definition......................................................................................................187
6.4.12.1 Pixel Look-up Table ...............................................................................................187
6.4.12.2 Triple 8-bit Mode ....................................................................................................188
6.4.12.3 16-bit 565 Mode .....................................................................................................188
6.4.12.4 16-bit 555 Mode .....................................................................................................188
6.5 Registers.....................................................................................................................................189
Chapter 7 Graphics Accelerator.............................................................. 231
7.1 Overview .....................................................................................................................................231
7.2 Block Processing Modes.............................................................................................................231
7.2.1 Copy ..................................................................................................................................231
7.2.2 Transparency.....................................................................................................................232
7.2.3 Logical Mask...................................................................................................................... 232
EP9307 User’s Manual - DS667UM1 11 Copyright 2004 Cirrus Logic
7.2.3.1 Logical Destination .................................................................................................. 232
7.2.3.2 Operation Precedence............................................................................................. 232
7.2.4 Remapping........................................................................................................................ 233
7.2.5 Block Fills .......................................................................................................................... 233
7.2.6 Packed Memory Transfer.................................................................................................. 233
7.3 Line Draws.................................................................................................................................. 233
7.3.1 Breshenham Line Draws................................................................................................... 234
7.3.2 Pixel Step Line Draws....................................................................................................... 234
7.4 Memory Organization for Graphics Accelerator ......................................................................... 234
7.4.1 Memory Organization for 1 Bit Per Pixel (bpp)................................................................. 235
7.4.2 Memory Organization for 4 Bit Per Pixel ........................................................................... 235
7.4.3 Memory Organization for 8 Bit Per Pixel ........................................................................... 235
7.4.4 Memory Organization for 24 Bit Per Pixel ......................................................................... 237
7.5 Register Programming................................................................................................................ 238
7.6 Word Count ................................................................................................................................ 238
7.6.1 Example: 8 BPP mode ...................................................................................................... 239
7.6.2 Example: 24 BPP (packed) mode..................................................................................... 239
7.7 Pixel End and Start..................................................................................................................... 240
7.7.1 4 BPP mode ...................................................................................................................... 240
7.7.1.1 4 BPP Word Layout ................................................................................................. 240
7.7.1.2 8 BPP Word Layout ................................................................................................. 241
7.7.1.3 16 BPP WORD Layout ............................................................................................ 241
7.7.1.4 24 BPP mode .......................................................................................................... 241
7.8 Register Usage........................................................................................................................... 242
7.8.1 Line (Bresenham’s Algorithm)........................................................................................... 242
7.8.2 DX/DY Line Draw Function ............................................................................................... 244
7.8.3 Block Fill............................................................................................................................ 245
7.8.4 Block Copy........................................................................................................................ 246
7.8.4.1 Source Memory Setup............................................................................................. 246
7.8.4.2 Destination Memory Setup ...................................................................................... 246
7.9 Registers ................................................................................................................................... 248
Chapter 8 1/10/100 Mbps Ethernet LAN Controller ................................ 263
8.1 Introduction ................................................................................................................................. 263
8.1.1 Detailed Description.......................................................................................................... 263
8.1.1.1 Host Interface and Descriptor Processor................................................................. 263
8.1.1.2 Reset and Initialization ............................................................................................ 264
8.1.1.3 Powerdown Modes .................................................................................................. 264
8.1.1.4 Address Space ........................................................................................................ 265
8.1.2 MAC Engine...................................................................................................................... 265
8.1.2.1 Data Encapsulation ................................................................................................. 265
8.1.3 Packet Transmission Process........................................................................................... 266
8.1.3.1 Carrier Deference .................................................................................................... 267
8.1.4 Transmit Back-Off ............................................................................................................. 269
8.1.4.1 Transmission ...........................................................................................................269
8.1.4.2 The FCS Field ......................................................................................................... 270
8.1.4.3 Bit Order .................................................................................................................. 270
8.1.4.4 Destination Address (DA) Filter ............................................................................... 270
Copyright 2004 Cirrus Logic
8.1.4.5 Perfect Address Filtering..........................................................................................270
8.1.4.6 Hash Filter................................................................................................................271
8.1.4.7 Flow Control .............................................................................................................272
8.1.4.8 Receive Flow Control...............................................................................................272
8.1.4.9 Transmit Flow Control ..............................................................................................273
8.1.4.10 Rx Missed and Tx Collision Counters....................................................................273
8.1.4.11 Accessing the MII...................................................................................................274
8.2 Descriptor Processor...................................................................................................................275
8.2.1 Receive Descriptor Processor Queues .............................................................................275
8.2.2 Receive Descriptor Queue ................................................................................................276
8.2.3 Receive Status Queue.......................................................................................................278
8.2.3.1 Receive Status Format.............................................................................................281
8.2.3.2 Receive Flow............................................................................................................284
8.2.3.3 Receive Errors .........................................................................................................285
8.2.3.4 Receive Descriptor Data/Status Flow ......................................................................286
8.2.3.5 Receive Descriptor Example....................................................................................287
8.2.3.6 Receive Frame Pre-Processing ...............................................................................287
8.2.3.7 Transmit Descriptor Processor.................................................................................288
8.2.3.8 Transmit Descriptor Queue ......................................................................................288
8.2.3.9 Transmit Descriptor Format .....................................................................................291
8.2.3.10 Transmit Status Queue ..........................................................................................292
8.2.3.11 Transmit Status Format..........................................................................................294
8.2.3.12 Transmit Flow.........................................................................................................296
8.2.3.13 Transmit Errors ......................................................................................................297
8.2.3.14 Transmit Descriptor Data/Status Flow ...................................................................298
8.2.4 Interrupts ...........................................................................................................................299
8.2.4.1 Interrupt Processing.................................................................................................299
8.2.5 Initialization........................................................................................................................299
8.2.5.1 Interrupt Processing.................................................................................................300
8.2.5.2 Receive Queue Processing......................................................................................300
8.2.5.3 Transmit Queue Processing.....................................................................................300
8.2.5.4 Other Processing .....................................................................................................301
8.2.5.5 Transmit Restart Process.........................................................................................301
8.3 Registers.....................................................................................................................................303
Chapter 9 DMA Controller........................................................................ 357
9.1 Introduction .................................................................................................................................357
9.1.1 DMA Features List.............................................................................................................357
9.1.2 Managing Data Transfers Using a DMA Channel .............................................................358
9.1.3 DMA Operations ................................................................................................................359
9.1.3.1 Memory-to-Memory Channels..................................................................................360
9.1.3.2 Memory-to-Peripheral Channels ..............................................................................360
9.1.4 Internal M2P or P2M AHB Master Interface Functional Description..................................361
9.1.5 M2M AHB Master Interface Functional Description...........................................................362
9.1.5.1 Software Trigger Mode.............................................................................................362
9.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP) and for External
Peripherals without Handshaking Signals .........................................................................362
EP9307 User’s Manual - DS667UM1 13 Copyright 2004 Cirrus Logic
9.1.5.3 Hardware Trigger Mode for External Peripherals with Handshaking Signals .......... 362
9.1.6 AHB Slave Interface Limitations........................................................................................ 363
9.1.7 Interrupt Interface.............................................................................................................. 363
9.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description.................................... 363
9.1.9 Internal M2P/P2M DMA Functional Description................................................................ 364
9.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine.................................. 364
9.1.9.2 Data Transfer Initiation and Termination ................................................................. 366
9.1.10 M2M DMA Functional Description................................................................................... 367
9.1.10.1 M2M DMA Control Finite State Machine ............................................................... 367
9.1.10.2 M2M Buffer Control Finite State Machine.............................................................. 369
9.1.10.3 Data Transfer Initiation .......................................................................................... 371
9.1.10.4 Data Transfer Termination..................................................................................... 373
9.1.10.5 Memory Block Transfer ......................................................................................... 374
9.1.10.6 Bandwidth Control ................................................................................................. 374
9.1.10.7 External Peripheral DMA Request (DREQ) Mode ................................................. 374
9.1.11 DMA Data Transfer Size Determination.......................................................................... 376
9.1.11.1 Software Initiated M2M and M2P/P2M Transfers.................................................. 376
9.1.11.2 Hardware Initiated M2M Transfers ........................................................................ 376
9.1.12 Buffer Descriptors ........................................................................................................... 377
9.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors ................................................ 377
9.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors................................................. 377
9.1.12.3 M2M Channel Buffer Descriptors........................................................................... 377
9.1.13 Bus Arbitration................................................................................................................. 377
9.2 Registers .................................................................................................................................... 379
9.2.1 DMA Controller Memory Map............................................................................................ 379
9.2.2 Internal M2P/P2M Channel Register Map......................................................................... 379
Chapter 10 Universal Serial Bus Host Controller .................................. 407
10.1 Introduction............................................................................................................................... 407
10.1.1 Features .......................................................................................................................... 407
10.2 Overview................................................................................................................................... 407
10.2.1 Data Transfer Types ....................................................................................................... 408
10.2.2 Host Controller Interface ................................................................................................. 409
10.2.2.1 Communication Channels ..................................................................................... 409
10.2.2.2 Data Structures...................................................................................................... 410
10.2.3 Host Controller Driver Responsibilities............................................................................ 412
10.2.3.1 Host Controller Management................................................................................. 412
10.2.3.2 Bandwidth Allocation ............................................................................................. 412
10.2.3.3 List Management ................................................................................................... 413
10.2.3.4 Root Hub ............................................................................................................... 414
10.2.4 Host Controller Responsibilities ...................................................................................... 414
10.2.4.1 USB States............................................................................................................414
10.2.4.2 Frame management .............................................................................................. 414
10.2.4.3 List Processing ...................................................................................................... 414
10.2.5 USB Host Controller Blocks ............................................................................................ 415
10.2.5.1 AHB Slave .............................................................................................................415
10.2.5.2 AHB Master ........................................................................................................... 415
Copyright 2004 Cirrus Logic
10.2.5.3 HCI Slave Block .....................................................................................................415
10.2.5.4 HCI Master Block ...................................................................................................416
10.2.5.5 USB State Control..................................................................................................416
10.2.5.6 Data FIFO ..............................................................................................................416
10.2.5.7 List Processor ........................................................................................................416
10.2.5.8 Root Hub and Host SIE..........................................................................................416
10.3 Registers...................................................................................................................................417
Chapter 11 Static Memory Controller ..................................................... 445
11.1 Introduction ...............................................................................................................................445
11.2 Static Memory Controller Operation..........................................................................................446
11.3 Byte Lane Write / Read Control ................................................................................................448
11.4 Registers...................................................................................................................................450
Chapter 12 SDRAM, SyncROM, and SyncFLASH Controller................ 453
12.1 Introduction ...............................................................................................................................453
12.1.1 Booting (from SROM or SyncFLASH) .............................................................................453
12.1.1.1 Address Pin Usage ................................................................................................454
12.1.1.2 SDRAM Initialization ..............................................................................................456
12.1.1.3 Programming External Device Mode Register .......................................................457
12.1.1.4 SDRAM Self Refresh .............................................................................................460
12.1.1.5 SROM and SyncFlash............................................................................................460
12.1.1.6 External Synchronous Memory System .................................................................461
12.2 Registers...................................................................................................................................465
Chapter 13 ARM920T Core and Advanced High-Speed Bus (AHB) ..... 473
13.1 Introduction ...............................................................................................................................473
13.2 Overview: ARM920T Processor Core.......................................................................................473
13.2.1 Features ..........................................................................................................................473
13.2.2 Block Diagram .................................................................................................................474
13.2.3 Operations ....................................................................................................................... 474
13.2.3.1 ARM9TDMI Core....................................................................................................475
13.2.3.2 Memory Management Unit.....................................................................................476
13.2.3.3 Cache and Write Buffer..........................................................................................477
13.2.4 Coprocessor Interface .....................................................................................................478
13.2.5 AMBA AHB Bus Interface Overview................................................................................479
13.2.6 EP9307 AHB Implementation Details..............................................................................480
13.2.7 Memory and Bus Access Errors ......................................................................................481
13.2.8 Bus Arbitration.................................................................................................................482
13.2.8.1 Main AHB Bus Arbiter............................................................................................482
13.2.8.2 SDRAM Slave Arbiter.............................................................................................483
13.2.8.3 EBI Bus Arbiter.......................................................................................................483
13.3 AHB Decoder ............................................................................................................................483
13.3.1 AHB Bus Slave ................................................................................................................484
13.3.2 AHB to APB Bridge..........................................................................................................484
13.3.2.1 Function and Operation of APB Bridge ..................................................................484
13.3.3 APB Bus Slave ................................................................................................................485
13.3.4 Register Definitions .........................................................................................................485
EP9307 User’s Manual - DS667UM1 15 Copyright 2004 Cirrus Logic
13.3.5 Memory Map ................................................................................................................... 489
13.3.6 Internal Register Map...................................................................................................... 490
13.3.6.1 Memory Access Rules........................................................................................... 490
Chapter 14 UART1 With HDLC and Modem Control Signals ................ 505
14.1 Introduction............................................................................................................................... 505
14.2 UART Overview........................................................................................................................ 505
14.2.1 UART Functional Description.......................................................................................... 506
14.2.1.1 AMBA APB Interface ............................................................................................. 506
14.2.1.2 DMA Block.............................................................................................................506
14.2.1.3 Register Block ....................................................................................................... 507
14.2.1.4 Baud Rate Generator ............................................................................................ 508
14.2.1.5 Transmit FIFO ....................................................................................................... 508
14.2.1.6 Receive FIFO ........................................................................................................ 508
14.2.1.7 Transmit Logic ....................................................................................................... 508
14.2.1.8 Receive Logic ........................................................................................................ 508
14.2.1.9 Interrupt Generation Logic ..................................................................................... 508
14.2.1.10 Synchronizing Registers and Logic ..................................................................... 509
14.2.2 UART Operation.............................................................................................................. 509
14.2.2.1 Error Bits................................................................................................................ 510
14.2.2.2 Disabling the FIFOs............................................................................................... 510
14.2.2.3 System/diagnostic Loopback Testing .................................................................... 510
14.2.2.4 UART Character Frame......................................................................................... 510
14.2.3 Interrupts......................................................................................................................... 511
14.2.3.1 UARTMSINTR....................................................................................................... 511
14.2.3.2 UARTRXINTR ....................................................................................................... 511
14.2.3.3 UARTTXINTR........................................................................................................ 512
14.2.3.4 UARTRTINTR........................................................................................................ 512
14.2.3.5 UARTINTR ............................................................................................................ 512
14.3 Modem...................................................................................................................................... 512
14.4 HDLC........................................................................................................................................ 513
14.4.1 Overview of HDLC Modes............................................................................................... 513
14.4.2 Selecting HDLC Modes................................................................................................... 514
14.4.3 HDLC Transmit ............................................................................................................... 515
14.4.4 HDLC Receive ................................................................................................................ 516
14.4.5 CRCs............................................................................................................................... 517
14.4.6 Address Matching ........................................................................................................... 517
14.4.7 Aborts.............................................................................................................................. 518
14.4.8 DMA ................................................................................................................................ 518
14.4.9 Writing Configuration Registers ...................................................................................... 519
14.5 UART1 Package Dependency..................................................................................................519
14.5.1 Clocking Requirements ...................................................................................................520
14.5.2 Bus Bandwidth Requirements......................................................................................... 520
14.6 Registers .................................................................................................................................. 522
Chapter 15 UART2 .................................................................................... 543
15.1 Introduction............................................................................................................................... 543
15.2 IrDA SIR Block.......................................................................................................................... 543
Copyright 2004 Cirrus Logic
15.2.1 IrDA SIR Encoder/decoder Functional Description .........................................................543
15.2.1.1 IrDA SIR Transmit Encoder....................................................................................544
15.2.1.2 IrDA SIR Receive Decoder ....................................................................................544
15.2.2 IrDA SIR Operation..........................................................................................................545
15.2.2.1 System/diagnostic Loopback Testing.....................................................................546
15.2.3 IrDA Data Modulation ......................................................................................................546
15.2.4 Enabling Infrared (Ir) Modes ............................................................................................547
15.3 UART2 Package Dependency ..................................................................................................547
15.3.1 Clocking Requirements ...................................................................................................547
15.3.2 Bus Bandwidth Requirements .........................................................................................548
15.4 Registers...................................................................................................................................549
Chapter 16 UART3 With HDLC Encoder ................................................. 561
16.1 Introduction ...............................................................................................................................561
16.2 Implementation Details..............................................................................................................561
16.2.1 UART3 Package Dependency.........................................................................................561
16.2.2 Clocking Requirements ...................................................................................................562
16.2.3 Bus Bandwidth Requirements .........................................................................................562
16.3 Registers...................................................................................................................................563
Chapter 17 IrDA ........................................................................................ 581
17.1 Introduction ...............................................................................................................................581
17.2 IrDA Interfaces ..........................................................................................................................581
17.3 Shared IrDA Interface Feature..................................................................................................582
17.3.1 Overview..........................................................................................................................582
17.3.2 Functional Description .....................................................................................................582
17.3.2.1 General Configuration ............................................................................................583
17.3.2.2 Transmitting Data................................................................................................... 583
17.3.2.3 Receiving Data.......................................................................................................586
17.3.2.4 Special Conditions .................................................................................................588
17.3.3 Control Information Buffering...........................................................................................588
17.4 Medium IrDA Specific Features ................................................................................................589
17.4.1 Introduction ......................................................................................................................589
17.4.1.1 Bit Encoding...........................................................................................................589
17.4.1.2 Frame Format ........................................................................................................589
17.4.2 Functional Description .....................................................................................................591
17.4.2.1 Baud Rate Generation ...........................................................................................591
17.4.2.2 Receive Operation .................................................................................................592
17.4.2.3 Transmit Operation ................................................................................................593
17.5 Fast IrDA Specific Features ......................................................................................................594
17.5.1 Introduction ......................................................................................................................594
17.5.1.1 4PPM Modulation...................................................................................................594
17.5.1.2 4.0 Mbps FIR Frame Format..................................................................................596
17.5.2 Functional Description .....................................................................................................597
17.5.2.1 Baud Rate Generation ...........................................................................................598
17.5.2.2 Receive Operation .................................................................................................598
17.5.2.3 Transmit Operation ................................................................................................600
17.5.3 IrDA Connectivity.............................................................................................................601
EP9307 User’s Manual - DS667UM1 17 Copyright 2004 Cirrus Logic
17.5.4 IrDA Integration Information............................................................................................602
17.5.4.1 Enabling Infrared Modes ....................................................................................... 602
17.5.4.2 Clocking Requirements ......................................................................................... 602
17.5.4.3 Bus Bandwidth Requirements ............................................................................... 603
17.6 Registers .................................................................................................................................. 604
Chapter 18 Timers..................................................................................... 619
18.1 Introduction............................................................................................................................... 619
18.1.1 Features .......................................................................................................................... 619
18.1.2 16 and 32-bit Timer Operation ........................................................................................ 619
18.1.2.1 Free Running Mode ............................................................................................... 620
18.1.2.2 Pre-load Mode ....................................................................................................... 620
18.1.3 40-bit Timer Operation .................................................................................................... 620
18.2 Registers .................................................................................................................................. 621
Chapter 19 Watchdog Timer .................................................................... 627
19.1 Introduction............................................................................................................................... 627
19.1.1 Watchdog Activation ....................................................................................................... 628
19.1.2 Clocking Requirements ...................................................................................................628
19.1.3 Reset Requirements ....................................................................................................... 628
19.1.4 Watchdog Status............................................................................................................. 628
19.2 Registers .................................................................................................................................. 630
Chapter 20 Real Time Clock With Software Trim................................... 633
20.1 Introduction............................................................................................................................... 633
20.1.1 Software Trim.................................................................................................................. 633
20.1.1.1 Software Compensation ........................................................................................ 634
20.1.1.2 Oscillator Frequency Calibration............................................................................ 634
20.1.1.3 RTCSWComp Value Determination ...................................................................... 634
20.1.1.4 Example - Measured Value Split Into Integer and Fractional Component............. 635
20.1.1.5 Maximum Error Calculation vs. Real Time Clock Accuracy................................... 635
20.1.1.6 Real-Time Interrupt................................................................................................ 636
20.1.2 Reset Control.................................................................................................................. 636
20.2 Registers .................................................................................................................................. 637
Chapter 21 I2S Controller ......................................................................... 641
21.1 Introduction............................................................................................................................... 641
2
21.2 I
21.3 I
21.4 I
21.5 I
21.6 I
21.7 Interrupts .................................................................................................................................. 653
21.8 Registers .................................................................................................................................. 655
S Transmitter Channel Overview ........................................................................................... 643
2
S Receiver Channel Overview ............................................................................................... 647
21.3.1 Receiver FIFO’s .............................................................................................................. 647
2
S Configuration and Status Registers.................................................................................... 649
2
S Master Clock Generation.................................................................................................... 649
2
S Bit Clock Rate Generation .................................................................................................. 651
21.6.1 Example of the Bit Clock Generation. ............................................................................. 652
21.6.2 Example of Right Justified LRCK format......................................................................... 652
2
21.8.1 I
21.8.2 I
S TX Registers ............................................................................................................. 655
2
S RX Registers............................................................................................................. 662
Copyright 2004 Cirrus Logic
21.8.3 I2S Configuration and Status Registers...........................................................................668
21.8.4 I
2
S Global Status Registers.............................................................................................672
Chapter 22 AC’97 Controller.................................................................... 675
22.1 Introduction ...............................................................................................................................675
22.2 Interrupts...................................................................................................................................677
22.2.1 Channel Interrupts ...........................................................................................................677
22.2.1.1 RIS .........................................................................................................................677
22.2.1.2 TIS..........................................................................................................................678
22.2.1.3 RTIS.......................................................................................................................678
22.2.1.4 TCIS.......................................................................................................................678
22.2.2 Global Interrupts..............................................................................................................678
22.2.2.1 CODECREADY......................................................................................................678
22.2.2.2 WINT......................................................................................................................678
22.2.2.3 GPIOINT ................................................................................................................679
22.2.2.4 GPIOTXCOMPLETE..............................................................................................679
22.2.2.5 SLOT2INT..............................................................................................................679
22.2.2.6 SLOT1TXCOMPLETE ...........................................................................................679
22.2.2.7 SLOT2TXCOMPLETE ...........................................................................................679
22.3 System Loopback Testing .........................................................................................................679
22.4 Registers...................................................................................................................................680
Chapter 23 Synchronous Serial Port ...................................................... 699
23.1 Introduction ...............................................................................................................................699
23.2 Features....................................................................................................................................699
23.3 SSP Functionality......................................................................................................................700
23.4 SSP Pin Multiplex......................................................................................................................700
23.5 Configuring the SSP..................................................................................................................700
23.5.1 Enabling SSP Operation..................................................................................................701
23.5.2 Master/Slave Mode..........................................................................................................701
23.5.3 Serial Bit Rate Generation...............................................................................................701
23.5.4 Frame Format.................................................................................................................701
23.5.5 Texas Instruments® Synchronous Serial Frame Format ................................................702
23.5.6 Motorola® SPI Frame Format .........................................................................................703
23.5.6.1 SPO Clock Polarity.................................................................................................703
23.5.6.2 SPH Clock Phase...................................................................................................703
23.5.7 Motorola SPI Format with SPO=0, SPH=0......................................................................703
23.5.8 Motorola SPI Format with SPO=0, SPH=1.....................................................................705
23.5.9 Motorola SPI Format with SPO=1, SPH=0......................................................................706
23.5.10 Motorola SPI Format with SPO=1, SPH=1....................................................................708
23.5.11 National Semiconductor® Microwire® Frame Format ...................................................709
23.5.11.1 Setup and Hold Time Requirements on SFRMIN with
Respect to SCLKIN in Microwire Mode.............................................................................711
23.6 Registers...................................................................................................................................712
Chapter 24 Pulse Width Modulator ......................................................... 719
24.1 Introduction ...............................................................................................................................719
24.2 Theory of Operation ..................................................................................................................719
EP9307 User’s Manual - DS667UM1 19 Copyright 2004 Cirrus Logic
24.2.1 PWM Programming Examples........................................................................................ 720
24.2.1.1 Example................................................................................................................. 720
24.2.1.2 Static Programming (PWM is Not Running) Example ........................................... 720
24.2.1.3 Dynamic Programming (PWM is Running) Example............................................. 721
24.2.2 Programming Rules ........................................................................................................ 721
24.3 Registers .................................................................................................................................. 722
Chapter 25 Analog Touch Screen Interface ........................................... 727
25.1 Introduction............................................................................................................................... 727
25.2 Touch Screen Controller Operation.......................................................................................... 727
25.2.1 Touch Screen Scanning: Four-wire and Eight-wire Operation ........................................ 730
25.2.2 Five-wire and Seven-wire Operation............................................................................... 737
25.2.3 Direct Operation.............................................................................................................. 740
25.2.4 Measuring Analog Input with the Touch Screen Controls Disabled ................................ 742
25.2.5 Measuring Touch Screen Resistance ............................................................................. 744
25.2.6 Polled and Interrupt-Driven Modes ................................................................................. 746
25.2.7 Touch Screen Package Dependency.............................................................................. 746
25.3 Registers .................................................................................................................................. 747
Chapter 26 Keypad Interface ................................................................... 755
26.1 Introduction............................................................................................................................... 755
26.2 Theory of Operation.................................................................................................................. 756
26.2.1 Apparent Key Detection ..................................................................................................757
26.2.2 Scan and Debounce........................................................................................................ 759
26.2.3 Interrupt Generation ........................................................................................................ 760
26.2.4 Low Power Mode ............................................................................................................ 760
26.2.5 Three-key Reset.............................................................................................................. 761
26.3 Registers .................................................................................................................................. 762
Chapter 27 GPIO Interface ....................................................................... 767
27.1 Introduction............................................................................................................................... 767
27.1.1 Memory Map ................................................................................................................... 768
27.1.2 Functional Description..................................................................................................... 769
27.1.3 Reset............................................................................................................................... 771
27.1.4 GPIO Pin Map................................................................................................................. 771
27.2 Registers .................................................................................................................................. 773
Chapter 28 Security .................................................................................. 781
28.1 Introduction............................................................................................................................... 781
28.2 Features ................................................................................................................................... 781
28.3 Contact Information .................................................................................................................. 781
28.4 Registers .................................................................................................................................. 782
Chapter 29 Glossary ................................................................................. 783
Copyright 2004 Cirrus Logic

List of Figures

Figure 1-1. EP9307 Block Diagram .................................................................................. 29
Figure 3-1. Flow Chart of Boot ROM Software ................................................................ 90
Figure 3-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices ............................... 93
Figure 4-1. Phase Locked Loop (PLL) Structure .............................................................. 99
Figure 4-2. EP9307 Clock Generation System.................................................................. 100
Figure 4-3. Bus Clock Generation ................................................................................... 101
Figure 4-4. EP9307 Power States and Transitions ......................................................... 105
Figure 5-1. Vectored Interrupt Controller Block Diagram ................................................ 132
Figure 6-1. Raster Engine Block Diagram ...................................................................... 156
Figure 6-2. Video Buffer Diagram ................................................................................... 157
Figure 6-3. Graphics Matrix for 50% Duty Cycle ............................................................. 170
Figure 6-4. Sample Matrix Causing Flickering ................................................................ 171
Figure 6-5. Sample Matrix That Avoids Flickering .......................................................... 172
Figure 6-6. Programming for One-third Luminous Intensity ............................................ 173
Figure 6-7. Creating Bit Patterns that Move to the Right ................................................ 174
Figure 6-8. Three and Four Count Axis .......................................................................... 175
Figure 6-9. Progressive/Dual Scan Video Signals .......................................................... 181
Figure 6-10. Interlaced Video Signals ............................................................................... 182
Figure 8-1. Block Diagram ................................................................................................ 263
Figure 8-2. Ethernet Frame / Packet Format (Type II only) ............................................... 266
Figure 8-3. Packet Transmission Process ......................................................................... 267
Figure 8-4. Carrier Deference State Diagram .................................................................... 268
Figure 8-5. Data Bit Transmission Order .......................................................................... 270
Figure 8-6. CRC Logic .................................................................................................... 271
Figure 8-7. Receive Descriptor Format and Data Fragments ......................................... 277
Figure 8-8. Receive Status Queue .................................................................................. 280
Figure 8-9. Receive Flow Diagram ................................................................................. 284
Figure 8-10. Receive Descriptor Data/Status Flow ........................................................... 286
Figure 8-11. Receive Descriptor Example ........................................................................ 287
Figure 8-12. Receive Frame Pre-processing .................................................................. 288
Figure 8-13. Transmit Descriptor Format and Data Fragments ........................................ 290
Figure 8-14. Multiple Fragments Per Transmit Frame ...................................................... 290
Figure 8-15. Transmit Status Queue ............................................................................... 293
Figure 8-16. Transmit Flow Diagram .............................................................................. 296
Figure 8-17. Transmit Descriptor Data/Status Flow ........................................................ 298
Figure 9-1. DMA M2P/P2M Finite State Machine.............................................................. 364
Figure 9-2. M2M DMA Control Finite State Machine ......................................................... 367
Figure 9-3. M2M DMA Buffer Finite State Machine .......................................................... 369
Figure 9-4. Edge-triggered DREQ Mode ........................................................................... 375
Figure 10-1. USB Focus Areas .......................................................................................... 408
Figure 10-2. Communication Channels ............................................................................ 409
Figure 10-3. Typical List Structure .................................................................................... 410
Figure 10-4. Interrupt Endpoint Descriptor Structure ........................................................ 411
EP9307 User’s Manual - DS667UM1 21 Copyright 2004 Cirrus Logic
Figure 10-5. Sample Interrupt Endpoint Schedule ............................................................ 412
Figure 10-6. Frame Bandwidth Allocation ......................................................................... 413
Figure 10-7. USB Host Controller Block Diagram .............................................................. 415
Figure 11-1. 32-bit read, 32-bit Memory, 0 wait cycles, RBLE = 1,
WAITn Inactive ................................................................................................................ 446
Figure 11-2. 32-bit write, 32-bit Memory, 0 wait cycles, RBLE = 1,
WAITn Inactive ............................................................................................................... 447
Figure 11-3. 16-bit read, 16-bit Memory, RBLE = 1, WAITn Active ................................... 447
Figure 11-4. 16-bit write, 16-bit Memory, RBLE = 1, WAITn Active................................... 448
Figure 13-1. ARM920T Block Diagram ............................................................................. 474
Figure 13-2. Typical AMBA AHB System ........................................................................ 479
Figure 13-3. EP9307 Main Data Paths .............................................................................. 480
Figure 14-1. UART Block Diagram .................................................................................... 507
Figure 14-2. UART Character Frame ................................................................................ 511
Figure 15-1. IrDA SIR Encoder/decoder Block Diagram ................................................... 544
Figure 15-2. IrDA Data Modulation (3/16) ......................................................................... 546
Figure 17-1. RZ1/NRZ Bit Encoding Example .................................................................. 589
Figure 17-2. 4PPM Modulation Encoding ......................................................................... 595
Figure 17-3. 4PPM Modulation Example .......................................................................... 595
Figure 17-4. IrDA (4.0 Mbps) Transmission Format........................................................... 596
2
Figure 21-1. Architectural Overview of the I
S Controller ............................................... 642
Figure 21-2. Transmitter FIFO’s ...................................................................................... 644
Figure 21-3. Bit Clock Generation Example ................................................................. 652
Figure 21-4. Frame Format for Right Justified Data .................................................... 653
Figure 23-1. Texas Instruments Synchronous Serial Frame Format (Single Transfer) ..... 702
Figure 23-2. TI Synchronous Serial Frame Format (Continuous Transfer)........................ 703
Figure 23-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0....... 704
Figure 23-4. Motorola SPI Frame Format (Continuous Transfer)
with SPO=0 and SPH=0 .................................................................................................. 704
Figure 23-5. Motorola SPI Frame Format with SPO=0 and SPH=1................................... 705
Figure 23-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0....... 706
Figure 23-7. Motorola SPI Frame Format (Continuous Transfer)
with SPO=1 and SPH=0 .................................................................................................. 707
Figure 23-8. Motorola SPI Frame Format with SPO=1 and SPH=1................................... 708
Figure 23-9. Microwire Frame Format (Single Transfer).................................................... 709
Figure 23-10. Microwire Frame Format (Continuous Transfers)........................................ 710
Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements.... 711
Figure 24-1. PWM_INV Example ....................................................................................... 725
Figure 25-1. Different Types of Touch Screens ................................................................ 728
Figure 25-2. 8-Wire Resistive Interface Switching Diagram.............................................. 732
Figure 25-3. 4-Wire Analog Resistive Interface Switching Diagram .................................. 733
Figure 25-4. Analog Resistive Touch Screen Scan Flow Chart ........................................ 736
Figure 25-5. 5-Wire Analog Resistive Interface Switching Diagram ................................. 738
Figure 25-6. 5-Wire Feedback (7-Wire) Analog Resistive Interface Switching Diagram ... 739
Copyright 2004 Cirrus Logic
Figure 25-7. Power Down Detect Press Switching Diagram ............................................. 741
Figure 25-8. Other Switching Diagrams ............................................................................ 743
Figure 25-9. Measure Resistance Switching Diagram ...................................................... 745
Figure 26-1. Key Array Block Diagram ......................................................................... 755
Figure 26-2. 8 x 8 Key Array Diagram ............................................................................ 757
Figure 26-3. Apparent Key 00H .................................................................................... 759
Figure 27-1. System Level GPIO Connectivity ............................................................... 768
Figure 27-2. Signal Connections Within the Standard GPIO Port Control Logic
(Ports C, D, E, G, H) ..................................................................................................... 770
Figure 27-3. Signal Connections Within the Enhanced GPIO Port Control Logic
(Ports A, B, F) .............................................................................................................. 771
EP9307 User’s Manual - DS667UM1 23 Copyright 2004 Cirrus Logic

List of Tables

Table 2-1: Saturation for Non-accumulator Instructions ...................................................... 39
Table 2-2: Accumulator Bit Formats for Saturation.............................................................. 39
Table 2-3: Comparison Relationships and Their Results ................................................... 41
Table 2-4: ARM Condition Codes and Crunch Compare Results ....................................... 41
Table 2-5: Condition Code Definitions ................................................................................ 49
Table 2-6: LDC/STC Opcode Map ...................................................................................... 50
Table 2-7: CDP Opcode Map .............................................................................................. 51
Table 2-8: MCR Opcode Map .......................................................................................... 51
Table 2-9: MRC Opcode Map ............................................................................................. 51
Table 2-10: MaverickCrunch Instruction Set ...................................................................... 52
Table 2-11: Mnemonic Codes.............................................................................................. 56
Table 2-12: Mnemonic Codes ........................................................................................... 57
Table 3-1: Boot Configuration Options (Normal Boot) ........................................................ 91
Table 4-1: Boot Configuration Options ............................................................................... 97
Table 4-2: Clock Speeds and Sources ........................................................................... 103
Table 4-3: Peripherals with PCLK gating ........................................................................ 104
Table 4-4: Syscon Register List ....................................................................................... 108
Table 4-5: Audio Interfaces Pin Assignment ..................................................................... 121
Table 5-1: Interrupt Configuration...................................................................................... 133
Table 5-2: VICx Register Summary ................................................................................... 139
Table 6-1: Raster Engine Video Mode Output Examples ............................................... 150
Table 6-2: Byte Oriented Frame Buffer Organization ..................................................... 153
Table 6-3: Output Pixel Transfer Modes ........................................................................... 162
Table 6-4: Grayscale Lookup Table (GrySclLUT) ........................................................... 166
Table 6-5: Grayscale Timing Diagram ............................................................................... 168
Table 6-6: Programming Format ..................................................................................... 169
Table 6-7: Programming 50% Duty Cycle Into Lookup Table ......................................... 173
Table 6-8: Programming 33% Duty Cycle into the Lookup Table ................................... 175
Table 6-9: Programming 33% Duty Cycle into the Lookup Table ................................... 176
Table 6-10: Cursor Memory Organization.......................................................................... 176
Table 6-11: Bits P[2:0] in the PixelMode Register ............................................................. 184
Table 6-12: Register List ................................................................................................. 189
Table 6-13: Color Mode Definition Table ........................................................................ 209
Table 6-14: Blink Mode Definition Table ......................................................................... 209
Table 6-15: Output Shift Mode Table .............................................................................. 209
Table 6-16: Bits per Pixel Scanned Out ............................................................................ 210
Table 6-17: Grayscale Look-Up-Table (LUT) .................................................................... 223
Table 7-1: Screen Pixels ................................................................................................... 234
Table 7-2: 1 bpp Memory Organization ............................................................................ 235
Table 7-3: 4 bpp Memory Organization .......................................................................... 235
Table 7-4: 8 bpp Memory Organization ............................................................................ 236
Table 7-5: 16 bpp Memory Organization .......................................................................... 237
Table 7-6: 24 bpp Packed Memory Organization (4 pixel/ 3 words) ................................. 237
EP9307 User’s Manual - DS667UM1 24 Copyright 2004 Cirrus Logic
Table 7-7: 24 bpp Unpacked Memory Organization (1 pixel/ 1 word) ............................... 238
Table 7-8: Transfer Example 1 ......................................................................................... 239
Table 7-9: Transfer Example 2 ........................................................................................ 239
Table 7-10: Transfer Example 3 ...................................................................................... 239
Table 7-11: Transfer Example 4 ...................................................................................... 239
Table 7-12: Transfer Example 5 ..................................................................................... 240
Table 7-13: 4 BPP Memory Layout .................................................................................. 240
Table 7-14: 8 BPP Memory Layout ................................................................................. 241
Table 7-15: 16 BPP Memory Layout ................................................................................ 241
Table 7-16: 24 BPP Memory Layout ................................................................................ 242
Table 8-1: FIFO RAM Address Map ................................................................................. 265
Table 8-2: RXCtl.MA and RXCtl.IAHA[0] Relationships .................................................. 272
Table 8-3: Ethernet Register List .................................................................................... 303
Table 8-4: Individual Accept, RxFlow Control Enable and Pause Accept Bits ................ 305
Table 8-5: Address Filter Pointer .................................................................................... 315
Table 9-1: Data Transfer Size............................................................................................ 376
Table 9-2: M2P DMA Bus Arbitration................................................................................. 378
Table 9-3: DMA Memory Map............................................................................................ 379
Table 9-4: Internal M2P/P2M Channel Register Map ........................................................ 380
Table 9-5: PPALLOC Register Bits Decode for a Transmit Channel ............................ 383
Table 9-6: PPALLOC Register Bits Decode for a Receive Channel ................................. 383
Table 9-7: PPALLOC Register Reset Values ................................................................... 383
Table 9-8: M2M Channel Register Map ......................................................................... 389
Table 9-9: BWC Decode Values........................................................................................ 392
Table 9-10: DMA Global Interrupt (DMAGlInt) Register .................................................... 404
Table 10-1: OpenHCI Register Addresses ....................................................................... 417
Table 11-1: nXBLS[3:0] Multiplexing.................................................................................. 448
Table 11-2: WRITING to an External Memory System ...................................................... 449
Table 11-3: SMC Register Map ......................................................................................... 450
Table 12-1: Boot Device Selection..................................................................................... 454
Table 12-2: Synchronous Memory Address Decoding ..................................................... 456
Table 12-3: General SDRAM Initialization Sequence ........................................................ 457
Table 12-4: Mode Register Command Decoding............................................................... 458
Table 12-5: Sync Memory CAS Settings ........................................................................... 458
Table 12-6: Sync Memory RAS, (Write) Burst Type Settings ............................................ 459
Table 12-7: Burst Length Settings ..................................................................................... 459
Table 12-8: Chip Select Decoding ..................................................................................... 461
Table 12-9: Memory System Examples ............................................................................. 462
Table 12-10: Memory Address Decoding for 256 Mbit, 16-Bit Wide, and
13-Row x 9-Column x 2-Bank Device ............................................................................. 462
Table 12-11: 32-Bit Wide Data Systems............................................................................ 463
Table 12-12: 16-Bit Wide Data Systems............................................................................ 464
Table 12-13: Synchronous Memory Controller Registers .................................................. 465
Table 12-14: Synchronous Memory Command Encoding ................................................. 467
EP9307 User’s Manual - DS667UM1 25 Copyright 2004 Cirrus Logic
Table 13-1: AHB Arbiter Priority Scheme ...................................................................... 482
Table 13-2: AHB Peripheral Address Range .................................................................. 484
Table 13-3: APB Peripheral Address Range .................................................................. 485
Table 13-4: Register Organization Summary .................................................................... 487
Table 13-5: CP15 ARM920T Register Description ............................................................ 488
Table 13-6: Global Memory Map for the Two Boot Modes ................................................ 489
Table 13-7: Internal Register Map .................................................................................... 491
Table 14-1: Receive FIFO Bit Functions............................................................................ 510
Table 14-2: Legal HDLC Mode Configurations ............................................................... 515
Table 14-3: HDLC Receive Address Matching Modes....................................................... 518
Table 14-4: UART1 Pin Functionality ................................................................................ 520
Table 14-5: DeviceCfg Register Bit Functions .................................................................. 520
Table 15-1: UART2 / IrDA Modes ..................................................................................... 547
Table 15-2: IonU2 Pin Function ........................................................................................ 547
Table 16-1: UART3 Pin Functionality ................................................................................ 561
Table 16-2: DeviceCfg Register Bit Functions .................................................................. 561
Table 17-1: Bit Values to Select Ir Module ........................................................................ 583
Table 17-2: Address Offsets for End-of-frame Data .......................................................... 585
Table 17-3: MIR Frame Format.......................................................................................... 590
Table 17-4: DeviceCfg.IonU2 Pin Function ................................................................... 601
Table 17-5: UART2 / IrDA Modes ..................................................................................... 602
Table 17-6: IrDA Service Memory Accesses / Second ................................................... 603
Table 18-1: Timers Register Map....................................................................................... 621
Table 19-1: Register Memory Map ................................................................................. 630
Table 20-1: Register Memory Map .................................................................................. 637
2
Table 21-1: I
S Controller Input and Output Signals ......................................................... 642
Table 21-2: Audio Interfaces Pin Assignment ................................................................... 643
Table 21-3: I2SClkDiv SYSCON Register Effect on I2S Clock Generation ................... 651
Table 21-4: Bit Clock Rate Generation ........................................................................... 651
Table 21-5: FIFO Flags ..................................................................................................... 654
2
Table 21-6: I Table 21-7: I Table 21-8: I
S TX Registers .......................................................................................... 655
2
S RX Registers .......................................................................................... 662
2
S Configuration and Status Registers ......................................................... 668
Table 22-1: Register Memory Map .................................................................................. 680
Table 22-2: Interaction Between RSIZE and CM ......................................................... 683
Table 22-3: Interaction Between RSIZE and CM Bits ................................................... 685
Table 23-1: SSP Register Memory Map Description ......................................................... 712
Table 24-1: Static Programming Steps .............................................................................. 720
Table 24-2: Dynamic Programming Steps ......................................................................... 721
Table 24-3: PWM Registers Map .................................................................................. 722
Table 25-1: Switch Definitions and Logical Safeguards to Prevent Physical Damage ..... 730
Table 25-2: Touch Screen Switch Register Configurations ......................................... 734
Table 25-3: External Signal Functions ............................................................................ 746
Copyright 2004 Cirrus Logic
Table 25-4: Register Memory Map ................................................................................. 747
Table 26-1: Register Memory Map ................................................................................. 762
Table 27-1: GPIO Port to Pin Map .................................................................................... 772
Table 27-2: GPIO Register Address Map .......................................................................... 773
Table 28-1: Security Register List ................................................................................. 782
EP9307 User’s Manual - DS667UM1 27 Copyright 2004 Cirrus Logic
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Copyright 2004 Cirrus Logic
NN

1.1 Introduction

The EP9307 is a highly integrated system-on-chip processor that paves the way for a multitude of next-generation consumer and industrial electronic products. Designers of digital media servers and jukeboxes, telematic control systems, thin clients, set-top boxes, point-of-sale terminals, industrial controls, biometric security systems, and GPS devices will benefit from the EP9307’s integrated architecture and advanced features. In fact, with amazingly agile performance provided by a 200 MHz ARM920T processor, and featuring an incredibly wide breadth of peripheral interfaces, the EP9307 is well suited to an even broader range of high volume applications. Furthermore, by enabling or disabling the EP9307’s peripheral interfaces, designers can reduce development costs and accelerate time-to-market by creating a single platform that can be easily modified to deliver a variety of differentiated end products.
Figure 1-1. EP9307 Block Diagram

Chapter 1

1Introduction

1
18-bit Raster LCD
SDRAM
SRAM/FLASH/ ROM
12 Channel DMA
Engine
1/10/100 Ethernet
MAC
JTAG
USB Host, 3 Ports
Boot ROM
UART1 w/ HDLC
UART3 w/ HDLC
MaverickCrunch
Coprocessor
ARM920T
I-Cache
AMBA High-Speed Bus (AHB)
Vectored Interrupt
Controllers (2)
D-Cache
16KB
AHB/APB
16KB
MMU
Bridge
UART2 w/ IrDA
System Ctrl - PLLs (2)
Touch Screen ADC
TM
8x8 Key Scan
PWM
2
S (IIS)
I
Enhanced GPIO
EEPROM, LED (2)
SPI
AMBA Peripheral Bus (APB)
AC’97
RTC with Trim
Watchdog Timer
Timers
EP9307 User’s Manual - DS667UM1 29 Copyright 2004 Cirrus Logic
Introduction

1 1.2 EP9307 Features

The EP9307 system-on-chip processor has the following features:
• 200 MHz ARM920T Processor
• 16 KByte data cache and 16 KByte instruction cache
• MMU enabling Linux
• 100 MHz system bus
• MaverickCrunch
• Floating point, integer and signal processing instructions
• Optimized for digital music compression algorithms
• Hardware interlocks allow in-line coding
• MaverickKey
• 32-bit unique ID
• 128-bit random ID
• Integrated Peripheral Interfaces
• EIDE, up to 2 devices
• 1/10/100 Mbps Ethernet MAC
• Three-port USB 2.0 Full Speed host (OHCI)
• Three UARTs (16550 Type)
• IrDA interface, slow and fast mode
™
™
IDs for Digital Rights Management or Design IP Security
®
and Windows® CE
Coprocessor
• LCD and Raster Interface with Graphics Accelerator
• Touch screen interface
•SPI port
• AC ‘97 interface
• I2S interface, up to 6 channels
• 8x8 keypad scanner
• External Memory Options
• 32-bit SDRAM interface, up to four banks
• 32/16/8-bit SRAM/Flash/ROM interface (I/F)
• Serial EEPROM interface
Copyright 2004 Cirrus Logic
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