Cirrus Logic EP9301 User's Guide

EP9301 User’s Guide

http://www.cirrus.com

Release 1.00

FEB ‘04

DS636UM2

Revision Date Changes

1 12 December 2003 Initial Release

2 12 February 2004

Updated ChipID, SysCfg and DeviceCfg register information. Added ExtensionID register information to the Security section.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and i ts subsidiaries (“Ci rrus”) beli eve that the informati on contai ned in this document is accurate and reli able. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the ti me of order acknowledgment, including those pertaini ng to warranty, patent infringement, and limitation of li ability. No responsibility i s assumed by Cirrus for the use of this information, incl uding use of this informati on as the basis for manufacture or sale of any items, or for i nfringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights , copyrights, trademarks, trade secret s or other int ellectual pr operty right s. Cirrus owns the copyrights associated with the informati on contained herein and gives consent for copies to be made of the information only for use within your organi zation with respect to Cirrus integrated circui ts or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, adverti sing or promotional purposes, or for creating any work for resale.

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Cirrus Logi c, Cirrus, MaverickKey, and the Cirrus Logic logo de signs are trademarks of Cirrus Logic, I nc. All other brand and product names in thi s document may be trademarks or service marks of their respective owners.

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2 EP9301 User’s Manual - DS636UM2

About the EP9301 User’s Guide

This Guide describes the architecture, hardware and operation of the Cirrus Logic EP9301. It is intended to be used in conjunction with the EP9301 Datasheet, which contains the full electrical specifications for the device.

How to Use this Guide

Subject Matter Location

AC’97 Chapter 18 - AC’97 Controller

ARM920T Processor

Boot ROM, Hardware and Software Chapter 3 - Boot ROM

Booting From SROM or SyncFlash Chapter 10 - SDRAM, SyncROM, and SyncFLASH Controller

Buses - AMBA, AHB, APB

DMA Controller Chapter 7 - DMA Controller

EP9301 Block Diagram

Ethernet Chapter 6 - 1/10/100 Mbps Ethernet LAN Controller

GPIO Chapter 21 - GPIO Interface

HDLC Chapter 11 - UART1 With HDLC and Modem Control Signals

S Chapter 17 - I2S Controller

Infra-Red Interface Chapter 13 - IrDA

Interrupt Registers Chapter 5 - Vectored Interrupt Controller

Interrupts Chapter 5 - Vectored Interrupt Controller

IrDA Chapter 13 - IrDA

MAC Chapter 6 - 1/10/100 Mbps Ethernet LAN Controller

Memory Map Chapter 1 - Introduction

Modem Chapter 11 - UART1 With HDLC and Modem Control Signals

Power Management Chapter 4 - System Controller

Programming Clocks Chapter 4 - System Controller

Real Time Clock Chapter 16 - Real Time Clock With Software Trim

Chapter 2 - ARM920T Core and Advanced High-Speed Bus (AHB)

Preface

Subject Matter Location

RTC Chapter 16 - Real Time Clock With Software Trim

SDRAM Chapter 10 - SDRAM, SyncROM, and SyncFLASH Controller

Security Chapter 22 - Security

SMC Chapter 9 - Static Memory Controller

SSP Chapter 19 - Synchronous Serial Port

Static Memory Controller Chapter 9 - Static Memory Controller

System Configuration Chapter 4 - System Controller

System Registers Chapter 4 - System Controller

Timers Chapter 14 - Timers

Touch Screen Chapter 20 - Analog-to-Digital Converter (ADC) Interface

UART

USB Chapter 8 - Universal Serial Bus Host Controller

Vectored Interrupt Registers Chapter 5 - Vectored Interrupt Controller

Vectored Interrupts Chapter 5 - Vectored Interrupt Controller

Watchdog Timer Chapter 15 - Watchdog Timer

Chapter 11 - UART1 With HDLC and Modem Control Signals Chapter 12 - UART2

Reference Documents

1. ARM920T Technical Reference Manual

2. AMBA Specification (Rev. 2.0), ARM IHI 0011A, ARM Limited.

3. AHB Example AMBA System (Addendum 01), ARM DDI 0170A, ARM Limited.

4. The coprocessor instruction assembler notation can be referenced from ARM programming manuals or the Quick Reference Card, document number ARM QRC 0001D.

5. The MAC engine is compliant with the requirements of ISO/IEC 8802-3 (1993), Sections 3 and 4.

6. OpenHCI - Open Host Controller interface Specification for USB, Release

1.0a; Compaq, Microsoft, National Semiconductor.

7. ARM Coprocessor Quick Reference Card, document number ARM QRC 0001D.

4 EP9301 User’s Manual - DS636UM2

8. Information Technology, AT Attachment with Packet Interface - 5 (ATA/ATAPI-5) ANSI NCITS document T13 1321D, Revision 3, 29 February 2000

9. OpenHCI - Open Host Controller Interface Specification for USB, Release: 1.0a, Released - 09/14/99 2:33 PM

10. ARM PrimeCell PL190-Rel1v1 Revision 1.7 Technical Reference Manual DDI0181C

11. Audio Codec ‘97, Revision 2.3, April 2002, Intel Corporation

Notational Conventions

This document uses the following conventions:

• Internal and external Signal Names, and Pin Names use mixed upper and lower case alphanumeric, and are shown in bold font: RDLED.

• Register Bit Fields are named using upper and lower case alphanumeric: that is, SBOOT, LCSn1.

• Registers are named using mixed upper and lower case alphanumeric: that is, SysCfg or PxDDR. (Where there are multiple registers with similar names, a lower case “x” is used as a place holder. For example, in the PxDDR registers, x represents a letter between A and H, indicating the specific port being discussed.)

Caution: In the Internal Register Map in Table 2-7 on page 7-47, some

memory locations are listed as Reserved. These memory locations should not be used. Reading from these memory locations will yield invalid data. Writing to these memory locations may cause unpredictable results.

(An example register description is shown below. This description is used for the following examples.)

A specific bit may be specified in one of two ways:

By or by

Both of these representations refer to the same bit.

The following:

SysCfg[8]

, or

SysCfg.SBOOT

also refer to the same bit.

Hexidecimal numbers are referred to as

0x0000_0000

Binary numbers are referred to as

0000_0000b

Note: This is only and example. For actual SysCfg register information, see “SysCfg”

on page 97.

SysCfg

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

REV RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD SBOOT LCSn7 LCSn6 LASDO LEEDA LEECLK RSVD LCSn2 LCSn1

Address:

0x8093_009C - Read/Write, Software locked

Default:

0x0000_0000

Definition:

System Configuration Register. Provides various system configuration options.

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

REV: Revision, reads chip Version number: 0 - Rev A, 1 - Rev B,

2 - Rev C, 3 - Rev D.

SBOOT: Serial Boot Flag. This bit is read-only.

1 hardware detected Serial Boot selection, 0 hardware detected Normal Boot.

LCSn7, LCSn6: Latched version of CSn7 and CSn6 respectively. These

are used to define the external bus width for the boot code boot.

LASDO: Latched version of ASDO pin. Used to select synchronous

versus asynchronous boot device.

LEEDA: Latched version of EEDAT pin.

LEECLK: Define Internal or external boot:

1 Internal 0 External

6 EP9301 User’s Manual - DS636UM2

LCSn2, LCSn1: Define Watchdog startup action:

0 0 Watchdog disabled, Reset duration disabled 0 1 Watchdog disabled, Reset duration active 1 0 Watchdog active, Reset duration disabled 1 1 Watchdog active, Reset duration active

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8 EP9301 User’s Manual - DS636UM2

Preface............................................................................................................. 3

About the EP9301 User’s Guide ............................................................................................................ 3

How to Use this Guide ...........................................................................................................................3

Related Documents from Cirrus Logic ...................................................................................................4

Reference Documents ...........................................................................................................................4

Notational Conventions ..........................................................................................................................5

Chapter 1 Introduction ............................................................................... 23

1.1 Introduction ...................................................................................................................................23

1.2 EP9301 Features ..........................................................................................................................23

1.3 EP9301 Applications .....................................................................................................................25

1.4 Overview of EP9301 Features ......................................................................................................25

1.4.1 High-Performance ARM920T Processor Core ....................................................................25

1.4.2 MaverickKey™ Unique ID Secures Digital Content and OEM Designs ..............................26

1.4.3 Integrated Two-port USB 2.0 Full Speed Host with Transceivers .......................................26

1.4.4 Integrated Ethernet MAC Reduces BOM Costs ..................................................................26

1.4.5 Multiple Booting Mechanisms Increase Flexibility ...............................................................26

1.4.6 Abundant General Purpose I/Os Build Flexible Systems ....................................................27

1.4.7 General-Purpose Memory Interface (SDRAM, SRAM, ROM and FLASH) .........................27

1.4.8 12-Bit Analog-to-Digital Converter (ADC) Functionality....................................................... 27

Chapter 2 ARM920T Core and Advanced High-Speed Bus (AHB) ......... 29

2.1 Introduction ...................................................................................................................................29

2.2 Overview: ARM920T Processor Core ...........................................................................................29

2.2.1 Features ..............................................................................................................................29

2.2.2 Block Diagram .....................................................................................................................30

2.2.3 Operations...........................................................................................................................30

2.2.3.1 ARM9TDMI Core........................................................................................................31

2.2.3.2 Memory Management Unit .........................................................................................32

2.2.3.3 Cache and Write Buffer..............................................................................................33

2.2.4 AMBA AHB Bus Interface Overview....................................................................................34

2.2.5 EP9301 AHB Implementation Details..................................................................................36

2.2.6 Memory and Bus Access Errors ..........................................................................................37

2.2.7 Bus Arbitration .....................................................................................................................37

2.2.7.1 Main AHB Bus Arbiter ................................................................................................38

2.2.7.2 EBI Bus Arbiter...........................................................................................................39

2.3 AHB Decoder ................................................................................................................................39

2.3.1 AHB Bus Slave ....................................................................................................................40

2.3.2 AHB to APB Bridge..............................................................................................................40

2.3.2.1 Function and Operation of APB Bridge......................................................................41

2.3.3 APB Bus Slave ....................................................................................................................41

2.3.4 Register Definitions .............................................................................................................42

2.3.5 Memory Map........................................................................................................................45

2.3.6 Internal Register Map ..........................................................................................................46

2.3.6.1 Memory Access Rules ...............................................................................................46

Chapter 3 Boot ROM .................................................................................. 59

3.1 Introduction ...................................................................................................................................59

3.1.1 Boot ROM Hardware Operational Overview ....................................................................... 59

3.1.1.1 Memory Map.............................................................................................................. 59

3.1.2 Boot ROM Software Operational Overview......................................................................... 59

3.1.2.1 Image Header ............................................................................................................ 60

3.1.2.2 Boot Algorithm ........................................................................................................... 60

3.1.2.3 Flowchart................................................................................................................... 62

3.2 Boot Options................................................................................................................................. 62

3.2.1 UART Boot.......................................................................................................................... 63

3.2.2 SPI Boot.............................................................................................................................. 63

3.2.3 FLASH Boot ........................................................................................................................ 64

3.2.4 SDRAM or SyncFLASH Boot.............................................................................................. 64

3.2.5 Synchronous Memory Operation ........................................................................................ 65

Chapter 4 System Controller .....................................................................67

4.1 Introduction ................................................................................................................................... 67

4.1.1 System Startup.................................................................................................................... 67

4.1.2 System Reset...................................................................................................................... 67

4.1.3 Hardware Configuration Control.......................................................................................... 68

4.1.4 Software System Configuration Options ............................................................................. 69

4.1.5 Clock Control....................................................................................................................... 69

4.1.5.1 Oscillators and Programmable PLLs ......................................................................... 70

4.1.5.2 Bus and Peripheral Clock Generation ....................................................................... 71

4.1.5.3 Steps for Clock Configuration.................................................................................... 74

4.1.6 Power Management ............................................................................................................ 75

4.1.6.1 Clock Gatings ............................................................................................................ 75

4.1.6.2 System Power States ................................................................................................ 75

4.1.7 Interrupt Generation ............................................................................................................ 77

4.2 Registers ...................................................................................................................................... 79

Chapter 5 Vectored Interrupt Controller ................................................... 99

5.1 Introduction ................................................................................................................................... 99

5.1.1 Interrupt Priority................................................................................................................. 100

5.1.2 Interrupt Descriptions ........................................................................................................ 102

5.2 Registers .................................................................................................................................... 106

Chapter 6 1/10/100 Mbps Ethernet LAN Controller ................................ 119

6.1 Introduction ................................................................................................................................. 119

6.1.1 Detailed Description.......................................................................................................... 119

6.1.1.1 Host Interface and Descriptor Processor................................................................. 119

6.1.1.2 Reset and Initialization ............................................................................................ 120

6.1.1.3 Powerdown Modes .................................................................................................. 120

6.1.1.4 Address Space ........................................................................................................ 121

6.1.2 MAC Engine...................................................................................................................... 121

6.1.2.1 Data Encapsulation ................................................................................................. 121

6.1.3 Packet Transmission Process........................................................................................... 122

6.1.3.1 Carrier Deference .................................................................................................... 123

6.1.4 Transmit Back-Off ............................................................................................................. 125

6.1.4.1 Transmission ...........................................................................................................125

10 EP9301 User’s Manual - DS636UM2

6.1.4.2 The FCS Field..........................................................................................................126

6.1.4.3 Bit Order...................................................................................................................126

6.1.4.4 Destination Address (DA) Filter................................................................................126

6.1.4.5 Perfect Address Filtering..........................................................................................126

6.1.4.6 Hash Filter................................................................................................................127

6.1.4.7 Flow Control .............................................................................................................128

6.1.4.8 Receive Flow Control...............................................................................................128

6.1.4.9 Transmit Flow Control ..............................................................................................129

6.1.4.10 Rx Missed and Tx Collision Counters....................................................................129

6.1.4.11 Accessing the MII...................................................................................................130

6.2 Descriptor Processor...................................................................................................................131

6.2.1 Receive Descriptor Processor Queues .............................................................................131

6.2.2 Receive Descriptor Queue ................................................................................................132

6.2.3 Receive Status Queue.......................................................................................................134

6.2.3.1 Receive Status Format.............................................................................................137

6.2.3.2 Receive Flow............................................................................................................140

6.2.3.3 Receive Errors .........................................................................................................141

6.2.3.4 Receive Descriptor Data/Status Flow ......................................................................142

6.2.3.5 Receive Descriptor Example....................................................................................143

6.2.3.6 Receive Frame Pre-Processing ...............................................................................143

6.2.3.7 Transmit Descriptor Processor.................................................................................144

6.2.3.8 Transmit Descriptor Queue ......................................................................................144

6.2.3.9 Transmit Descriptor Format .....................................................................................147

6.2.3.10 Transmit Status Queue ..........................................................................................148

6.2.3.11 Transmit Status Format..........................................................................................150

6.2.3.12 Transmit Flow.........................................................................................................152

6.2.3.13 Transmit Errors ......................................................................................................153

6.2.3.14 Transmit Descriptor Data/Status Flow ...................................................................154

6.2.4 Interrupts ...........................................................................................................................155

6.2.4.1 Interrupt Processing.................................................................................................155

6.2.5 Initialization........................................................................................................................155

6.2.5.1 Interrupt Processing.................................................................................................156

6.2.5.2 Receive Queue Processing......................................................................................156

6.2.5.3 Transmit Queue Processing.....................................................................................156

6.2.5.4 Other Processing .....................................................................................................157

6.2.5.5 Transmit Restart Process.........................................................................................157

6.3 Registers.....................................................................................................................................159

Chapter 7 DMA Controller........................................................................ 213

7.1 Introduction .................................................................................................................................213

7.1.1 DMA Features List.............................................................................................................213

7.1.2 Managing Data Transfers Using a DMA Channel .............................................................214

7.1.3 DMA Operations ................................................................................................................215

7.1.3.1 Memory-to-Memory Channels..................................................................................216

7.1.3.2 Memory-to-Peripheral Channels ..............................................................................216

7.1.4 Internal M2P or P2M AHB Master Interface Functional Description..................................217

7.1.5 M2M AHB Master Interface Functional Description...........................................................218

7.1.5.1 Software Trigger Mode ............................................................................................ 218

7.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP) and

for External Peripherals without Handshaking Signals ..................................................... 218

7.1.5.3 Hardware Trigger Mode for External Peripherals with Handshaking Signals .......... 219

7.1.6 AHB Slave Interface Limitations........................................................................................ 219

7.1.7 Interrupt Interface.............................................................................................................. 219

7.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description.................................... 219

7.1.9 Internal M2P/P2M DMA Functional Description................................................................ 220

7.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine.................................. 220

7.1.9.2 Data Transfer Initiation and Termination ................................................................. 222

7.1.10 M2M DMA Functional Description................................................................................... 223

7.1.10.1 M2M DMA Control Finite State Machine ............................................................... 223

7.1.10.2 M2M Buffer Control Finite State Machine.............................................................. 225

7.1.10.3 Data Transfer Initiation .......................................................................................... 227

7.1.10.4 Data Transfer Termination..................................................................................... 229

7.1.10.5 Memory Block Transfer ......................................................................................... 230

7.1.10.6 Bandwidth Control ................................................................................................. 230

7.1.10.7 External Peripheral DMA Request (DREQ) Mode ................................................. 230

7.1.11 DMA Data Transfer Size Determination.......................................................................... 232

7.1.11.1 Software Initiated M2M and M2P/P2M Transfers.................................................. 232

7.1.11.2 Hardware Initiated M2M Transfers ........................................................................ 232

7.1.12 Buffer Descriptors ........................................................................................................... 233

7.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors ................................................ 233

7.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors................................................. 233

7.1.12.3 M2M Channel Buffer Descriptors........................................................................... 233

7.1.13 Bus Arbitration................................................................................................................. 233

7.2 Registers .................................................................................................................................... 235

7.2.1 DMA Controller Memory Map............................................................................................ 235

7.2.2 Internal M2P/P2M Channel Register Map......................................................................... 235

Chapter 8 Universal Serial Bus Host Controller .................................... 263

8.1 Introduction ................................................................................................................................. 263

8.1.1 Features............................................................................................................................ 263

8.2 Overview..................................................................................................................................... 263

8.2.1 Data Transfer Types ......................................................................................................... 264

8.2.2 Host Controller Interface ................................................................................................... 265

8.2.2.1 Communication Channels ....................................................................................... 265

8.2.2.2 Data Structures........................................................................................................266

8.2.3 Host Controller Driver Responsibilities.............................................................................. 268

8.2.3.1 Host Controller Management................................................................................... 268

8.2.3.2 Bandwidth Allocation ............................................................................................... 268

8.2.3.3 List Management ..................................................................................................... 269

8.2.3.4 Root Hub ................................................................................................................. 270

8.2.4 Host Controller Responsibilities ........................................................................................ 270

8.2.4.1 USB States.............................................................................................................. 270

8.2.4.2 Frame management ................................................................................................ 270

8.2.4.3 List Processing ........................................................................................................270

12 EP9301 User’s Manual - DS636UM2

8.2.5 USB Host Controller Blocks...............................................................................................271

8.2.5.1 AHB Slave................................................................................................................271

8.2.5.2 AHB Master..............................................................................................................271

8.2.5.3 HCI Slave Block .......................................................................................................271

8.2.5.4 HCI Master Block .....................................................................................................272

8.2.5.5 USB State Control....................................................................................................272

8.2.5.6 Data FIFO ................................................................................................................272

8.2.5.7 List Processor ..........................................................................................................272

8.2.5.8 Root Hub and Host SIE............................................................................................272

8.3 Registers.....................................................................................................................................273

Chapter 9 Static Memory Controller ....................................................... 305

9.1 Introduction .................................................................................................................................305

9.2 Static Memory Controller Operation............................................................................................306

9.3 Byte Lane Write / Read Control ..................................................................................................308

9.4 Registers.....................................................................................................................................310

Chapter 10 SDRAM, SyncROM, and SyncFLASH Controller................ 313

10.1 Introduction ...............................................................................................................................313

10.1.1 Booting (from SROM or SyncFLASH) .............................................................................313

10.1.1.1 Address Pin Usage ................................................................................................314

10.1.1.2 SDRAM Initialization ..............................................................................................316

10.1.1.3 Programming External Device Mode Register .......................................................317

10.1.1.4 SDRAM Self Refresh .............................................................................................319

10.1.1.5 SROM and SyncFlash............................................................................................320

10.1.1.6 External Synchronous Memory System .................................................................320

10.2 Registers...................................................................................................................................324

Chapter 11 UART1 With HDLC and Modem Control Signals................ 331

11.1 Introduction ...............................................................................................................................331

11.2 UART Overview ........................................................................................................................331

11.2.1 UART Functional Description ..........................................................................................332

11.2.1.1 AMBA APB Interface..............................................................................................332

11.2.1.2 DMA Block .............................................................................................................332

11.2.1.3 Register Block........................................................................................................333

11.2.1.4 Baud Rate Generator.............................................................................................334

11.2.1.5 Transmit FIFO........................................................................................................334

11.2.1.6 Receive FIFO .........................................................................................................334

11.2.1.7 Transmit Logic........................................................................................................334

11.2.1.8 Receive Logic.........................................................................................................334

11.2.1.9 Interrupt Generation Logic .....................................................................................334

11.2.1.10 Synchronizing Registers and Logic......................................................................335

11.2.2 UART Operation ..............................................................................................................335

11.2.2.1 Error Bits................................................................................................................336

11.2.2.2 Disabling the FIFOs ...............................................................................................336

11.2.2.3 System/diagnostic Loopback Testing.....................................................................336

11.2.2.4 UART Character Frame .........................................................................................336

11.2.3 Interrupts .........................................................................................................................337

11.2.3.1 UARTMSINTR....................................................................................................... 337

11.2.3.2 UARTRXINTR ....................................................................................................... 337

11.2.3.3 UARTTXINTR........................................................................................................ 338

11.2.3.4 UARTRTINTR........................................................................................................ 338

11.2.3.5 UARTINTR ............................................................................................................ 338

11.3 Modem...................................................................................................................................... 338

11.4 HDLC........................................................................................................................................ 339

11.4.1 Overview of HDLC Modes............................................................................................... 339

11.4.2 Selecting HDLC Modes................................................................................................... 340

11.4.3 HDLC Transmit ............................................................................................................... 341

11.4.4 HDLC Receive ................................................................................................................ 342

11.4.5 CRCs............................................................................................................................... 343

11.4.6 Address Matching ........................................................................................................... 343

11.4.7 Aborts.............................................................................................................................. 344

11.4.8 DMA ................................................................................................................................ 344

11.4.9 Writing Configuration Registers ...................................................................................... 345

11.5 UART1 Package Dependency..................................................................................................345

11.5.1 Clocking Requirements ...................................................................................................346

11.5.2 Bus Bandwidth Requirements......................................................................................... 346

11.6 Registers .................................................................................................................................. 348

Chapter 12 UART2 .................................................................................... 369

12.1 Introduction............................................................................................................................... 369

12.2 IrDA SIR Block.......................................................................................................................... 369

12.2.1 IrDA SIR Encoder/decoder Functional Description ......................................................... 369

12.2.1.1 IrDA SIR Transmit Encoder ................................................................................... 370

12.2.1.2 IrDA SIR Receive Decoder.................................................................................... 370

12.2.2 IrDA SIR Operation ......................................................................................................... 371

12.2.2.1 System/diagnostic Loopback Testing .................................................................... 372

12.2.3 IrDA Data Modulation...................................................................................................... 372

12.2.4 Enabling Infrared (Ir) Modes ........................................................................................... 373

12.3 UART2 Package Dependency..................................................................................................373

12.3.1 Clocking Requirements ...................................................................................................373

12.3.2 Bus Bandwidth Requirements......................................................................................... 374

12.4 Registers .................................................................................................................................. 375

Chapter 13 IrDA......................................................................................... 387

13.1 Introduction............................................................................................................................... 387

13.2 IrDA Interfaces.......................................................................................................................... 387

13.3 Shared IrDA Interface Feature ................................................................................................. 388

13.3.1 Overview ......................................................................................................................... 388

13.3.2 Functional Description..................................................................................................... 388

13.3.2.1 General Configuration ........................................................................................... 389

13.3.2.2 Transmitting Data .................................................................................................. 389

13.3.2.3 Receiving Data ...................................................................................................... 392

13.3.2.4 Special Conditions ................................................................................................. 394

13.3.3 Control Information Buffering .......................................................................................... 394

13.4 Medium IrDA Specific Features................................................................................................ 395

14 EP9301 User’s Manual - DS636UM2

13.4.1 Introduction ......................................................................................................................395

13.4.1.1 Bit Encoding...........................................................................................................395

13.4.1.2 Frame Format ........................................................................................................395

13.4.2 Functional Description .....................................................................................................397

13.4.2.1 Baud Rate Generation ........................................................................................... 397

13.4.2.2 Receive Operation .................................................................................................398

13.4.2.3 Transmit Operation ................................................................................................399

13.5 Fast IrDA Specific Features ......................................................................................................400

13.5.1 Introduction ......................................................................................................................400

13.5.1.1 4PPM Modulation...................................................................................................400

13.5.1.2 4.0 Mbps FIR Frame Format..................................................................................402

13.5.2 Functional Description .....................................................................................................403

13.5.2.1 Baud Rate Generation ........................................................................................... 404

13.5.2.2 Receive Operation .................................................................................................404

13.5.2.3 Transmit Operation ................................................................................................406

13.5.3 IrDA Connectivity.............................................................................................................407

13.5.4 IrDA Integration Information ............................................................................................408

13.5.4.1 Enabling Infrared Modes ........................................................................................408

13.5.4.2 Clocking Requirements ..........................................................................................408

13.5.4.3 Bus Bandwidth Requirements................................................................................ 409

13.6 Registers...................................................................................................................................410

Chapter 14 Timers .................................................................................... 425

14.1 Introduction ...............................................................................................................................425

14.1.1 Features ..........................................................................................................................425

14.1.2 16 and 32-bit Timer Operation.........................................................................................425

14.1.2.1 Free Running Mode ...............................................................................................426

14.1.2.2 Pre-load Mode........................................................................................................426

14.1.3 40-bit Timer Operation.....................................................................................................426

14.2 Registers...................................................................................................................................427

Chapter 15 Watchdog Timer.................................................................... 433

15.1 Introduction ...............................................................................................................................433

15.1.1 Watchdog Activation........................................................................................................434

15.1.2 Clocking Requirements ...................................................................................................434

15.1.3 Reset Requirements........................................................................................................434

15.1.4 Watchdog Status .............................................................................................................434

15.2 Registers...................................................................................................................................435

Chapter 16 Real Time Clock With Software Trim .................................. 439

16.1 Introduction ...............................................................................................................................439

16.1.1 Software Trim ..................................................................................................................439

16.1.1.1 Software Compensation.........................................................................................440

16.1.1.2 Oscillator Frequency Calibration ............................................................................440

16.1.1.3 RTCSWComp Value Determination.......................................................................440

16.1.1.4 Example - Measured Value Split Into Integer and Fractional Component .............441

16.1.1.5 Maximum Error Calculation vs. Real Time Clock Accuracy...................................441

16.1.1.6 Real-Time Interrupt................................................................................................442

16.1.2 Reset Control.................................................................................................................. 442

16.2 Registers .................................................................................................................................. 443

Chapter 17 I2S Controller ......................................................................... 447

17.1 Introduction............................................................................................................................... 447

17.2 I

17.3 I

S Transmitter Channel Overview ........................................................................................... 449

S Receiver Channel Overview ............................................................................................... 452

17.3.1 Receiver FIFO................................................................................................................. 453

17.4 I

17.5 I

17.6 I

S Configuration and Status Registers.................................................................................... 455

S Master Clock Generation.................................................................................................... 455

S Bit Clock Rate Generation .................................................................................................. 457

17.6.1 Example of the Bit Clock Generation. ............................................................................. 458

17.6.2 Example of Right Justified LRCK format......................................................................... 458

17.7 Interrupts .................................................................................................................................. 459

17.8 Registers .................................................................................................................................. 461

17.8.1 I

17.8.2 I

17.8.3 I

17.8.4 I

S TX Registers ............................................................................................................. 461

S RX Registers............................................................................................................. 465

S Configuration and Status Registers .......................................................................... 469

S Global Status Registers ............................................................................................ 472

Chapter 18 AC’97 Controller .................................................................... 475

18.1 Introduction............................................................................................................................... 475

18.2 Interrupts .................................................................................................................................. 477

18.2.1 Channel Interrupts........................................................................................................... 477

18.2.1.1 RIS......................................................................................................................... 477

18.2.1.2 TIS ......................................................................................................................... 477

18.2.1.3 RTIS ...................................................................................................................... 477

18.2.1.4 TCIS ...................................................................................................................... 478

18.2.2 Global Interrupts.............................................................................................................. 478

18.2.2.1 CODECREADY ..................................................................................................... 478

18.2.2.2 WINT ..................................................................................................................... 478

18.2.2.3 GPIOINT................................................................................................................ 478

18.2.2.4 GPIOTXCOMPLETE ............................................................................................. 478

18.2.2.5 SLOT2INT ............................................................................................................. 479

18.2.2.6 SLOT1TXCOMPLETE........................................................................................... 479

18.2.2.7 SLOT2TXCOMPLETE........................................................................................... 479

18.3 System Loopback Testing ........................................................................................................ 479

18.4 Registers .................................................................................................................................. 480

Chapter 19 Synchronous Serial Port ...................................................... 497

19.1 Introduction............................................................................................................................... 497

19.2 Features ................................................................................................................................... 497

19.3 SSP Functionality ..................................................................................................................... 498

19.4 SSP Pin Multiplex..................................................................................................................... 498

19.5 Configuring the SSP ................................................................................................................. 498

19.5.1 Enabling SSP Operation ................................................................................................. 499

19.5.2 Master/Slave Mode ......................................................................................................... 499

19.5.3 Serial Bit Rate Generation ..............................................................................................499

19.5.4 Frame Format ................................................................................................................ 499

16 EP9301 User’s Manual - DS636UM2

19.5.5 Texas Instruments® Synchronous Serial Frame Format ................................................500

19.5.6 Motorola® SPI Frame Format .........................................................................................501

19.5.6.1 SPO Clock Polarity.................................................................................................501

19.5.6.2 SPH Clock Phase...................................................................................................501

19.5.7 Motorola SPI Format with SPO=0, SPH=0......................................................................501

19.5.8 Motorola SPI Format with SPO=0, SPH=1.....................................................................503

19.5.9 Motorola SPI Format with SPO=1, SPH=0......................................................................504

19.5.10 Motorola SPI Format with SPO=1, SPH=1....................................................................506

19.5.11 National Semiconductor® Microwire® Frame Format ...................................................507

19.5.11.1 Setup and Hold Time Requirements on SFRMIN with

Respect to SCLKIN in Microwire Mode.............................................................................509

19.6 Registers...................................................................................................................................510

Chapter 20 Analog-to-Digital Converter (ADC) Interface ...................... 517

20.1 Introduction ...............................................................................................................................517

20.2 ADC Operation..........................................................................................................................517

20.3 Registers...................................................................................................................................518

Chapter 21 GPIO Interface ....................................................................... 523

21.1 Introduction ...............................................................................................................................523

21.1.1 Memory Map....................................................................................................................524

21.1.2 Functional Description .....................................................................................................524

21.1.3 Reset ...............................................................................................................................529

21.1.4 GPIO Pin Map .................................................................................................................529

21.2 Registers...................................................................................................................................531

Chapter 22 Security .................................................................................. 553

22.1 Introduction ...............................................................................................................................553

22.2 Features....................................................................................................................................553

22.3 Contact Information...................................................................................................................553

22.4 Registers...................................................................................................................................554

Chapter 23 Glossary................................................................................. 555

List of Figures

Figure 1-1. EP9301 Block Diagram .................................................................................. 23

Figure 2-1. ARM920T Block Diagram ................................................................................. 30

Figure 2-2. Typical AMBA AHB System ............................................................................ 35

Figure 2-3. EP9301 Main Data Paths ................................................................................. 36

Figure 3-1. Flow Chart of Boot ROM Software ................................................................ 62

Figure 3-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices ............................... 65

Figure 4-1. Phase Locked Loop (PLL) Structure .............................................................. 70

Figure 4-2. EP9301 Clock Generation System.................................................................... 71

Figure 4-3. Bus Clock Generation ..................................................................................... 72

Figure 4-4. EP9301 Power States and Transitions ........................................................... 76

Figure 5-1. Vectored Interrupt Controller Block Diagram ................................................ 100

Figure 6-1. Block Diagram ................................................................................................ 119

Figure 6-2. Ethernet Frame / Packet Format (Type II only) ............................................... 122

Figure 6-3. Packet Transmission Process ......................................................................... 123

Figure 6-4. Carrier Deference State Diagram .................................................................... 124

Figure 6-5. Data Bit Transmission Order .......................................................................... 126

Figure 6-6. CRC Logic .................................................................................................... 127

Figure 6-7. Receive Descriptor Format and Data Fragments ......................................... 133

Figure 6-8. Receive Status Queue .................................................................................. 136

Figure 6-9. Receive Flow Diagram ................................................................................. 140

Figure 6-10. Receive Descriptor Data/Status Flow ........................................................... 142

Figure 6-11. Receive Descriptor Example ........................................................................ 143

Figure 6-12. Receive Frame Pre-processing .................................................................. 144

Figure 6-13. Transmit Descriptor Format and Data Fragments ........................................ 146

Figure 6-14. Multiple Fragments Per Transmit Frame ...................................................... 146

Figure 6-15. Transmit Status Queue ............................................................................... 149

Figure 6-16. Transmit Flow Diagram .............................................................................. 152

Figure 6-17. Transmit Descriptor Data/Status Flow ........................................................ 154

Figure 7-1. DMA M2P/P2M Finite State Machine.............................................................. 220

Figure 7-2. M2M DMA Control Finite State Machine ......................................................... 223

Figure 7-3. M2M DMA Buffer Finite State Machine .......................................................... 225

Figure 7-4. Edge-triggered DREQ Mode ........................................................................... 231

Figure 8-1. USB Focus Areas ............................................................................................ 264

Figure 8-2. Communication Channels .............................................................................. 265

Figure 8-3. Typical List Structure ...................................................................................... 266

Figure 8-4. Interrupt Endpoint Descriptor Structure .......................................................... 267

Figure 8-5. Sample Interrupt Endpoint Schedule ............................................................. 268

Figure 8-6. Frame Bandwidth Allocation ........................................................................... 269

Figure 8-7. USB Host Controller Block Diagram ................................................................ 271

Figure 9-1. 16-bit read, 16-bit Memory, 0 wait cycles, RBLE = 1,

WAITn Inactive ................................................................................................................ 306

Figure 9-2. 16-bit write, 16-bit Memory, 0 wait cycles, RBLE = 1,

WAITn Inactive ............................................................................................................... 307

Figure 9-3. 16-bit read, 16-bit Memory, RBLE = 1, WAITn Active ..................................... 307

Figure 9-4. 16-bit write, 16-bit Memory, RBLE = 1, WAITn Active..................................... 308

Figure 11-1. UART Block Diagram ................................................................................... 333

Figure 11-2. UART Character Frame ................................................................................ 337

Figure 12-1. IrDA SIR Encoder/decoder Block Diagram ................................................... 370

Figure 12-2. IrDA Data Modulation (3/16) ......................................................................... 372

Figure 13-1. RZ1/NRZ Bit Encoding Example .................................................................. 395

Figure 13-2. 4PPM Modulation Encoding ......................................................................... 401

Figure 13-3. 4PPM Modulation Example .......................................................................... 401

Figure 13-4. IrDA (4.0 Mbps) Transmission Format .......................................................... 402

Figure 17-1. Architectural Overview of the I

S Controller ............................................... 448

Figure 17-2. Transmitter FIFO ........................................................................................ 450

Figure 17-3. Bit Clock Generation Example ................................................................. 458

Figure 17-4. Frame Format for Right Justified Data ................................................... 459

Figure 19-1. Texas Instruments Synchronous Serial Frame Format (Single Transfer) ..... 500

Figure 19-2. TI Synchronous Serial Frame Format (Continuous Transfer) ....................... 501

Figure 19-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0....... 502

Figure 19-4. Motorola SPI Frame Format (Continuous Transfer)

with SPO=0 and SPH=0.................................................................................................. 502

Figure 19-5. Motorola SPI Frame Format with SPO=0 and SPH=1 .................................. 503

Figure 19-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0....... 504

Figure 19-7. Motorola SPI Frame Format (Continuous Transfer)

with SPO=1 and SPH=0.................................................................................................. 505

Figure 19-8. Motorola SPI Frame Format with SPO=1 and SPH=1 .................................. 506

Figure 19-9. Microwire Frame Format (Single Transfer).................................................... 507

Figure 19-10. Microwire Frame Format (Continuous Transfers)........................................ 508

Figure 19-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements.... 509

Figure 21-1. System Level GPIO Connectivity ............................................................... 524

Figure 21-2. Signal Connections Within GPIO Port C Control Logic ............................... 526

Figure 21-3. Signal Connections Within GPIO Port E Control Logic ............................... 526

Figure 21-4. Signal Connections Within GPIO Port G Control Logic ............................... 527

Figure 21-5. Signal Connections Within GPIO Port H Control Logic ............................... 527

Figure 21-6. Signal Connections Within the Enhanced GPIO Port A and B Control Logic ....

528

Figure 21-7. Signal Connections Within the Enhanced GPIO Port F Control Logic ........ 529

List of Tables

Table 2-1: AHB Arbiter Priority Scheme ......................................................................... 38

Table 2-2: AHB Peripheral Address Range ...................................................................... 40

Table 2-3: APB Peripheral Address Range ..................................................................... 41

Table 2-4: Register Organization Summary ........................................................................ 43

Table 2-5: CP15 ARM920T Register Description ................................................................ 44

Table 2-6: Global Memory Map for the Two Boot Modes .................................................... 45

Table 2-7: Internal Register Map ........................................................................................ 47

Table 3-1: Boot Configuration Options (Normal Boot) ....................................................... 63

Table 4-1: Boot Configuration Options .............................................................................. 69

Table 4-2: Clock Speeds and Sources ............................................................................. 74

Table 4-3: Peripherals with PCLK gating .......................................................................... 75

Table 4-4: Syscon Register List ......................................................................................... 79

Table 4-5: Audio Interfaces Pin Assignment ....................................................................... 92

Table 5-1: Interrupt Configuration...................................................................................... 101

Table 5-2: VICx Register Summary ................................................................................... 106

Table 6-1: FIFO RAM Address Map ................................................................................. 121

Table 6-2: RXCtl.MA and RXCtl.IAHA[0] Relationships .................................................. 128

Table 6-3: Ethernet Register List .................................................................................... 159

Table 6-4: Individual Accept, RxFlow Control Enable and Pause Accept Bits ................ 161

Table 6-5: Address Filter Pointer .................................................................................... 171

Table 7-1: Data Transfer Size............................................................................................ 232

Table 7-2: M2P DMA Bus Arbitration................................................................................. 234

Table 7-3: DMA Memory Map............................................................................................ 235

Table 7-4: Internal M2P/P2M Channel Register Map ........................................................ 236

Table 7-5: PPALLOC Register Bits Decode for a Transmit Channel ............................ 239

Table 7-6: PPALLOC Register Bits Decode for a Receive Channel ................................. 239

Table 7-7: PPALLOC Register Reset Values ................................................................... 239

Table 7-8: M2M Channel Register Map ......................................................................... 245

Table 7-9: BWC Decode Values........................................................................................ 248

Table 7-10: DMA Global Interrupt (DMAGlInt) Register .................................................... 260

Table 8-1: OpenHCI Register Addresses ......................................................................... 273

Table 9-1: nXBLS[1:0] Multiplexing.................................................................................... 308

Table 9-2: WRITING to an External Memory System........................................................ 309

Table 9-3: SMC Register Map ........................................................................................... 310

Table 10-1: Boot Device Selection..................................................................................... 314

Table 10-2: Synchronous Memory Address Decoding ..................................................... 316

Table 10-3: General SDRAM Initialization Sequence ........................................................ 316

Table 10-4: Mode Register Command Decoding............................................................... 318

Table 10-5: Sync Memory CAS Settings ........................................................................... 318

Table 10-6: Sync Memory RAS, (Write) Burst Type Settings ............................................ 319

Table 10-7: Burst Length Settings ..................................................................................... 319

Table 10-8: Chip Select Decoding ..................................................................................... 321

Table 10-9: Memory System Examples ............................................................................. 322

Table 10-10: Memory Address Decoding for 256 Mbit, 16-Bit Wide, and

13-Row x 9-Column x 2-Bank Device ............................................................................. 322

Table 10-11: 16-Bit Wide Data Systems............................................................................ 322

Table 10-12: Synchronous Memory Controller Registers .................................................. 324

Table 10-13: Synchronous Memory Command Encoding ................................................. 326

Table 11-1: Receive FIFO Bit Functions............................................................................ 336

Table 11-2: Legal HDLC Mode Configurations ............................................................... 341

Table 11-3: HDLC Receive Address Matching Modes ...................................................... 344

Table 11-4: UART1 Pin Functionality ................................................................................ 346

Table 11-5: DeviceCfg Register Bit Functions .................................................................. 346

Table 12-1: UART2 / IrDA Modes ..................................................................................... 373

Table 12-2: IonU2 Pin Function ........................................................................................ 373

Table 13-1: Bit Values to Select Ir Module ........................................................................ 389

Table 13-2: Address Offsets for End-of-frame Data ......................................................... 391

Table 13-3: MIR Frame Format ......................................................................................... 396

Table 13-4: DeviceCfg.IonU2 Pin Function ................................................................... 407

Table 13-5: UART2 / IrDA Modes ..................................................................................... 408

Table 13-6: IrDA Service Memory Accesses / Second ................................................... 409

Table 14-1: Timers Register Map ...................................................................................... 427

Table 15-1: Register Memory Map ................................................................................ 435

Table 16-1: Register Memory Map ................................................................................. 443

Table 17-1: I

S Controller Input and Output Signals ......................................................... 448

Table 17-2: Audio Interfaces Pin Assignment ................................................................... 449

Table 17-3: I2SClkDiv SYSCON Register Effect on I2S Clock Generation ................... 457

Table 17-4: Bit Clock Rate Generation ........................................................................... 457

Table 17-5: FIFO Flags ..................................................................................................... 460

Table 17-6: I Table 17-7: I Table 17-8: I

S TX Registers .......................................................................................... 461

S RX Registers .......................................................................................... 465

S Configuration and Status Registers ......................................................... 469

Table 18-1: Register Memory Map ................................................................................. 480

Table 18-2: Interaction Between RSIZE and CM ......................................................... 482

Table 18-3: Interaction Between RSIZE and CM Bits ................................................... 484

Table 19-1: SSP Register Memory Map Description ......................................................... 510

Table 20-1: Register Memory Map ................................................................................. 518

Table 20-2: Table of ADCSwitch values ........................................................................... 520

Table 21-1: GPIO Port to Pin Map .................................................................................... 530

Table 21-2: GPIO Register Address Map .......................................................................... 531

Table 22-1: Security Register List ................................................................................. 554

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22 EP9301 User’s Manual - DS636UM2

1.1 Introduction

The EP9301 is a highly integrated system-on-chip processor that paves the way for a multitude of next-generation consumer and industrial electronic products. Designers of digital media servers and jukeboxes, telematic control systems, thin clients, set-top boxes, point-of-sale terminals, industrial controls, biometric security systems, and GPS devices will benefit from the EP9301’s integrated architecture and advanced features. In fact, with amazingly agile performance provided by a 166 MHz ARM920T processor, and featuring an incredibly wide breadth of peripheral interfaces, the EP9301 is well suited to an even broader range of high volume applications. Furthermore, by enabling or disabling the EP9301’s peripheral interfaces, designers can reduce development costs and accelerate time-to-market by creating a single platform that can be easily modified to deliver a variety of differentiated end products.

Figure 1-1. EP9301 Block Diagram

Chapter 1 1Introduction

Vectored Interrupt

Controllers (2)

Boot ROM

SDRAM

SRAM/

FLASH/ROM

12 Channel DMA

Engine

1/10/100 Ethernet

MAC

JTAG

USB Host, 2 Ports

1.2 EP9301 Features

The EP9301 system-on-chip processor has the following features:

AMBA High-Speed Bus (AHB)

UART1 w/ HDLC

UART2 w/ IrDA

ARM920T

I-Cache

D-Cache

16KB

AHB/APB

16KB

MMU

Bridge

S (IIS)

System Ctrl - PLLs (2)

Enhanced GPIO EEPROM, LED (2)

Watchdog Timer

AMBA Peripheral Bus (APB)

RTC with Trim

ADC

SPI

Timers

AC’97

Introduction

• 166 MHz ARM920T Processor

• 16 KByte data cache and 16 KByte instruction cache

• MMU enabling Linux

• 66 MHz system bus

™

• MaverickKey

• 32-bit unique ID

• 128-bit random ID

Integrated Peripheral Interfaces

• 1/10/100 Mbps Ethernet MAC

• Two-port USB 2.0 Full Speed host (OHCI)

• Two UARTs (16550 Type)

• IrDA interface, slow and fast mode

• Analog-to-Digital Converter (ADC)

• Serial Peripheral Interface (SPI) port

• AC ‘97 interface

IDs for Digital Rights Management or Design IP Security

and Windows® CE

• I2S interface, up to 2 channels

• External Memory Options

• 16-bit SDRAM interface, up to four banks

• 16/8-bit SRAM/Flash/ROM interface (I/F)

• Serial EEPROM interface

Internal Peripherals

• Real-Time clock with software trim

• 12 DMA channels for data transfer that maximizes system performance

•Boot ROM

• Dual PLLs control all clock domains

• Watchdog timer

• Two general purpose 16-bit timers

• General purpose 32-bit timer

• 40-bit debug timer

• General-Purpose I/Os

• 16 enhanced GPIOs including interrupt capability

24 EP9301 User’s Manual - DS636UM2

Introduction

• 31 additional optional GPIOs multiplexed on peripherals

• Available in 208-pin LQFP package

1.3 EP9301 Applications

The EP9301 can be used in a variety of applications, such as:

• Digital media servers

• Integrated home media gateways

• Digital audio jukeboxes

• Portable audio/video players

• Streaming audio/video players

• Telematic control systems

• Set-top boxes

• Point-of-sale terminals

• Thin clients

• Internet TVs

• Biometric security systems

• Industrial controls

• GPS & fleet management systems

• Educational toys

• Voting machines

• Medical equipment

1.4 Overview of EP9301 Features

1.4.1 High-Performance ARM920T Processor Core

The EP9301 features an advanced ARM920T processor design with an MMU that supports Linux®, Windows® CE, and many other embedded operating systems. The ARM920T’s 32-bit microcontroller architecture, with a five-stage pipeline, delivers impressive performance at very low power. The included 16 KByte instruction cache and 16 KByte data cache provide zero-cycle latency to the current program and data, or can be locked to provide guaranteed nolatency access to critical instructions and data. For applications with instruction memory size restrictions, the ARM920T’s compressed Thumb instruction set provides a space-efficient design that maximizes external instruction memory usage.

Introduction

1.4.2 MaverickKey™ Unique ID Secures Digital Content and OEM Designs

MaverickKey unique hardware programmed IDs provide an excellent solution to the growing concern over secure Web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs for DRM (Digital Rights Management) mechanisms.

MaverickKey uses a specific 32-bit ID and a 128-bit random ID that are programmed into the EP9301 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device that the EP9301 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by matching device IDs to server IDs.

MaverickKey IDs can also be used by OEMs and design houses to protect against design piracy by presetting ranges for unique IDs. For more information on securing your design using MaverickKey, please contact your Cirrus Logic sales representative.

1.4.3 Integrated Two-port USB 2.0 Full Speed Host with Transceivers

The EP9301 integrates two USB 2.0 Full Speed host ports. Fully compliant to the OHCI USB 2.0 Full Speed specification (12 Mbps), the host ports can be used to provide connections to a number of external devices including mass storage devices, external portable devices such as audio players or cameras, printers, or USB hubs. Naturally, the two-port USB host also supports the USB

2.0 Low Speed standard. This provides the opportunity to create a wide array of flexible system configurations.

1.4.4 Integrated Ethernet MAC Reduces BOM Costs

The EP9301 integrates a 1/10/100 Mbps Ethernet Media Access Controller (MAC) on the device. With a simple connection to an MII-based external PHY, an EP9301-based system has easy, high-performance, cost-effective Internet capability.

1.4.5 Multiple Booting Mechanisms Increase Flexibility

The processor includes a 16 KByte boot ROM to set up standard configurations. Optionally, the processor may be booted from FLASH memory, over the SPI serial interface, or through the UART. This boot flexibility makes it easy to design user-controlled, field-upgradable systems. See Chapter 3 on page 59, for additional details.

26 EP9301 User’s Manual - DS636UM2

Introduction

1.4.6 Abundant General Purpose I/Os Build Flexible Systems

The EP9301 includes both enhanced and standard general-purpose I/O pins (GPIOs). The 16 different enhanced GPIOs may individually be configured as inputs, outputs, or interrupt-enabled inputs. There are an additional 31 standard GPIOs that may individually be used as inputs, outputs, or opendrain pins. The standard GPIOs are multiplexed with peripheral function pins, so the number available depends on the utilization of peripherals. Together, the enhanced and standard GPIOs facilitate easy system design with external peripherals not integrated on the EP9301.

1.4.7 General-Purpose Memory Interface (SDRAM, SRAM, ROM and FLASH)

The EP9301 features a unified memory address model in which all memory devices are accessed over a common address/data bus. Memory accesses are performed via the high-speed processor bus. The SRAM memory controller supports 8 and 16-bit devices and accommodates an internal boot ROM concurrently with a 16-bit SDRAM memory.

1.4.8 12-Bit Analog-to-Digital Converter (ADC) Functionality

The EP9301 includes a 12-bit ADC, which can be used for general ADC functionality. The interface performs all sampling, averaging, ADC range checking, and control for a wide variety of applications. To improve system performance, the converter only interrupts the processor when a meaningful change occurs.

Introduction

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28 EP9301 User’s Manual - DS636UM2

Chapter 2 2ARM920T Core and Advanced High-Speed Bus (AHB)

2.1 Introduction

This section discusses the ARM920T processor core and the Advanced HighSpeed Bus (AHB).

2.2 Overview: ARM920T Processor Core

The ARM920T is a Harvard architecture processor core with separate 16 kbyte instruction and data caches with an 8-word line length used in the EP9301. The processor core utilizes a five-stage pipeline consisting of fetch, decode, execute, data memory access, and write stages.

2.2.1 Features

Key features include:

• ARM V4T (32-bit) and Thumb (16-bit compressed) instruction sets

• 32-bit Advanced Micro-Controller Bus Architecture (AMBA)

• 16 kbyte Instruction Cache with lockdown

• 16 kbyte Data Cache (programmable write-through or write-back) with lockdown

• Write Buffer

• MMU for Microsoft Windows CE and Linux operating systems

• Translation Look-aside Buffers (TLB) with 64 Data and 64 Instruction Entries

• Programmable Page Sizes of 64 kbyte, 4 kbyte, and 1 kbyte

• Independent lockdown of TLB Entries

• JTAG Interface for Debug Control

ARM920T Core and Advanced High-Speed Bus (AHB)

2.2.2 Block Diagram

Figure 2-1. ARM920T Block Diagram

External Co-Proc

Interface

JTAG

Instruction

cache

R13

ARM9TDMI

Processor core

(Integral

EmbeddedICE)

R13

Data cache Data MMU

Instruction

MMU

CP15

Write

Buffer

Write Back

PA TAG

RAM

AMBA

Bus

Int.

APB

2.2.3 Operations

The ARM920T core follows a Harvard architecture and consists of an ARM9TDMI core, MMU, instruction and data cache. The core supports both the 32-bit ARM and 16-bit Thumb instruction sets.

The internal bus structure (AMBA) includes both an internal high speed and external low speed bus. The high speed bus AHB (Advanced Highperformance Bus) contains a high speed internal bus clock to synchronize coprocessor, MMU, cache, DMA controller, and memory modules. AMBA includes a AHB/APB bridge to the lower speed APB (Advanced Peripheral Bus). The APB bus connects to lower speed peripheral devices such as UARTs and GPIOs.

The MMU provides memory address translation for all memory and peripherals designed to remap memory devices and peripheral address locations. Sections, large, small and tiny pages are programmable to map memory in 1 Mbyte, 64 kbyte, 4 kbyte, 1 kbyte size blocks. To increase system

30 EP9301 User’s Manual - DS636UM2

+ 526 hidden pages

Cirrus Logic EP9301 User's Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

EP9301 User’s Guide

About the EP9301 User’s Guide

How to Use this Guide

Preface

Related Documents from Cirrus Logic

Reference Documents

Notational Conventions

Table of Contents

List of Figures

List of Tables

1.1 Introduction

Chapter 1

1Introduction

1.2 EP9301 Features

1.3 EP9301 Applications

1.4 Overview of EP9301 Features

1.4.1 High-Performance ARM920T Processor Core

1.4.2 MaverickKey™ Unique ID Secures Digital Content and OEM Designs

1.4.3 Integrated Two-port USB 2.0 Full Speed Host with Transceivers

1.4.4 Integrated Ethernet MAC Reduces BOM Costs

1.4.5 Multiple Booting Mechanisms Increase Flexibility

1.4.6 Abundant General Purpose I/Os Build Flexible Systems

1.4.7 General-Purpose Memory Interface (SDRAM, SRAM, ROM and FLASH)

1.4.8 12-Bit Analog-to-Digital Converter (ADC) Functionality

Chapter 2

2ARM920T Core and Advanced High-Speed Bus (AHB)

2.1 Introduction

2.2 Overview: ARM920T Processor Core

2.2.1 Features

2.2.2 Block Diagram

2.2.3 Operations