Cirrus Logic EP73xx User Manual

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EP73xx User’s Guide

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Jan ‘04

DS508UM4

EP73xx User’s Guide Change Control Log

22 Jan 2004

Reason for entry The Users Guide has changed from Revision 3 (UM3) to Revision 4 (UM4). Significant Changes:

1. Typographical errors corrected.

2. Manual adapted for 90 MHz operation.

3. Crystal and PLL precision increased to 4 decimal points where applicable.

4. Distinction between 18-74 MHz (PLL) “mode” and precise “operation” frequency made. Example, at 90.3168 operating frequency the processor is in PLL, or 18-74 MHz, mode with a higher PLL Multiplier value.

5. Programming example on page 10-1 updated for consistency.

Updated Tables and Figures:

1. Revision 3, Chapter 5, ADCKSEL table on page 5-5 to 5-6 updated (Revision 4, new table is Table 5-3 on page 5-6.)

2. Revision 3, Chapter 8, Wait State tables on page 8-4 updated (Revision 4, new tables are Tabl e 8 -3 and Table 8-4 on

page 8-4.)

3. Revision 3, Chapter 9, Figure 9-2 on page 8-4, LCD Data to Pixel Mapping updated (Revision 4, new figure is Figure

9-2 on page 9-6.)

4. Revision 3, Chapter 15, Table 15-A on page 15-3, ADC Interface Operation Frequencies updated (Revision 4, new table is Table 15-2 on page 15-3.)

5. Revision 3, Chapter 16, Table 16-A on page 16-3, Matrix for Programming the MUX updated (Revision 4, new table is Table 16-2 on page 16-3.)

6. Revision 3, Chapter 16, Figure 16-2 on page 18-5), Digital Audio Clock Generation updated (Revision 4, new figure is Figure 16-2 on page 16-3.)

7. Revision 3, Chapter 16, Table 16-D on page 16-5, Programmable Audio Divisors for 74 MHz updated (Revision 4, new table is Table 16-5 on page 16-5.)

8. Revision 4, Chapter 16, Table 16-6 on page 16-6, Programmable Audio Divisors for 90 MHz added.

9. Revision 4, Chapter 17, Table 17-2 on page 17-2, UART Bit Rate at 90 MHz added.

Note: In the online version of this manual, you can click on cross-references that appear in blue text to jump

to the targetedreference.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsid iaries ("Cirrus") believe that the information contained in this document is accurate and reliab le. However, the information is subj ect to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest v ersion of relevant information to verify, before placing orders, that information be ing relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, MaverickKey ar e trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation.

LINUX is a registered trademark of Linus Torvalds.

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Chapter 1. Introduction

Overview............................................................................................................................................................ 1-1

Processor ..................................................................................................................................................... 1-1

Peripherals .................................................................................................................................................. 1-1

Memory Map and Register List............................................................................................................... 1-2

Pin Description........................................................................................................................................... 1-6

Block Diagrams ............................................................................................................................................... 1-11

References ................................................................................................................................................. 1-12

Chapter 2. CPU Core

Introduction....................................................................................................................................................... 2-1

Features .............................................................................................................................................................. 2-1

Programming Register List.............................................................................................................................. 2-1

Block Diagram...................................................................................................................................................2-2

Programming Examples ..................................................................................................................................2-2

Operational Overview...................................................................................................................................... 2-4

MMU............................................................................................................................................................ 2-4

TLB............................................................................................................................................................... 2-5

Cache ........................................................................................................................................................... 2-5

Write Buffer ................................................................................................................................................ 2-6

Debug Interface.......................................................................................................................................... 2-7

CPU Register Definitions................................................................................................................................. 2-7

ARM720T Core Coprocessor Registers................................................................................................... 2-8

CPU Clocks ................................................................................................................................................. 2-9

PLL Multiplier Write Register (PLLW) .............................................................................................. 2-11

PLL Multiplier Read Register (PLLR)............................................................................................... 2-11

CPU State Control.................................................................................................................................... 2-12

State Control Register Descriptions ............................................................................................................. 2-13

Enter the Standby State Register (STDBY)..................................................................................... 2-13

Enter the Idle State Register (HALT) ............................................................................................... 2-14

Power Up Sequence................................................................................................................................. 2-14

RESET ........................................................................................................................................................ 2-15

1Contents

Chapter 3. Timers

Introduction....................................................................................................................................................... 3-1

Features .............................................................................................................................................................. 3-1

Timer Register List............................................................................................................................................ 3-1

Programming Example .................................................................................................................................... 3-1

Operational Overview...................................................................................................................................... 3-2

Free Running Mode................................................................................................................................... 3-2

Prescale Mode ............................................................................................................................................ 3-3

RTC Timer...................................................................................................................................................3-3

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Timer Register Descriptions............................................................................................................................ 3-3

Timer Counter 1 Data Register (TC1D) ..............................................................................................3-3

Timer Counter 2 Data Register(TC2D)...............................................................................................3-3

Real Time Clock Data Register (RTCDR) ..........................................................................................3-3

Real Time Clock Match Register (RTCMR)........................................................................................3-4

Chapter 4. Interrupt Controller

Introduction....................................................................................................................................................... 4-1

Features .............................................................................................................................................................. 4-1

Interrupt Register List...................................................................................................................................... 4-1

Programming Examples .................................................................................................................................. 4-2

Operational Overview...................................................................................................................................... 4-3

Interrupt Types and Priorities ................................................................................................................. 4-4

Interrupt Operation................................................................................................................................... 4-4

Interrupt Listing......................................................................................................................................... 4-5

Interrupt Latencies in Different States.................................................................................................... 4-6

Interrupt Register Descriptions ...................................................................................................................... 4-8

Interrupt Status Register 1 (INTSR1) .................................................................................................4-8

Interrupt Mask Register 1 (INTMR1) ................................................................................................4-10

Interrupt Mask Register 2 (INTMR2) ................................................................................................4-12

Interrupt Status Register 3 (INTSR3) ...............................................................................................4-12

Interrupt Mask Register 3 (INTMR3) ................................................................................................4-13

Battery Low End of Interrupt (BLEOI) ...............................................................................................4-13

Media Change End of Interrupt (MCEOI) .........................................................................................4-13

Tick End of Interrupt (TEOI) .............................................................................................................4-13

TC1 End of Interrupt (TC1EOI).........................................................................................................4-13

TC1 End of Interrupt (TC2EOI).........................................................................................................4-14

RTC Match End of Interrupt (RTCEOI).............................................................................................4-14

UART1 Modem Status Changed End of Interrupt (UMSEOI)...........................................................4-14

CODEC End of Interrupt (COEOI) ....................................................................................................4-14

Keyboard End of Interrupt (KBDEOI) ...............................................................................................4-14

SSI2 FIFO Overflow End of Interrupt (SRXEOF) .............................................................................4-14

Chapter 5. System Registers

Introduction....................................................................................................................................................... 5-1

Features .............................................................................................................................................................. 5-1

System Register List ......................................................................................................................................... 5-2

Programming Example.................................................................................................................................... 5-2

Operational Overview...................................................................................................................................... 5-3

Buzzer.......................................................................................................................................................... 5-3

Debug Mode............................................................................................................................................... 5-3

System Control Register Descriptions ........................................................................................................... 5-4

System Control Register 1 (SYSCON1) .............................................................................................5-4

System Control Register 2 (SYSCON2) .............................................................................................5-7

System Control Register 3 (SYSCON3) .............................................................................................5-8

System Flag Register 1 (SYSFLG1)...................................................................................................5-9

System Flag Register 2 (SYSFLG2).................................................................................................5-12

Clear all Start-up Reason Flag Register (STFCLR) .........................................................................5-13

32-bit Unique ID Register (UNIQID) .................................................................................................5-13

Random ID 0 Register, bits 31-0 (RANDID0) ...................................................................................5-13

Random ID 1 Register, bits 63-32 (RANDID1) .................................................................................5-13

Random ID 2 Register, bits 95-64 (RANDID2) .................................................................................5-13

Random ID 3 Register, bits 127-96 (RANDID3) ...............................................................................5-13

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Chapter 6. Processor Support

Introduction....................................................................................................................................................... 6-1

Features .............................................................................................................................................................. 6-1

Operational Overview...................................................................................................................................... 6-1

Internal Boot Mode.................................................................................................................................... 6-2

External Boot Mode................................................................................................................................... 6-2

Endianess .................................................................................................................................................... 6-4

Chapter 7. SDRAM Controller

Introduction....................................................................................................................................................... 7-1

Features .............................................................................................................................................................. 7-1

SDRAM Register List........................................................................................................................................ 7-1

Programming Example .................................................................................................................................... 7-2

Operational Overview...................................................................................................................................... 7-2

System Initialization..................................................................................................................................7-2

Byte Masks .................................................................................................................................................. 7-3

SDRAM Register Descriptions........................................................................................................................ 7-3

SDRAM Control Register (SDCONF) ................................................................................................ 7-3

SDRAM Refresh Period Register (SDRFPR) .................................................................................... 7-4

Contents

Chapter 8. SRAM/Expansion Bus Controller

Introduction....................................................................................................................................................... 8-1

Features .............................................................................................................................................................. 8-1

SRAM / Expansion Bus Register List ............................................................................................................ 8-1

Programming Example .................................................................................................................................... 8-1

Operational Overview...................................................................................................................................... 8-2

SRAM / Expansion Bus Register Descriptions ............................................................................................ 8-3

Memory Configuration Register 1 (MEMCFG1)................................................................................. 8-3

Memory Configuration Register 2 (MEMCFG2)................................................................................. 8-5

Chapter 9. LCD Interface

Introduction....................................................................................................................................................... 9-1

Features .............................................................................................................................................................. 9-1

LCD Register List.............................................................................................................................................. 9-1

Programming Example .................................................................................................................................... 9-2

Operational Overview...................................................................................................................................... 9-2

LCD Controller External Memory........................................................................................................... 9-2

LCD DMA Controller................................................................................................................................ 9-3

Gray Scale ...................................................................................................................................................9-4

Hardware Interface.................................................................................................................................... 9-6

Color LCDs ................................................................................................................................................. 9-6

LCD Register Descriptions .............................................................................................................................. 9-7

LCD Control Register (LCDCON)...................................................................................................... 9-7

LCD Palette Registers ....................................................................................................................... 9-8

LCD Frame Buffer Start Address (FBADDR)..................................................................................... 9-9

Chapter 10. Keyboard Interface

Introduction..................................................................................................................................................... 10-1

Features ............................................................................................................................................................ 10-1

Register List ..................................................................................................................................................... 10-1

Programming Example .................................................................................................................................. 10-1

Operational Overview.................................................................................................................................... 10-2

Keyboard Interrupt Matrix..................................................................................................................... 10-2

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Contents

Chapter 11. General Purpose I/O (GPIO)

Introduction..................................................................................................................................................... 11-1

Features ............................................................................................................................................................ 11-1

General Purpose I/O (GPIO) Register List................................................................................................. 11-1

Programming Example.................................................................................................................................. 11-2

Operational Overview.................................................................................................................................... 11-2

Register Descriptions ..................................................................................................................................... 11-2

Chapter 12. PWM Interface

Introduction..................................................................................................................................................... 12-1

Features ............................................................................................................................................................ 12-1

Block Diagram................................................................................................................................................. 12-1

PWM (Pulse Width Modulator) Register List ............................................................................................12-2

Programming Example.................................................................................................................................. 12-2

Operational Overview.................................................................................................................................... 12-2

PWM Register Descriptions .......................................................................................................................... 12-3

Pump Control Register (PMPCON) ..................................................................................................12-3

Chapter 13. Dedicated LED Flasher

Introduction..................................................................................................................................................... 13-1

LED Flasher Register List .............................................................................................................................. 13-1

Programming Example.................................................................................................................................. 13-1

Operational Overview.................................................................................................................................... 13-1

Register Definitions ........................................................................................................................................ 13-2

LED Flasher Register (LEDFLSH) ....................................................................................................13-2

Chapter 14. JTAG Interface

Introduction..................................................................................................................................................... 14-1

Features ............................................................................................................................................................ 14-1

Operational Overview.................................................................................................................................... 14-1

Boundary Scan ......................................................................................................................................... 14-2

Debug Modes ........................................................................................................................................... 14-3

Software Selectable Test Functionality................................................................................................. 14-4

Chapter 15. SSI Port

Introduction..................................................................................................................................................... 15-1

Features ............................................................................................................................................................ 15-1

SSI Port Register List ...................................................................................................................................... 15-1

Programming Example.................................................................................................................................. 15-1

Operational Overview.................................................................................................................................... 15-2

SSI1/ADC Interface................................................................................................................................. 15-2

SSI Port Register Descriptions ...................................................................................................................... 15-4

Synchronous Serial ADC Interface Data Register (SYNCIO)...........................................................15-4

Chapter 16. DAI/CODEC/SSI2

Introduction..................................................................................................................................................... 16-1

Features ............................................................................................................................................................ 16-1

Block Diagram................................................................................................................................................. 16-2

DAI/CODEC/SSI2 Register List.................................................................................................................. 16-2

Programming Example.................................................................................................................................. 16-2

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Operational Overview.................................................................................................................................... 16-3

DAI/CODEC/SSI2 MUX ....................................................................................................................... 16-3

DAI Interface ............................................................................................................................................ 16-4

Master/Slave SSI2 Interface ................................................................................................................... 16-7

CODEC Sound Interface ....................................................................................................................... 16-10

DAI/CODEC/SSI2 Register Descriptions ................................................................................................ 16-11

DAI Mode Control Register (DAI64FS) .......................................................................................... 16-11

DAI Control Register (DAIR).......................................................................................................... 16-12

DAI Data Register 0 (DAIDR0) ...................................................................................................... 16-14

DAI Data Register 1 (DAIDR1) ...................................................................................................... 16-15

DAI Status Register (DAISR)......................................................................................................... 16-16

Synchronous Serial Interface 2 Data Register (SS2DR) ............................................................... 16-20

Synchronous Serial Interface 2 Pop Residual Byte (SS2POP) ..................................................... 16-20

CODEC Interface Data Register (CODR)...................................................................................... 16-20

Chapter 17. UART and SIR Encoder

Introduction..................................................................................................................................................... 17-1

Features ............................................................................................................................................................ 17-1

UART and SIR Encoder Register List .......................................................................................................... 17-1

Programming Example .................................................................................................................................. 17-1

Operational Overview.................................................................................................................................... 17-2

UART1....................................................................................................................................................... 17-3

SIR Encoder .............................................................................................................................................. 17-4

UART2....................................................................................................................................................... 17-4

UART and SIR Encoder Register Descriptions...........................................................................................17-5

UART Data Registers (UARTDR1 and UARTDR2) ......................................................................... 17-5

Bit Rate and Line Control Registers (UBRLCR1 and UBRLCR2) ................................................... 17-6

Contents

Appendix A. Boot Code

Index ................................................................................................................................................................... 1-1

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List of Figures

Figure 1-1. EP73xx Block Diagram ............................................................................................................... 1-11

Figure 1-2. Typical EP73xx System Block Diagram ................................................................................... 1-12

Figure 2-1. ARM720T B lock Diagram ............................................................................................................ 2-2

Figure 2-2. ARM720T Cache Organization. .................................................................................................. 2-6

Figure 2-3. Register Organization Summary ................................................................................................ 2-8

Figure 2-4. State Diagram .............................................................................................................................. 2-12

Figure 9-1. Pixel Gray Scale Mapping............................................................................................................ 9-5

Figure 9-2. LCD Data to Pixel Mapping ........................................................................................................ 9-6

Figure 12-1. Block Diagram of a Power Supply Using Two PWM Drives ............................................. 12-1

Figure 16-1. Portion of the EP73xx Block Diagram Showing Multiplexed Feature .............................. 16-2

Figure 16-2. Digital Audio Clock Generation ............................................................................................. 16-5

Figure 16-3. SSI2 Port Directions in Slave and Master Mode ................................................................... 16-8

Figure 16-4. Residual Byte Reading.............................................................................................................. 16-9

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List of Tables

Table 1-1: EP73xx Memory Map in External Boot Mode ............................................................................ 1-2

Table 1-2: EP73xx Internal Registers (Little Endian Mode) ........................................................................ 1-4

Table 1-3: EP73xx Internal Registers (Big Endian Mode)............................................................................ 1-6

Table 1-4: External Signal Functions .............................................................................................................. 1-7

Table 1-5: SSI/CODEC/DAI Pin Multiplexing .......................................................................................... 1-10

Table 1-6: Output Bi-Directional Pins .......................................................................................................... 1-10

Table 2-1: Programming Registers ................................................................................................................. 2-1

Table 2-2: ARM720T Core Coprocessor Registers........................................................................................2-9

Table 2-3: Status of Peripherals and Clocks by Operating State .............................................................. 2-14

Table 3-1: Timer Registers................................................................................................................................ 3-1

Table 4-1: Interrupt Registers .......................................................................................................................... 4-1

Table 4-2: Vector Addresses by Interrupt Type............................................................................................4-3

Table 4-3: Exception Priority Handling ......................................................................................................... 4-4

Table 4-4: Interrupt Allocation in the First Interrupt Register ................................................................... 4-5

Table 4-5: Interrupt Allocation in the Second Interrupt Register .............................................................. 4-5

Table 4-6: Interrupt Allocation in the Third Interrupt Register ................................................................. 4-5

Table 4-7: External Interrupt Sources............................................................................................................. 4-7

Table 5-1: System Registers ............................................................................................................................. 5-2

Table 5-2: Keyboard Column Drive State...................................................................................................... 5-4

Table 5-3: ADC Sample Clock Settings.......................................................................................................... 5-6

Table 5-4: ARM720T Clock Speed Settings ................................................................................................... 5-9

Table 5-5: Default (Power-on Reset) Bus Width Settings.......................................................................... 5-11

Table 6-1: Chip Select Address Ranges for On-Chip Boot ROM ............................................................... 6-2

Table 6-2: Boot Options .................................................................................................................................... 6-2

Table 6-3: Memory Map in External Boot Mode .......................................................................................... 6-3

Table 6-4: Effect of Endianess on Read Operations......................................................................................6-4

Table 6-5: Effect on Endianess on Write Operations.................................................................................... 6-4

Table 7-1: SDRAM Registers ........................................................................................................................... 7-1

Table 8-1: SRAM / Expansion Bus Registers................................................................................................ 8-1

Table 8-2: Bus Width Selection Settings......................................................................................................... 8-3

Table 8-3: Wait States at 13 / 18 MHz Operation......................................................................................... 8-4

Table 8-4: Wait States at 36 MHz Operation ................................................................................................. 8-4

Table 9-1: LCD Registers..................................................................................................................................9-1

Table 9-2: Gray Scale Value to Color Mapping ............................................................................................ 9-9

Table 11-1: General Purpose I/O (GPIO) Registers ................................................................................... 11-1

Table 12-1: PWM (Pulse Width Modulator) Registers .............................................................................. 12-2

Table 12-2: PWM Pump Drive Settings ....................................................................................................... 12-3

Table 13-1: LED Flasher Registers ................................................................................................................ 13-1

Table 14-1: Instructions Supported in JTAG Mode.................................................................................... 14-2

Table 14-2: EP73xx Hardware Test Modes.................................................................................................. 14-3

Table 14-3: Oscillator and PLL Test Mode Signals.................... ....................................... .......................... 14-4

Table 14-4: Software Selectable Test Functionality .................................................................................... 14-4

Table 15-1: SSI Port Registers ........................................................................................................................ 15-1

Table 15-2: ADC Interface Operation Frequencies..................................................................................... 15-3

Table 16-1: DAI/CODEC/SSI2 Registers.................................................................................................... 16-2

Table 16-2: Matrix for Programming the MUX........................................................................................... 16-3

Table 16-3: Pin Sharing for Multiplexor....................................................................................................... 16-4

Table 16-4: Communication Interface Performance................................................................................... 16-4

Table 16-5: Programmable Audio Divisors at 74 MHz ............................................................................. 16-5

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Table 16-6: Programmable Audio Divisors at 90 MHz ............................................................................. 16-6

Table 17-1: UART and SIR Encoder Registers ............................................................................................17-1

Table 17-2: UART Bit Rates at 90 MHz ........................................................................................................ 17-2

Table 17-3: UART Bit Rate in PLL Clock Mode (74 MHz) ........................................................................ 17-3

Table 17-4: UART Bit Rate from 13 MHz Clock ......................................................................................... 17-3

Table 17-5: Word Length Selection............................................................................................................... 17-6

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Overview

Processor

Chapter 1

1Introduction

This chapter describes the EP73xx ARM processor, mem ory map, registers, an d signals. See the data sheet that is associated with a specific EP73xx device for more informationaboutpinassignmentsforthatproduct.

The EP73xx incorporates an ARM 32-bit RISC m icro controller that controls a wide range of on-chip peripherals.The ARM720T includes a a 8 Kbytes unified cache and a MMU compatible with operating systems like Windows

CE and Linux®.

Peripherals

See the A RM 720T Technical Reference Manual, as cited on page 1-12.

On-chip EP73xx peripherals are product-specific for each chip. The supersetof available features includes:

• 48 Kbytes of on-chip SRAM th at can be shared b etween the LCD controller and general application use

• Memory interfaces (chip selects) for up to six independent 256 M byte expansion segments with programmable width and wait states

• 27 general purpose Input/Outputs.

• Digital Audio Interface (DAI) to interface with CD-quality DACs and CODECs

• Interrupt Controller

• Advanced system state controller and power management

• Two full-duplex 16550 A compatible UARTs with 16-byte transmit and receive FIFOs.

• IrDA SIR protocol controller capable of speeds up to 115.2 kbps

• Programmable LCD controller for 1,2 or 4-bit-per-pixel with 16-level grayscaler and frame buffer start address.

• On-chip boot ROM programmed for serial port download of boot code.

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Introduction

• Two 16-bit general purpose timer counters

• 32-bit RTC (Real-Time-Clock) timer and comparator

• Dedicated LED flasher pin driven from the RTC with programmable du ty ratio (Multiplexed with GPIO pin)

• Two synchronous serial interfaces for M icro-wire or SPI interfaces s uch as ADCs, one supporting both the master and slave and other supporting only master mode.

• Two programmable PWM (Pulse Width Modulation) interfaces

• SDRAM i nterface for direct interface to a maximum of two external banks of SDRAM memory. Each bank can be up to 256 Mbit in size and configurable for 32 or 16-bit wide accesses.

• PLL (Phase Lock Loop) oscillator for generating core speeds of 18-90 MHz from an external 3.6864 MHz crystal.

• Low power 32.768 kHz RTC (Real Time Clock)

• MaverickKey - Unique and Random IDs for SDMI compliance

Memory Map and Register List

The lower 2 GByte of the address space is allocated to memory. The 64 MByte of address space from 0xC000.0000 to 0xCFFF.FFFF is allocated to SDRAM. About

1.5 GBytes of address space, less 8 Kbytes for internal registers, is not accessible in the EP73xx. The M MU in the EP73xx should be programmed to g enerate an abort exception for access to this area.

Internal peripherals are addressed through a set of internal memory l oca tions from hex address 0x8000.0000 to 0x8000.3FFF. These are known as the internal registers in the EP73xx. In Table 1-1 also shows how the 4-Gbyte address range of the ARM720T processor (as configured within this chip) is mapped in the EP73xx. The external boot ROM is not fully decoded (i.e., the b oot code will repeat within the 256-Mbyte space from 0x7000.0000 to 0x8000.0000). See Table 6-1 on page 6-2 for the m emory map when booted from on-chip boot ROM. The SRAM is fully decoded up to a maximum size of 48 Kbytes. Access to any location above this range will be wrapped to within the range.

Global Memory Map

Table 1-1: EP73xx Memory Map in External Boot Mode

Address Contents Size

0xF000.0000 Reserved 256 Mbytes

0xE000.0000 Reserved 256 Mbytes

0xD000.0000 Reserved 256 Mbytes

0xC000.0000 SDRAM 64 Mbytes

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Table 1-1: EP73xx Memory Map in External Boot Mode (Continued)

Address Contents Size

0x8000.4000 Unused ~1 Gbyte

0x8000.0000 Internal registers 8 Kbytes

0x7000.0000 Boot ROM (nCS[7]) 128 bytes

0x6000.0000 SRAM (nCS[6]) 48 Kbytes

0x5000.0000 Expansion (nCS[5]) 256 Mbytes

0x4000.0000 Expansion (nCS[4]) 256 Mbytes

0x3000.0000 Expansion (nCS[3]) 256 Mbytes

0x2000.0000 Expansion (nCS[2]) 256 Mbytes

0x1000.0000 ROM Bank 1 (nCS[1]) 256 Mbytes

0x0000.0000 ROM Bank 0 (nCS[0]) 256 Mbytes

Internal Register Map

Table 1-2 on page 1-4 shows the Internal Registers of the EP73xx when the CPU is

configured to a little endian memory system. Table 1-3 on page 1-6 shows the differences that occur when the CPU is configuredto a big endian memorysystemfor byte-wide access to Ports A, B, an d D. All the internal registers are inherently little endian (i.e., the least significant byte is attached to bits 7 to 0 of the data bus). Hence, the system Endianness affects the addresses required for byte accesses to the internal registers, resulting in a reversal of th e byte address required to read/write a particular byte within a register.

Introduction

There is no effect on the register addresses for word accesses. Bits internal address bus are only decoded for Ports A, B, and D (to allow read/write to individual ports). For all other registers,bits will return the whole register contents onto the E P 73xx’s intern al bus, from where the appropriate byte (according to the en dianness) will be read by the CPU. To avoid the additional c omplexity, it is preferable to perform all internal register accesses as word operations, except for ports A to D which are explicitly designed to operate with byte accesses, as well as with w ord ac cesses.

An 8 Kbytes segment of memory in the range 0x8000.0000 to 0x8000.3FFF is reserved for internal use in the EP73xx. Accesses in this range will not cause any external bus activity unless debug mode is enabled. Writes to bits that are not explicitly defined in the internal area are legal and will have no effect. Reads from bits not explicitly defined in the internal area are legal but will read undefined values. A ll the internal addresses s hould only be ac cessed as 32-bit words an d are always on a word boundary, except for the GPIO port registers, which can be accessed as bytes. A ddress bits in the range internal register is valid for 64 bytes (i.e., the SYSFLG1 register appears at locations 0x8000.0140 to 0x8000.017C). There are some gaps in the register map for backward compatibility reasons, but registers located next to a gap are still only decoded for 64 bytes.

The GPIO port registers are byte-wide and can be accessed as a word but not as a halfword. These registers additionally decode notation.

A[0-5] are not decoded (except for Ports A–D), this means each

A[0-1] arenot decoded, s o that byte reads

A[0-1]. All addresses are in hexadecimal

A[0-1] of the

EP7309/11/12 User’s Manual - DS508UM4 1-3



Introduction

Note: All byte-wideregisters should be accessed as words (except Port A to Port D

registers, which are designed to work in both word and byte modes). All registers bit alignment starts from the LSB of the register (i.e., they are all right shift justified). The registers which interact with the 32 kHz clock or which could change during readback (i.e., RTC data registers, SYSFLG1 register (lower 6-bits only), the TC1D and TC2D data registers,port registers, and interrupt status registers), should be read twice and comparedto ensure that a stable value has been read back.

All internal registers in the EP73xx are reset (cleared to zero) by a system reset (i.e.,

nPOR, nRESET,ornPWRFL signals becoming active), and the Real Time Clock data

nPOR

becoming active. This ensures that the system time preserved through a user reset or power fail condition. In the following register descriptions, little endian is assumed.

Table 1-2: EP73xx Internal Registers (Little Endian Mode)

Address Name Default RD/WR Size Comments Page

0x8000.0000 PADR 0 RW 8 Port A data register page 11-1

0x8000.0001 PBDR 0 RW 8 Port B data register page 11-1

0x8000.0002 ——8Reserved

0x8000.0003 PDDR 0 RW 8 Port D data register page 11-1

0x8000.0040 PADDR 0 RW 8 Port A data direction register page 11-1

0x8000.0041 PBDDR 0 RW 8 Port B data direction register page 11-1

0x8000.0042 ——8Reserved

0x8000.0043 PDDDR 0 RW 8 Port D data direction register page 11-1

0x8000.0080 PEDR 0 RW 3 Port E data register page 11-1

0x8000.00C0 PEDDR 0 RW 3 Port E data direction register page 11-1

0x8000.0100 SYSCON1 0 RW 32 System control register 1 page 5-4

0x8000.0140 SYSFLG1 0 RD 32 System status flags register 1 page 5-9

0x8000.0180 MEMCFG1 0 RW 32 Expansion memory configuration register 1 page 8-3

0x8000.01C0 MEMCFG2 0 RW 32 Expansion memory configuration register 2 page 8-5

0x8000.0200 0 RW 32 Reserved

0x8000.0240 INTSR1 0 RD 32 Interrupt status register 1 page 4-8

0x8000.0280 INTMR1 0 RW 32 Interrupt mask register 1 page 4-10

0x8000.02C0 LCDCON 0 RW 32 LCD control register page 9-7

0x8000.0300 TC1D 0 RW 16 Read / Write register sets and reads data to TC1 page 3-3

0x8000.0340 TC2D 0 RW 16 Read / Write register sets and reads data to TC2 page 3-3

0x8000.0380 RTCDR — RW 32 Real Time Clock data register page 3-3

0x8000.03C0 RTCMR — RW 32 Real Time Clock match register page 3-4

0x8000.0400 PMPC ON 0 RW 12 PWM pump control register page 12-3

0x8000.0440 CODR 0 RW 8 CODEC data I/O register page 16-20

0x8000.0480 UARTDR1 0 RW 16 UART1 FIFO data register page 17-5

0x8000.04C0 UBRLCR1 0 RW 32 UART1 bit rate and line control register page 17-6

0x8000.0500 SYNCIO 0 RW 32 Synchronous serial I/O data register for master only SSI page 15-4

1-4 EP7309/11/12 User’s Manual - DS508UM4



Introduction

Table 1-2: EP73xx Internal Registers (Little Endian Mode) (Continued)

Address Name Default RD/WR Size Comments Page

0x8000.0540 PALLSW 0 RW 32 Least significant 32-bit word of LCD palette register page 9-8

0x8000.0580 PALMSW 0 RW 32 Most significant 32-bit word of LCD palette register page 9-8

0x8000.05C0 STFCLR — WR — Write to clear all start up reason flags page 5-13

0x8000.0600 BLEOI — WR — Write to clear battery low interrupt page 4-13

0x8000.0640 MCEOI — WR — Write to clear media changed interrupt page 4-13

0x8000.0680 TEOI — WR — Write to clear tick and watchdog interrupt page 4-13

0x8000.06C0 TC1EOI — WR — Write to clear TC1 interrupt page 4-13

0x8000.0700 TC2EOI — WR — Write to clear TC2 interrupt page 4-14

0x8000.0740 RTCEOI — WR — Write to clear RTC match interrupt page 4-14

0x8000.0780 UMSEOI — WR — Write to clear UART modem status changed interrupt page 4-14

0x8000.07C0 COEOI — WR — Write to clear CODEC sound interrupt page 4-14

0x8000.0800 HALT — WR — Write to enter the Idle State page 2-14

0x8000.0840 STDBY — WR — Write to enter the Standby State page 2-13

0x8000.0880–

0x8000.0FFF

0x8000.1000 FBADDR 0xC RW 4 LCD frame buffer start address page 9-9

0x8000.1100 SYSCON2 0 RW 16 System control register 2 page 5-7

0x8000.1140 SYSFLG2 0 RD 24 System status register 2 page 5-12

0x8000.1240 INTSR2 0 RD 16 Interrupt status register 2 page 4-11

0x8000.1280 INTMR2 0 RW 16 Interrupt mask register 2 page 4-12

0x8000.12C0–

0x8000.147F

0x8000.1480 UARTDR2 0 RW 16 UART2 Data Register page 17-5

0x8000.14C0 UBRLCR2 0 RW 32 UART2 bit rate and line control register page 17-6

0x8000.1500 SS2DR 0 RW 16 Master / slave SSI2 data Register page 16-20

0x8000.1600 SRXEOF — WR — Write to clear RX FIFO overflow flag page 4-14

0x8000.16C0 SS2POP — WR — Write to pop SSI2 residual byte into RX FIFO page 16-20

0x8000.1700 KBDEOI — WR — Write to clear keyboard interrupt page 4-14

0x8000.1800 Reserved — WR —

0x8000.1840–

0x8000.1FFF

0x8000.2000 DAIR 0 RW 32 DAI control register page 16-12

0x8000.2040 DAIR0 0 RW 32 DAI data register 0 page 16-14

0x8000.2080 DAIDR1 0 RW 32 DAI data register 1 page 16-15

0x8000.20C0 DAIDR2 0 WR 21 DAI data register 2 page 16-16

0x8000.2100 DAISR 0 RW 32 DAI status register page 16-16

0x8000.2200 SYSCON3 0 RW 16 System control register 3 page 5-8

0x8000.2240 INTSR3 0 RD 32 Interrupt status register 3 page 4-12

0x8000.2280 INTMR3 0 RW 8 Interrupt mask register 3 page 4-13

Reser ved Write will have no effect, read is undefined

Do not write to this location. A write will cause the processor to go into an unsupported power savings state.

Reserved — Write will have no effect, read is undefined

EP7309/11/12 User’s Manual - DS508UM4 1-5



Introduction

Table 1-2: EP73xx Internal Registers (Little Endian Mode) (Continued)

Address Name Default RD/WR Size Comments Page

0x8000.22C0 LEDFLSH 0 RW 7 LED Flash register page 13-2

0x8000.2300 SDCONF 2 RW 32 SDRAM Configuration Register page 7-3

0x8000.2340 SDRFPR 128 RW 16 SDRAM Refresh Register page 7-4

0x8000.2440 UNIQID 0 R 32 32-bit unique ID for the EP73xx device page 5-13

0x8000.2600 DAI64Fs 0 RW 32 DAI 64Fs Control Register page 16-11

0x8000.2610 PLLW W 8 Write Register for PLL Multiplier page 2-11

0x8000.A5A8 PLLR R Read Register for PLL Multiplier page 2-11

0x8000.2700 RANDID0 0 R 32 Bits 31-0 of 128-bit random ID for the EP73xx device page 5-13

0x8000.2704 RANDID1 0 R 32 Bits 63-32 of 128-bit random ID for the EP73xx device page 5-13

0x8000.2708 RANDID2 0 R 32 Bits 95-64 of 128-bit random ID for the EP73xx device page 5-13

0x8000.270C RANDID3 0 R 32 Bits 127-96 of 128-bit random ID for the EP73xx device page 5-13

All other address

space that is not

assigned to a

this table

Reserved

All addresses that are outside the address space of the registers listed in this table are reserved. The undefined areas contain test registers used during manufacturing tests. Writes to this area should never be attempted during normal operation as this may cause unexpected behavior. Any read from this register will be undefined.

Table 1-3: EP73xx Internal Registers (Big Endian Mode)

Big Endian Mode Name Default RD/WR Size Comments

0x0000.0083 PEDR 0 RW 3 Port E Data Register

0X8000.00C3 PEDDR 0 RW 3 Port E Data Direction Register

0x8000.0000 PDDR 0 RW 8 Port D Data Register

0x8000.0001 ——8Reserved

0x8000.0002 PBDR 0 RW 8 Port B Data Register

0x8000.0003 PADR 0 RW 8 Port A Data Register

0x8000.0040 PDDDR 0 RW 8 Port D Data Direction Register

0x8000.0041 ——8Reserved

0x8000.0042 PBDDR 0 RW 8 Port B Data Direction Register

0x8000.0043 PADDR 0 RW 8 Port A data Direction Register

Pin Description

Table 1-4 on page 1-7 describes the function of all external signals to the EP 73xx. Note

that all output signals and all I/O pins ( when acting as ou tputs) are High-Z capable. This is to enable the High-Z test modes to be supported.

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

External Signal Functions

Table 1-4: External Signal Functions

Function Signal Name Signal Description

Introduction

Data bus D[0-31] I/O 32-bit system data bus for memory, SDRAM, and I/O interface

A[0-31] O 32 bits of system byte address during memory and expansion cycles

DRA[0-14] are multiplexed with A[27-13] for SDRAM memory accesses. A27 corresponds to DRA0 on SDRAM device. This offers additional power savings since

Address bus

Memory Interface

A[27-13]/

DRA[0-14]

BA[0-1]/ A[13-14]

nMOE/nSDCAS O ROM expansion OP enable/ SDRAM CAS control signal

nMWE/nSDWE O ROM expansion write enable/ SDRAM write enable control signal

nCS[0-5] O Chip select; active low, SRAM-like chip selects for expansion

SDQM[0-1] O LDQM; lower byte masks for SDRAM accesses

SDQM[2-3] O UDQM; upper byte masks for SDRAM/ multiplexed with PD[6-7]. See GPIO section

SDCS[0-1] O SDRAM chip selects

EXPRDY I

WRITE/nSDRAS O

the lightest loading is expected on the high order ROM address lines. Whenever the EP73xx is in the Standby State, the external address and data buses

are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to prevent peripherals that are powered-down from draining current. Also, the internal peripheral’s signals get set to their Reset State.

I/O A13 and A14, during SDRAM accesses, become bank select pins BA0 and BA1.

Expansion port ready; external expansion devices dr ive this low to extend the bus cycle. This is used to inser t wait states for an external bus cycle.

Transfer Direction for expansion bus/SDRAM RAS control signal during SDRAM access

To do write accesses of different sizes Word and Half-Word must be externally decoded. The encoding of these signals is as follows:

Access Size Word Half-Word

Word 1 0

Half-Word 0 1

WORD/

HALFWORD

EP7309/11/12 User’s Manual - DS508UM4 1-7

The core will generate an address. When doing a read, the ARM core will select the appropriate byte channels. When doing a write, the correct bytes will have to be enabled depending on the above signals and the least significant bits of the address bus.

The ARM architecture does not support unaligned accesses. For a read using x 32 memor y, it is assumed that you will ignore bits 1 and 0 of the address bus and perform a word read (or in power critical systems decode the relevant bits depending on the size of the access). If an unaligned read takes place, the core will rotate the resulting data in the register. For more information on this behavior see the LDR instruction in the ARM7TDMI data sheet.



Byte 0 0

Introduction

Table 1-4: External Signal Functions (Continued)

Function Signal Name Signal Description

Expansion clock rate is the same as the CPU clock for 13 MHz and 18 MHz. It runs

External Clock EXPCLK I/O

nMEDCHG/

nBROM

Interrupts

Power

Management

State Control

nEXTFIQ I External active low fast interrupt request input

EINT[3] I External active high interrupt request input

nEINT[1-2] I Two general purpose, active low interrupt inputs

nPWRFL

nEXTPWR I

nBATCHG

RUN/CLKEN O

WAKEUP

BATOK

nPOR I

at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is used as the clock input.

Media changed input; active low, deglitched. Used as a general purpose FIQ interrupt during normal operation. It is also used on power up to configure the

processor to either boot from the internal Boot ROM, or from external memory. When low, the chip will boot from the internal Boot ROM.

I Power fail input; active low, deglitched input to force system into the Standby State

Main battery OK input; falling edge generates a FIQ, a low level in the Standby State

inhibits system star t up; deglitched input

External power sense; must be driven low if the system is powered by an external source

New battery sense; driven low if battery voltage falls below the "no-battery"

threshold; it is a deglitched input

Power-on reset input. This signal is not deglitched. When active it completely resets the entire system, including all the RTC registers. Upon power-up, the signal must be held active low for a minimum of 100 µsec. after V

operation, nPOR needs to be held low for at least one clock cycle of the selected clock speed (i.e., when running at 13 MHz, the pulse width of nPOR needs to be > 77 nsec). Note that nURESET, TEST[0], TEST[1], PE[0], PE[1], PE[2], DRIVE[0], DRIVE[1], nMEDCHG, are all latched on the rising edge of nPOR.

This pin is programmed to either output the RUN signal or the CLKEN signal. The CLKENSL bit is used to configure this pin. When RUN is selected, the pin will be high when the system is active or idle, low while in the Standby State. When CLKEN is selected, the pin will only be driven low when in the Standby State (For RUN, see

Table 1-6 on page 1-10).

Wake up is a deglitched input signal. It must also be held high for at least 125 µsec to guarantee its detection. Once detected it forces the system into the Operating State from the Standby State. It is only active when the system is in the Standby State. This pin is ignored when the system is in the Idle or Operating State. It is used to

wakeup the system after first power-up, or after software has forced the system into the Standby State. WAKEUP will be ignored for up to two seconds after nPOR goes HIGH. Therefore, the external WAKEUP logic must be designed to allow it to rise and stay HIGH for at least 125 usec, two seconds after nPOR goes HIGH.

User reset input; active low deglitched input from user reset button.

has settled. During normal

DAI, CODEC or

SSI2 Interface

(See Table 1-5 on

page 1-10 for pin

assignment and

direction following

multiplexing)

nURESET

SSICLK I/O DAI/CODEC/SSI2 clock signal

SSITXFR I/O DAI/CODEC/SSI2 serial data output frame/synchronization pulse output

SSITXDA O DAI/CODEC/SSI2 serial data output

SSIRXDA I DAI/CODEC/SSI2 serial data input

SSIRXFR I/O

This pin is also latched upon the rising edge of nPOR and read along with the input pins nTEST[0-1] to force the device into special test modes. nURESET does not reset the RTC.

SSI2 serial data input frame/synchronization pulse DAI/CODEC external clock input

1-8 EP7309/11/12 User’s Manual - DS508UM4



Table 1-4: External Signal Functions (Continued)

Function Signal Name Signal Description

ADCCLK O Serial clock output

ADC

Interface

(SSI1)

IrDA and

RS232

Interfaces

LCD

Keyboard & Buzzer drive LED Flasher

General

Purpose I/O

PWM

Drives

nADCCS O Chip select for ADC interface

ADCOUT O Serial data output

ADCIN I Serial data input

SMPCLK O Sample clock output

LEDDRV O Infrared LED drive output (UART1)

PHDIN I Photo diode input (UART1)

TXD[1-2] O RS232 UART1 and 2 TX outputs

RXD[1-2] I RS232 UART1 and 2 RX inputs

DSR I RS232 DSR input

DCD I RS232 DCD input

CTS I RS232 CTS input

DD[0-3] I/O

CL[1] O LCD line clock

CL[2] O LCD pixel clock

FRM O LCD frame synchronization pulse output

M O LCD AC bias drive

COL[0-7] O Keyboard column drives (SYSCON1)

BUZ O Buzzer drive output (SYSCON1)

PD[0]/

LEDFLSH

PA[0-7] I/O Port A I/O (bit 6 for boot clock option); also used as keyboard row inputs

PB[0-7] I/O Port B I/O. All eight Port B bits can be used as GPIOs.

PD[0-5] I/O Port D I/O / PD0 multiplexed at LEDFLSH. See above.

PD[6-7]/SDQM

[0-1]

PE[0]/

BOOTSEL[0]

PE[1]/

BOOTSEL[1]

PE[2]/

CLKSEL

DRIVE[0-1] I/O

FB[0-1] I PWM feedback inputs

LCD serial display data; pins can be used on power up to read the ID of some LCD modules (See Table 1-6 on page 1-10).

LED flasher driver — multiplexed with Port D bit 0. This pin can provide up to 4 mA

of drive current.

I/O Port D I/O/dedicated byte mask select for SDRAM

Port E I/O (3 bits only). Can be used as general purpose I/O dur ing normal

I/O

operation.

During power-on reset, PE[0] and PE[1] are inputs and are latched by the rising edge

I/O

of nPOR to select the memory width that the EP73xx will use to read from the boot code storage device (i.e., external 8-bit-wide FLASH bank).

During power-on reset, PE[2] is latched by the rising edge of nPOR to select the

I/O

clock mode of operation (i.e., either the PLL or external 13 MHz clock mode).

PWM drive outputs. These pins are inputs on power up to determine what polarity the output of the PWM should be when active. Otherwise, these pins are always an output (See Table 1-6 on page 1-10).

Introduction

EP7309/11/12 User’s Manual - DS508UM4 1-9



Introduction

Table 1-4: External Signal Functions (Continued)

Function Signal Name Signal Description

TDI I JTAG data in

TDO O JTAG data out

Boundary

Scan

Test nTEST[0-1] I

Oscillators

No Connects N/C No connects should be left as no connects; do not connect to ground

1. All deglitched inputs are via the 16.384 kHz clock. Each deglitched signal must be held active for at least two clock periods. Therefore, the input signal must be active for at least ~125 µs to be detected cleanly.

The RTC crystal must be populated for the device to function properly.

TMS I JTAG mode select

TCLK I JTAG clock

nTRST I JTAG async reset

Test mode select inputs. These pins are used in conjunction with the power-on latched state of nURESET to select between the various device test models.

MOSCIN

MOSCOUT

RTCIN

RTCOUT

Main 3.6864 MHz oscillator for 18.432 MHz–90.3168 MHz PLL

Real Time Clock 32.768 kHz oscillator

DAI/CODEC/SSI2 Pin Multiplexing

Table 1-5: SSI/CODEC/DAI Pin Multiplexing

SSI2 CODEC DAI Direction Strength

SSICLK PCMCLK SCLK I/O 1

SSITXFR PCMSYNC LRCK I/O 1

SSITXDA PCMOUT SDOUT Output 1

SSIRXDA PCMIN SDIN Input

SSIRXFR p/u* MCLK I/O 1

* p/u = use an ~10 k pull-up

The selection between SSI2 an d the CO DEC is controlled by the state of the SER SEL bit in SYSCON2 (See SYSCON2 System Control Register 2). The choice between the SSI2, CODEC, and the DAI is controlled by the DAISEL bit in SYSCON3 (See “System

Control Register 3 (SYSCON3)” on page 5-8).

Output B i-Directional Pins

Table 1-6: Output Bi-Directional Pins

RUN

The RUN pin is looped back in to skew the address and data bus from each other.

Drive [0-1]

DD[0-3]

The above output pins are implemented as bi-directional pins to enable the output side of the pad to be monitored and

1-10 EP7309/11/12 User’s Manual - DS508UM4

Drive 0 and 1 are looped back in on power up to determine what polarity the output of the PWM should be when active.

DD[0-3] are looped back on power up to bits 7:4 of the SYSFLG1 register. Pin values are latched upon the enabling of the LCD Controller via the LCDEN bit. This is useful for reading the panel ID of some LCD modules. When some LCD modules are reset, they will output a panel ID onto these pins. See the SYSFLG1 register for more information.

hence provide more accurate control of timing or duration.



Block Diagrams

Introduction

13-MHz INPUT

3.6864 MHz

32.768 kHz

nPOR, RUN,

RESET, WAKEUP

BATOK, EXTPWR

PWRFL, BATCHG

EINT[1-3], FIQ,

MEDCHG

FLASHING LED DRIVE

PORTS A, B, D (8-BIT)

PORT E (3-BIT)

KEYBD DRIVERS (0-7)

DC TO DC

ADCCLK, ADCIN,

ADCOUT,

SMPCLK, ADCCS

SSICLK, SSITXFR,

SSITXDA, SSIRXDA,

SSIRSFR

PLL

32.768-kHz

OSCILLATOR

STATE

CONTROL

POWER

MANAGEMENT

INTERRUPT

CONTROLLER

RTC

GPIO

PWM

SSI1

DAI

SSI2

CODEC

INTERNAL DATA BUS

ARM720T

ARM7TDMI CPU CORE

8-KBYTE

CACHE

MMU

WRITE

BUFFER

TIMER

COUNTERS(2)

ON-CHIP

BOOT ROM

EPB BRIDGE

EPB BUS

Figure 1-1. EP73xx Block Diagram

MEMORY CONTROLLER

EXPANSION CNTRL

SDRAM CNTRL

INTERNAL ADDRESS BUS

LCD

MaverickKey™

LCD

CONTROLLER

ON-CHIP

SRAM

48 KBYTES

UART1

UART2

ICE-JTAG

IrDA

D[0-31]

EXPCLK, WORD, nCS[0-3], EXPRDY, WRITE

MOE, MWE, SDCLK, SDQM[0-3], SDRAS, SDCAS

A[0-27], DRA[0-14]

TEST AND DEVELOPMENT

LCD DRIVE

LED AND PHOTODIODE ASYNC INTERFACE 1

ASYNC INTERFACE 2

EP7309/11/12 User’s Manual - DS508UM4 1-11



Introduction

CRYSTAL

PC CARD

SOCKET

SDRAM

EXTERNAL MEMORY-

MAPPED EXPANSION

ADDITIONAL I/O

CONTROLLER

×16

SDRAM

×16

FLASH

×16

FLASH

PC CARD

×16

SDRAM

×16

SDRAM

×16

FLASH

×16

FLASH

BUFFERS

AND

LATCHES

MOSCIN

RTCIN

nCS[4] PB0 EXPCLK

D[0-31] A[0-27]

nMOE WRITE

SDRAS/ SDCAS

SDCS[0]

SDQM[0-3]

SDCS[1] SDQM[0-3]

nCS[0] nCS[1]

CS[n] WORD

nCS[2] nCS[3]

LEDFLSH

DD[0-3]

COL[0-7]

PA[0-7]

PB[0 -7]

PD[0-7]

PE[0-2]

nPOR

nPWRFL

BATOK

nEXTPWR

EP73XX

nBATCHG

WAKEUP

DRIVE [0-1]

FB[0-1]

SSICLK

SSITXFR

SSITXDA

SSIRXDA

SSIRXFR

LEDDRV

PHDIN

RXD1/2

TXD1/2

ADCCLK nADCCS ADCOUT

ADCIN

SMPCLK

CL1 CL2

FRM

RUN

DSR

CTS

DCD

LCD

KEYBOARD

POWER

SUPPLY UNIT

INPUT

AND

COMPARATORS

BATTERY

DC-TO-DC

CONVERTERS

CODEC/SSI2/

DAI

IR LED AND

PHOTODIODE

2× RS-232

TRANSCEIVERS

ADC

DIGITIZER

Figure 1-2. Typical EP73xx System Block Diagram

References

• ARM720T Technical Reference Manual, Revision 3 (ARM DDI 0192A)

• ARM System-on-Chip Architecture, 2nd Edition, b y Steve Furberu

Note: Click on the ARM Documentationsite to view more documents.

1-12 EP7309/11/12 User’s Manual - DS508UM4



Introduction

The 7312 processor u tilizes the ARM720T wh ich is based on the ARM7TDMI RISC (Reduced Instruction Set Computer) core running at a dynamically programmable speed from 18-90 MHz. This chapter discusses the key features of the ARM core.

Features

Key features include:

Chapter 2

2CPU Core

• ARM7TDMI CPU core (which supports the logic for the Th um b instruction set, core debug, enhanced multiplier, JTAG, and the Embedded ICE) running at a dynamically programmable clock speeds.

• Memory Management Unit (MMU) compatible with the ARM710 core (providing address translation and a 64-entry translation lookaside buffer) with added supp ort for Windows CE.

• 8 Kbytes of unified instruction an d data cache with a four-way set associative cache controller.

• Write Buffer

• TLB (Translation Look-Aside Buffer)

• System State Control: Operating, Idle, Standby

•CPUClockOptions

• System Reset Options

• CPU and Co-processor Registers

Programming Register List

Table 2-1: Programming Registers

Address Name Type Size Description Page

0x8000.0840 STDBY Write Write Enters Standby State page 2-13

0x8000.0800 HALT Write Write enters Idle State page 2-13

0x8000.2610 PLL Write 8 Write register for PLL Multiplier page 2-11

0x8000.A5A8 PLL Read 8 Read Register for PLL Multiplier page 2-11

EP7309/11/12 User’s Manual - DS508UM4 2-1



CPU Core

Block Diagram

Detailed block diagram of the core is shown below.

MMU 8KbyteCache

Virtual A ddress Bus

Inte rna l D a ta Bu s

Write Buffer

ARM7TDMI

CPU

System

Control

Coprocessor

JTA G Debug Inte rface

Co pro cesso r Inter face

AMBA

Inte rface

AMBA

address

AMBA

data

Figure 2-1. ARM720T Block Diagram

Programming Examples

;*****************************************************************************

; Set up the MMU. Start by flushing the cache and TLB.

;*****************************************************************************

;

ldr r0, =0x00000000

mcr p15, 0, r0, c5, c0 ; co-processor register c5

mcr p15, 0, r0, c7, c0 ; co-processor register c7

;

;*****************************************************************************

; Set user mode access for all 16 domains.

;*****************************************************************************

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CPU Core

;

ldr r0, =0x55555555

mcr p15, 0, r0, c3, c0 ; co-processor register c3

;

;*****************************************************************************

; Tell the MMU where to find the page table.

;*****************************************************************************

;

IMPORT PageTable

ldr r0, =PageTable

mcr p15, 0, r0, c2, c0 ; co-processor register c2

;

;*****************************************************************************

;EnabletheMMU.

;*****************************************************************************

;

ldr r0, =0x0000007d ; Cache and Write Buffer enabled in the command

mcr p15, 0, r0, c1, c0 ; co-processor register c1

;

;*****************************************************************************

; There should always be two NOP instructions following the enable or ; disable of the MMU.

;*****************************************************************************

;

mov r0, r0

;

;*****************************************************************************

; System state control registers. Standby and Idle states can b e entered by ; writes to these register locations.

;*****************************************************************************

;

ldr r0 , =0x80000000 ; base address for Standby and Idle(Halt) registers

mov r1, #0xAA ; value to be written to registers

str r1, [r0,#0x0840] ; write to Standby - system will now enter Standby

str r1, [r0,#0x0800] ; write to Idle(Halt) - system, will now enter Idle

;

state

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CPU Core

Operational Overview

Using the Von Neumann (load/store) architecture, the ARM720T core h as a three stage instruction pipeline to increase the speed of the instruction execution within the processor. The fetch-decode-execute of concurrent instructions are done in parallel requiring approximately 1.9 CPI (cycles per instruction).

The core provides a 8 Kbytes un ified cache and a memory managem ent unit (MMU). The MMU supports a two-level page table arrangement and controls the cache and write buffer for each page created.

ARM720T core has 37 32-bit registers: 1-program counter, 1-current program status register, 5-saved program status registers, 30-general purpose registers. The core also supports 16 co-processor registers for control of the on-chip cache, MMU, and buffers.

Thecoresupportstwoinstructionsets,ARMandThumbforfull32-bitor16-bit instruction decoding. State switching between ARM and Thumb, and register assignments for each, are detailed in the ARM720T document provided by ARM. The core supports both big as well as little-endian modes.

The core contains an embedded debug architecture. The 5-pin JTAG port will allow the host s ystem to convert debugger commands into JTAG commands for the purpose of hardware c ontrol to do th e following:

• Set breakpoints and watchpoints

•HalttheARMprocessor

• Access internal registers

• Access system memory

MMU

The MMU (Memory M anagement Unit) does the following

• Translates virtual addresses to physical addresses

• Controls memory access permissions, cache and write buffer accesses for each page.

The MMU consists of a TLB (translation look aside buffer) an d hardware for page table accesses as well as the access control logic.

Memory is divided by the MMU i n the following m anner:

• Sections: 1 Mbyte memory blocks

• Large Page: 64 Kbytes memory b locks which allows mapping of large region with only a single entry in the TLB.

• Small Page: 4 Kbytes memory blocks

Based on the entry for the section or page, the cache and write buffer wi ll be either enabled or disabled for that region of memory.

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TLB

CPU Core

The TLB (Translation look-aside Buffer) is a 64-entry associative cache of recent virtual address to physical address translations to eliminate a two- stage search for a higher proportion of internal register or external bus accesses.

Cache

• Provides the translation and access permission information for memory accesses

• For a TLB miss, the TLB walking hardware accesses the transition table from physical memory to update itself (two-stage).

• If the TLB is full, a stored value will be over-written.

Cacheis 4-wayset associativewith 8 Kbytes of mixedinstructionand data,organized as 512 lines of 4 words (16-byte). Connected directly to the core, cache only stores the virtual address. Cache can only be used once the MMU is enabled. Once en abled, the specific sections or pages of memory that are segmentedcan control whether cacheor write buffer is used for that region. Cache is disabled at power on reset. See Figure

2-2 on page 2-6 for cache organization.

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CPU Core

31 11 10 43210

virtual add ress

tag R A M

128 entry

=? =? =? =?

tag R A M

128 entry

encode

hit data

tag R A M

128 entry

Figure 2-2. ARM720T Cache Organization

tag R A M

128 en try

[10:0]

[10:9]

byte addresses

[1:0]

Data RAM

[8:2]

2048 x 32-bit

word

Write Buffer

Cache is direct-mapped. The copy of the address or data is stored along with an address tag that is compared with the location in system memory. Cache is also writethrough and uses a replacement al gorithm to select which of the four possible locations will be overwritten in the case of a cache miss.

The write buffer h olds four addresses and eight data words.The MMU defines which addresses are bufferable. Each address can be associated with any number of data words. Data words a re written to sequential memory s tarting at that address.

The write bufferbecomes full when all four addresses are used or all eight data words are used. The processor can write into the write buffer at fast cache speed and continue executing instructions stored in cache while the write buffer storesdata to external memory at the current memory bus speed. If there is a memory fault generated by a buffered write, the system will not be able to recover from it since the processor state is not recoverable.

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Debug Interface

JTAG (Joint Test Action Group) or IEEE 1149 provides a boundary scan test interface with 5 dedicated signals connected directory to the CPU core:

•TRST-TestReset(activelow)

•TCK-TestClock

• TMS - Test Mode Select

•TDI-TestDataIn

•TDO-TestDataOut

See Chapter 14 for more information on debugging the EP73xx via the JTAG interface.

CPU Register Definitions

ARM has 37 32-bit internal registers. If operating in Thumb mode, the processor must switch to ARM m ode before taking an exception. The return instruction will restore the processor to Th umb state. Most tasks are executed out of User mode.

CPU Core

User: Unprivileged normal operating mode. FIQ: Fast interrupt (high priority) mode when FIQ is asserted IRQ: Interrupt request (norm al) mode whe n IRQ i s asserted Supervisor: Software interrupt instruction (SWI) or reset will cause entry into

this mode

Abort: Memory access violation will cause entry into this mode Undef: Undefined instructions System: Privileged mode. Uses same registers as user mode

Figure 2-3 on page 2-8 illustrates the use of all registers for the following core

operating modes. Each will bank or store a specific number of registers. Banked register information is not shared between m odes. FIQs bank the fewest number of registers which increases performance.

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CPU Core

User FIQ IR Q SVC Undef Abort

r13 (sp)

r14 (lr)

r15 (pc )

r0 r1 r2 r3 r4 r5 r6 r7 r8

r9 r10 r11 r12

Banked

r9 r10 r11 r12

r13 (sp)

r14 (lr)

Banked

r13 (sp)

r14 (lr)

Banked

r13 (sp)

r14 (lr)

Banked

r13 (sp)

r14 (lr)

Thum b state

Low registers

Banked

Thum b state

High registers

r13 (sp)

r14 (lr)

cpsr

sps r

Figure 2-3. Register Organization Summary

spsr

User mode in Thumb state generally limits access to r0-r7. There are a f ew instructions that allow access to the high registers. For the 5 exceptions, the processor must revert to ARM state.

R0-R12: General pu rpose read/write 32-bit registers R13 (sp): Stack Pointer R14 (lr): Link Register R15 (pc): Program Counter CPSR: Current Program Status Register (contains condition codes and

operating modes)

SPSR: Saved Program Status Register (saves CPSR when exception oc curs)

ARM720T Core Coprocessor Registers

spsr

The ARM720T core has 16 coprocessor registers for control over the MMU. See Table

2-2 on page 2-9 Updates to the co- processor registers are written using the CP15

instruction.

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Table 2-2: ARM720T Core Coprocessor Registers

CPU Core

4Reserved

6 Fault Address (Read/Write) register contains address of the last data access abort

8 TLB Operation (Write) register can configure or clean (flush) when written to

9-12 Reserved

13 Used to support WinCE. Returns a logic “1” if WinCE enhancements are enabled.

14-15 Reserved

ID Register (Read/Write) register than may return an ID consisting of an architecture version and AR M trademark

Control (Read/Write) register to enable MMU, cache, write buffer, and other coprocessor operations

Translation Base Table (Read/Write) register contains the start address of the first level translation table

Domain Access Control (Read/Write) register specifies permissions for all 16 domains

Fault Status (Read/Write) register indicates type of fault and domain of last data abort. Write to this location flushes entire TLB.

Cache Operation (Write) register will configure or perform a clean (flush) of the cache and write buffer when written to

CPU Clocks

There are two clocks required to maintain any of the processor states that will be described in the following section.

•RealTimeClock(RTC)

• On-chip PLL (Phase Lock Loop) Clock

• External 13 MHz Clock (Optional)

Real Time Clock (RTC)

The RTC is generated from an external 32 kHz crystal oscillator created by the crystals fundamental tone. The RTC, from the crystal will be clocked at 1 Hz. Internally, it contains a match and data registers that are updated once per second. More information is contained in Chapter3 of the manual.

Real Time Clock Characteristics and Interface Requirements

• The external crystal conn ects directly to the RTCIN and RTCOUT pinson the processor.

• 32.768 kHz frequency should be created by the fundamental tone of the external crystal.

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CPU Core

• Start-up resistor is n ot necessary. One is provided internally.

• Start-up capacitors may be placed on each side of the external crystal and ground. Value for each should be around 10 pF but also should be selected based upon crystal specifications. Capacitance of the traces and crystal leads should be subtracted from the load capacitor value for precision.

• The crystal should have a maximum of 5 ppm frequency drift over the chips’s operating temperature range.

• Voltage for the crystal must be 2.5 V+

A digital clock source can be used to drive the the clock should match that of Vdd supply for the processor pads or the supply voltage used to drive the non-core Vdd pins on the EP73xx. In this configuration, the output clock pin should be left floating.

RTCIN ontheEP73xx.Voltagelevelsof

On-Chip PLL

The on-chip PLL is generated f rom an external 3.686 MHz crystal. The ARM720T CPU clock, from the PLL, can then be programmed to 18.432, 36.864, 49.152, 73.728, and 90.3168 MHz.

The external bus is controlled by the PLL and defaults to 18 MHz until the internal CPU clock reaches 36 MHz or above, at which point the external bus runs at 1/2 the CPU clock speed. Modifying the PLL speed in the SYSCON3 register will require a NOP at the next instruction for the system to stabilize. Internally, the state controller switches from the current clock to the new clock speed, by bringing both clocks low, then perform the switch to the new speed to insure a glitch-free transition.

PLL Clock Characteristics and Interface Requirements

0.2 V.

• The 3.6864 M Hz frequency should be c reated by the crystals fundamental tone.

• Start-up resistor is p rovided internally

• Value of loading capacitors should be in the range of 10 pF. However, the actual value will depend on the crystal’s specifications. The total sum of the capacitance on the pins and the leads should factor into the value of the loading capacitors.

• The crystal should have a maximum of 10 ppm frequency drift over the operating temperature of the chip.

A digital clock source can be used to drive the levels of the clock source should match the Vdd supply for the EP73xx non-core pins. The output clock pin (

MOSCOUT) should be left floating.

PLL Multiplier for 90 MHz Operation

There are two internal register that can be used to increase the PLL frequency beyond 74 MHz. The intention is to increase the speed to 90 MHz for use with the D AI and to increaseoverall performance. This can affectdevices and their times ru nning from the

MOSCIN pin of the EP73xx. Voltage

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internal PLL clock so adjustments and consideration will need to be tak en into account.

PLL Equation: (PLL Multiplier/2)* 3.686 MHz = PLL Frequency

ex. For 90 MHz operation, PLL M ultiplier = 49

CPU Core

It should be noted that using the PLL Multiplier to achieve 90 MHz operation will result in a shifting up of frequencies and rates derived from the PLL by 22. 5%. For example, the data bus will move from 36 MHz to 45 MHz. Take care wh en using a PLL-derived system bec ause such shifting may be in effect.

Programming Example

;********************************************************************************

; Sample code for entering the proper value into the PLL Multiplier Write Register to

; achieve 90 MHz operation. This is done after setting the PLL to 74 MHz in

; SYSCON3.

;********************************************************************************

;begin

PLL_Multiplier_Write_Register EQU 0x80002610; the location of the PLL multiplier

Value_For_90_MHz_Operation EQU 0x31000000 ; the value for 90Mhz operation

ldr r0= PLL_Multiplier_Write_Register

ldr r1= Value_For_90_MHz_Operation

str r1, [r0] ; store R1 at R0

;end

PLL Register Descriptions

;Write register

PLL Multiplier Write Register (PLLW)

Address: 0x8000.2610, Write Only Definition: PLL Multiplier is written to the upper 8 b its of this register only. Do

not read from this location

PLL Multiplier Read Register (PLLR)

Address: 0x8000.A5A8, Read Only Definition: PLL Multiplier value written to above register can be read at this

location in the upper 8 bit only. Do not write to this location.

Note: Increasing the PLL clock too high will cause the processor to abort any

operation.Decreasing the speed willnot clear the condition. A system reset and a lower setting will be required. PLL must be preset to 74MHz via SYSCON3 before PLL m ultiplier can be used properly.

External 13 MHz Clock

An external 13 MHz crystal oscillator can be used to drive the EP73xx. When selected, the CPU and external buses are both clocked at 13 MHz. In this c onfiguration, the

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CPU Core

internal PLL is n ot used. The default value “00” for the PLL setting in SYSCON3 must not change.

CPU State Control

There are three principal power management states on the EP73xx processor

• Operating State (highest power consumption)

• Idle State

• Standby State (lowest power consumption)

nPOR, power fail,

or user reset

Interrupt or rising wakeup

Standby Operating

Write to standby location,

power fail, or user reset

Standby State

Idle

Write to halt location

Figure 2-4. State Diagram

Each state leaves on or turns off a unique set of CPU peripherals which can serve to reduce or limit the power required for the system for blocks of time in which there is no external system activity. The processor can enter or exit any one of the three states.

Standby state is the lowest p ower state the processor can achieve and still be c apable of returning to operating state or equates to the system being switched off. The RTC clock remains on to insure that the processor can “wake up” from an external interrupt or the “wak e up” signal.

When the EP73xx is first powered on, the processor is in a “cold reset”. The same condition can be created by asserting

nPOR. Cold reset for the processor is the

standby state. In this instance, none of the peripherals have been initialized so the only method for entering th e operating state is by means of the

WAKEUP pin.

Clock Status

• If internal PLL is used, it will shut off

• If external 13 MHz clock is being used, CPU will ignore input. External

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CPU Core

logic (CLKEN) pin can be used to disable external oscillator if desired. In this configuration,

•RTCremainson.

Entering standby state can be accomplished in software by writing to the STDBY register, or in hardware with i npu t from the

Before entering th e stand by state, the software m us t properly disable the DAI. Failing to do so will result in higher than ex pec ted power consumption while in this state as well as unpredictable behavior of the DAI.

During standby state, all system memory and state are m aintained and the system time is kept up-to-date. The external address and data bus are forced low internally by the are powered down from draining current. Sincethe also be used to disable external devices to further reduce power drain while in this state. The internal peripherals external signals return to their reset state.

Exiting standby is accomplished with the following external stimulus of a keyboard interrupt (if enabled), power management inputs, external interrupts

WAKEUP.

RUN signal which is also driven low. This is done to prevent peripherals that

nURESET or by nPWRFL.

RUN signal is driven low, it can

EINT[3:1],or

The following register will allow the system software to put the processor into Standby state. Writing to this location will not clear the internal registers settings of the processor. The processor will s it until an ex tern al interrupt or the asserted and continue executing code from the poi nt of entry into Standby.

State Control Register Descriptions

Enter the Standby State Register (STDBY)

Address: 0x8000.0840, Write Only Definition: A write to this location will put the s ys tem into the Standby State by

halting the main oscillator. A write to this location while there is an active interrupt will have no effect.

Note: Before enteringthe Standby State, the LCD Controller should be disabled. The

LCD controller shouldbe enabled on exit from the StandbyState. If the EP73XX is attemptingto get into the Standby State when there is a pending interrupt request, it will not enter into the low power mode. The instructionwill get executed, but the processor will ignore the command.

Idle State

From operating state, th e processor can en ter Idle state by writing to the HALT register of the EP 73xx. When an interrupt occurs, the processor will return to the operating state and execute the next instruction.

WAKEUP pin is

WAKEUP cannot be used.

In the I dle state, the device will function as it would in operating s tate with the exception of the CPU clock which is halted. The PLL (if enabled) or the external 13 MHz clock source will remain active during this state.

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CPU Core

The following register will allow the system software to put the processor into Idle state.

Enter the Idle State Register (HALT)

Address: 0x8000.0800, Write Only

Definition: A write to this location will put the system into the Idle State by

halting the clock to the processor until an interrupt is generated. A write to this location while there is an active interrupt will have no effect

Below is a list of peripherals and clocks and their status during each of the three states:

Table 2-3: Status of Peripherals and Clocks by Operating State

Address (W/B) Operating Idle Standby

SDRAM Control On On SELFREF Off N/A

UARTs On On Off Reset Reset

LCD FIFO On On Reset Reset Reset

LCD On On Off Reset Reset

ADC Interface On On Off Reset Reset

SSI2 Interface On On Off Reset Reset

DAI Interface On On Off Reset Reset

CODEC On On Off Reset Reset

Timers On On Off Reset Reset

nPOR

RESET

nURESET

RESET

RTC On On On On On

LED Flasher On On On Reset Reset

DC-to-DC On On Off Reset Reset

CPU On Off Off Reset Reset

Interrupt Control On On On Reset Reset

PLL/CLKEN Signal On On Off Off Off

Power Up Sequence

The EP73xx has a power-up sequence that mu st be followed for a proper start. If any of the recommended timing sequences below are viol ated, the part may not s tart properly and may not recover without a hard reset.

1. Upon power-up, Vdd has settled

Note: nURESET must be stable before nPOR rising.

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nPOR must be held low for a minimum of 100 µsafter

CPU Core

2. Once nPOR goes high, the EP73xx will enter Standby State. In this state, the PLL is not enabledand thus the CPU is not turned on. The must be asserted

WAKEUP signal

RESET

3. After

4. Once the WAKEUP signal is detected internally, it first enters a deglitching

5. Once the

There are three asynchronous resets to the EP73xx: nPOR, nPWRFL,andnURESET.If any of these are active, a system reset is generated internally. This will reset all internal registers in the EP73xx except the RTC data and match registers. These registers are only cleared by

nPOR goes high, the WAKEUP signal will be detected by the processor

after one to two seconds. After such time, the can be detected but must be asserted high for a minimum of 125 µs

Note: IMPORTANT. nURESET must not be asserted during the period between

WAKEUP assertion and transition from Standbyto Operating s tate. This will cause t he processor to enter an unknown s tate and require a system r eset to clear this condition.

circuit which is the reason for the 125 µs duration. The PLL is then enabled and the CPU turns on. read ag ain after a time the EP73xx will return to Standby. Idle state.

WAKEUP signal has been detected, a maximum of 250 ms will

elapse before the CPU is turned on and begins fetching the first instruction.

WAKEUP signal is then ignored and will only be

nPOR assertion or power is cycled on the device at which

nPOR.

WAKEUP (active high) signal

WAKEUP is also ignored during

Any reset will also reset the CPU and cause it to start execution at the reset vector (address 0x0) when the EP73xx returns to the operating state.

Internal to the EP73xx, three different s ignals are used to reset the storag e elements. These are

nPOR (active low) is the highest priority reset signal and is also the external signal

that forces the internal signals signal) active. nPOR will only be active after the EP73xx has first powered up and not during any other resets. the cold reset flag (CLDFLG) which is bit 15 of the SYSFLG register.

nSYSRES (System R eset, active low) is generated internally to the EP73xx if nPOR, nPWRFL,or nURESET are active. It is the second highest priority reset signal, used to

asynchronouslyresetmostinternalregistersintheEP73xx. forces going into Standby.This can be done without co-operation from the system software.

nSTDBY and RUN signals are high when the EP73xx is in Operating or Idle state.

The The except the RTC.

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nPOR, nSYSRES,andnSTDBY.

nSYSRESandnSTDBY (equivalent to the external RUN

nPOR active will clear all flags in the status register ex cept for

nSYSRES (when active)

nSTDBY and RUN low which is the result of the CPU resetting and the EP73xx

nSTDBY will disable any peripheral block that is clocked from the CPU clock



CPU Core

This page intentionally blank.

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Introduction

EP73xx has three g eneral purpose timers that can serve as watchdogs for system resources or and events. Two timers are based on the internal P LL or 13 MHz clock and the third is fed by the RTC. Routines requiring periodic service to check status and new values can make use of these timers.

Features

All timers have the following characteristics

Chapter 3

3Timers

• Programmable for two modes: free running and pre-scale

• Interrupt flags and corresponding mask for control and status

• Timer 16-bit read/write data register to set and read values. Can be accessed at any time.

Timer Register List

Address Name Type Size Description Page

0x8000.0300 TC1D R/W 16 TC1 Data Register page 3-3

0x8000.0340 TC2D R/W 16 TC2 Data Register page 3-3

0x8000.0380 RTCDR R/W 32 RTC Data Register page 3-3

0x8000.03C0 RTCMR R/W 32 RTC Match Register page 3-4

Programming Example

;*****************************************************************************

; Enable TC1 Timer prescale = 2 kHz Program a 2 ms interrupt rate

;*****************************************************************************

;

TC1Prescale EQU 0x10 ; Set prescale in SYSCON1

TC1Timer EQU 0x14 ; Set 10 ms timer in TC1 timer

TC1Mask EQU 0x100 ; UnMask TC1 interrupt

ldr r12, =0x80000000 ; base address for Timers

ldr r1, =TC1Prescale

Table 3-1: Timer Registers

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Timers

str r1, [r12, #0x0100] ; Prescale - 2 kHz clock

ldr r1, =TC1Timer

str r1, [r12, #0x300] ; 10 ms timer rate

ldr r0, =TC1Mask

str r0, [r12,#0x0280] ; Interrupt enabled

;

Operational Overview

These identical count-down timers derive their clock from the internal PLL or external 13 MHz clock. Values for these timers are programmed into the read/write registers as seen below and are decremented on the s econd active edge of the clock once the write to th e register is com plete (i.e., after the first complete period of the clock). When the timer reaches 0, the corresponding interrupt is asserted (if enabled). Values can be written to the data registers at any time.

When running from the PLL clock, 512 kHz and 2 kHz rates are possible for each timer. When using the external 13 M H z crystal, the default frequencies for the timers will be 541 and 2.115 k Hz. Optionally, in 13 MHz mode, a divider of 26 can be used to generate a frequency of 500 kHz. This is set automatically in 13 MHz mode by setting the OSTB bit in SYSCON2 register thus routing a 500 kHz clock to the timer. This however, does not affect the frequencies derived for any of the other internal peripherals.

Settingthe clock source frequencyfor TC1 and TC2 involves writesto SYSCON1 bit 5 and 7. C learing each b it sets the clock to 2 kHz. Setting this bit sets the clock at 512 kHz.

Interrupts masks f or these registers are s et in the INTMR1 register and status seen in the INTSR1 register. To clear the interrupt for TC1 and TC2, a write to the TE2EOITC1 and TE2EOI-TC2 registers respectively will clear the underflow interrupt.

When operating at 90 Mhz, the two timers deriving their clocks from the PLL will be shifted upwards by 22.5%. Therefore the 512 kHz clock will become 627.2 kHz and the 2 kHz clock will become 2.45 kHz. The timer deriving its clock from the RTC is not affected.

Free Running Mode

In free running mode, the counter will wrap around to 0xFFFF when it underflows and will c ontinue to count down. Any value written will be decremented on the second edge of the selected clock rate. A value of 0 in bit 4 or 6 of SYSCON1 will set free running mode for TC1 and TC2 respectively.

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Prescale Mode

Any value wri tten to TC1 or TC2 is automatically re-loaded when the counter underflows. Any value written to TC1 or TC2 will be decremented on the second edge of the selected clock. Setting bit 4 or 6 in SYSCON1 for TC1 and TC2 respectively, will initiate prescale mode.

RTC Timer

The RTC timer is derived from the RTC clock. The timer interface creates a 1 Hz tick that can be controlled by the RTCDR (RTC data register). This 32-bit read/write register value corresponds to the number of 1 Hz ticks and will be incremented on the next rising edge of the 1 Hz clock. Any value may be written to this register.

The interrupt driven from this c lock comes from th e RTCMR (RTC Match R egister). Once the value in th e match register actually “matches” the value in the data register, the interrupt will assert.

Timers

Timer Register Descriptions

Timer Counter 1 Data Register (TC1D)

Address: 0x8000.0300, Read/Write Definition: The timer counter 1 data register is a 16-bit read/write register

which sets and reads data to TC1. Any value written will be decremented on the next rising edge of the clock.

Timer Counter 2 Data Register(TC2D)

Address: 0x8000.0340, Read/Write Definition: The timer counter 2 data register is a 16-bit read/write register

which sets and reads data to TC2. Any value written will be decremented on the next rising edge of the clock

Real Time Clock Data Register (RTCDR)

Address: 0x8000.0380, Read/Write Definition: The Real Time Clock data register is a 32-bit read/write register,

which sets and reads th e binary time in the RTC. Any v alu e written will be incremented on the next rising edge of the 1 Hz clock. This register is reset only by

nPOR.

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Timers

Real Time Clock Match Register (RTCMR)

Address: 0x8000.03C0, Read/Write Definition: The Real Time Clock match register is a 32-bit read/write register,

which sets and reads the binary match time to RTC. Any value written will be compared to the current binary time in the RTC, if they match it will assert the RTCMI interrupt source. This register is reset only by

nPOR.

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Introduction

Like most modern microprocessors, the EP73xx contains an interrupt controller to manage both external and internal exceptions. When an expected or unexpected event arises du ring the execution of a p rogram (i.e. interrupt or memory fault) an exception is generated. If more than one exception occurs at the same time, a fixed priority system determines the order in which they are handled.

Features

Chapter 4

4Interrupt Controller

• Interrupt requests received from 22 different sources

• Standard (IRQ) and Fast (FIQ) interrupt types

• Interrupts can be used to wake th e CPU from IDLE or STANDBY

Interrupt Register List

Address Name Type Size Description Page

0x8000.0240 INTSR1 RO 32 Interrupt Status page 4-8

0x8000.1240 INTSR2 R/W 32 Interrupt Status page 4-11

0x8000.2240 INTSR3 R/W 32 Interrupt Status page 4-12

0x8000.0280 INTMR1 R/W 32 Interrupt Mask page 4-10

0x8000.1280 INTMR2 R/W 32 Interrupt Mask page 4-12

0x8000.2280 INTMR3 R/W 32 Interrupt Mask page 4-13

0x8000.0600 BLEOI R/W --- Battery Low EOI page 4-13

0x8000.0640 MCEOI R/W --- Media Change EOI page 4-13

0x8000.0680 TEOI R/W --- Tick Watchdog EOI page 4-13

0x8000.06C0 TC1EOI R/W --- TC1 EOI page 4-13

Table 4-1: Interrupt Registers

0x8000.0700 TC2EOI R/W --- TC2 EOI page 4-14

0x8000.0740 RTCEOI R/W --- RTC Match EOI page 4-14

0x8000.0780 UMSEOI R/W --- UART1 Modem EOI page 4-14

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Interrupt Controller

Address Name Type Size Description Page

0x8000.07C0 COEOI R/W --- CODEC EOI page 4-14

0x8000.1700 KBDEOI R/W --- Keyboard EOI page 4-14

Table 4-1: Interrupt Registers (Continued)

0x8000.1600 SRXEOF R/W --- SSI2 FIFO EOI page 4-14

Programming Examples

ENTRY

;

ldr r15, ResetV

ldr r15, UndefV

ldr r15, SWIV

ldr r15, PAbortV

ldr r15, DAbortV

ldr r15, UnusedV

ldr r15, IRQV

ldr r15, FIQV

;

;*****************************************************************************

; The following is the actual vector table. It contains the addresses of the routines ; which handle each exception type.

;*****************************************************************************

ResetV

DCD ResetHandler ; (0x0)

UndefV

DCD UndefHandler ; (0x4)

SWIV

DCD SWIHandler ; (0x8)

PAbortV

DCD PAbortHandler ; (0xc)

DAbortV

DCD DAbortHandler ; (0x10)

UnusedV

DCD UnusedHandler ; (0x14)

IRQV

DCD IRQHandler ; (0x18)

FIQV

DCD FIQHandler ; (0x1C)

;*****************************************************************************

; IRQHandler routine checks for Timer1 ex pire interrupt. Sets GPIO PA0-8 low ; Interrupt cleared before return to p rogram.

;*****************************************************************************

IRQHandler

TIMERCHECK EQU 0x00000100

ldr r0, =0x80000000 ; base address for interrupt status register

ldr r1, [r0,#0x240] ; r1 contains timer status from INTSR1

cmp r1, #TIMERCHECK

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Interrupt Controller

bne nextstatuscheck ; not the timer - moving down the IRQ routine

mov r2, #0x0

strb r2, [r0,#0x0] ; setting PA0-8 low

mov r2, #0xFFFFFFFF

str r2, [r0,0x06C0] ; Write to TC1EOI register - clear interrupt

; ........ code...........

subs pc, lr, #4 ; Return from interrupt to pending instruction

;

Operational Overview

Once an exception occurs, the ARM720T will attempt to complete the current instruction (except for a system reset) and will then identify the interrupt type. The interrupt vector table, already loaded by the system software contains a reference or address of the specific interrupt routine for each type of exception identified by the processor. The CPU will jump to the appropriate routine for servicing of the interrupt. The vector table for all interrupt types is as follows:

Table 4-2: Vector Addresses by Interrupt Type

Interrupt Vector Address

Reset 0x0

Undefined Instruction 0x4

Software Interrupt (SWI) 0x8

Prefetch Abort (Instruction fetch) 0xC

Data abort (Data access) 0x10

IRQ (normal interrupt) 0x18

FIQ (fast interrupt) 0x1C

Within each routine for eac h interrupt type created by the system software, the specific interrupt can be determined by examining any one of the three status registers. After an action is taken, a write to the appropriate “End of I nterrupt” register must be issued to clear the interrupt status register to prevent re-entry an d an endless loop.

For severalinterrupts occurring simultaneously, the pre-determined priority based on type of interrupt will cause the highest interrupt priority to execute first and queue any remaining interrupts. I nterrupts of the same type that occur simultaneously simplyrequiresystemsoftwaretocheckallpossibleinterruptsforthespecifictype.

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Interrupt Controller

Interrupt Types and Priorities

The EP73xx interrupt controller can generate two types of interrupts: Standard (IRQ) or Fast (FIQ).Seventeenof thetwenty-twointerrupt sources areIRQ interrupts,while the remaining five are F IQ. FIQs have a higher priority than IRQs. If two interrupts are received from within the same group (IRQ or FIQ), the order in whichthey are serviced must be resolved in software. The priorities are listed in Table 4-3.

Table 4-3: Exception Priority Handling

Priority Exception

Highest Reset

. Data Abort

.FIQ

.IRQ

.Prefetch Abort

Lowest Undefined Instruction, Software Interrupt

Interrupt Operation

All i nterrupts are level sensitive; that is, they must conform to the following sequence:

1. The interrupting dev ic e (either external or internal) asserts the ap propriate

2. If the appropriatebit is setin the interruptmask register, then eitheran FIQ

3. If interrupts are enabled, the processor jumps to the appropriate address.

4. Within the interrupt h an d ler routine, the status register is read to

5. Software in the interrupt service routine will clear the interrupt source by

The interrupt service routine may then re-enable interrupts; other pending interrupts are serviced in a similar way. Alternately, the service routine may return to the interrupt dispatch code, which can check for pending interrupts and dispatch them accordingly. The “ End of I nterru pt” type interrupts are latched . All other interrupt sources (i.e., external i nterrupt source) must b e held active until its respective service routine starts executing. See “End-Of-Interrupt Locations” on page 4-13 for more details.

interrupt.

or an IRQ will be asserted by the interrupt controller. (Descriptions of each bit in this register can be found in “Interrupt Status Register 1 (INTSR1)”

on page 4-8.)

determine if the source of the interrupt(s). This will determine which subroutine(s) to call to service said interrupt(s).

an action specific to the devi ce requesting the interrupt (i.e., reading the UART RX register).

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Interrupt Listing

Table 4-4, Table 4-5,andTable 4-6 show the names and allocation of interrupts in the

EP73xx.

Interrupt Controller

Table 4-4: Interrupt Allocation in the First Interrupt Register

Interrupt

FIQ 0 EXTFIQ External fast interrupt input (nEXTFIQ pin)

FIQ 1 BLINT Battery low interrupt

FIQ 2 WEINT Tick Watchdog expired interrupt

FIQ 3 MCINT Media changed interrupt

IRQ 4 CSINT CODEC sound interrupt

IRQ 5 EINT1 External interrupt input 1 (nEINT[1] pin)

IRQ 6 EINT2 External interrupt input 2 (nEINT[2] pin)

IRQ 7 EINT3 External interrupt input 3 (EINT[3] pin)

IRQ 8 TC1OI TC1 underflow interrupt

IRQ 9 TC2OI TC2 underflow interrupt

IRQ 10 RTCMI RTC compare match interrupt

IRQ 11 TINT 64 Hz tick interrupt

IRQ 12 UTXINT1 Internal UART1 transmit FIFO empty interrupt

IRQ 13 URXINT1 Internal UART1 receive FIFO full interrupt

IRQ 14 UMSINT Internal UART1 modem status changed interrupt

IRQ 15 SSEOTI Synchronous serial interface 1 end of transfer interrupt

Bit in INTMR1

and INTSR1

Name Comment

Table 4-5: Interrupt Allocation in the Second Interrupt Register

Interrupt

IRQ 0 KBDINT Key press interrupt

IRQ 1 SS2RX Master / slave SSI 16 bytes received

IRQ 2 SS2TX Master / slave SSI 16 bytes transmitted

IRQ 12 UTXINT2 UART2 transmit FIFO empty interrupt

IRQ 13 URXINT2 UART2 receive FIFO full interrupt

Interrupt

FIQ 0 DAIINT DAI interface interrupt

EP7309/11/12 User’s Manual - DS508UM4 4-5

Bit in INTMR2 and

INTSR2

Table 4-6: Interrupt Allocation in the Third Interrupt Register

Bit in INTMR3 and

INTSR3



Name Comment

Interrupt Controller

Interrupt Latencies in Different States

Operating State

The ARM720T processor checks for a low level on its FIQ and IRQ inputs at th e end of each instruction. The interrupt latency is therefore directly related to the amount of time it takes to complete execution of the current instruction when the interrupt condition is detected. There is a one to two clock cycle synchronization penalty following the assertion of the interrupt. For example, if the EP73xx is operating at 13 MHz with a 16-bit external memory system, and instruction sequence stored in one wait state FLASH memory, the worst-case interrupt latency is 251 clock cy cles. This delay will include:

• Instruction fetch to complete LDM r0!, (r0-r15) worst case. This is a quad word quad instruction burst on the memory bus.

• Time for interrupt signal(data abort)

• Write Buffer flush (result of LDM instruct ion)

•3TLBmisses(worstcase)

Idle State

•6cachemisses(worstcase)

• 1 additional cache and MMU miss due to fetch from vector space

The ARM720T processor, operating at 13 MHz, has a worst-case interrupt latency of about 19.3 ms in the example system. For those interrupt inputs which have de-

glitching, the interrupt latency is increased by the maximum time required to p a ss

through the deglitcher, which is approximately 125 µs (2 cycles of the 16.384 kHz clock derived from the RTC oscillator). Adding the deglitcher creates an absolute worst-case latency of approximately 141 ms. If the ARM720T is run at 36 MHz or greater, the 19.3 ms value will be reduced.

All serial data transfer peripherals included in the EP73xx (except the master-only SSI1) have local buffering to ensure a reasonable interrupt latency response requirement for the OS of 1 ms or less. This assumes that the design data rates do not exceed the d ata rates described in this specification. If the OS cann ot meet this requirement, there will be a risk of data over/underflow occurring.

When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after approximately two clock cycles. However, there is potentially up to 20 ms latency as described above, unless the code is written to include at least two single cycle instructions immediately after the write to the I DLE register (in whic h case the latency drops to a few microseconds).

This is im portant, as the Idle State can only be left because of a pending interrupt, which has to be synchronized by the processor before it can be serviced.

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Standby State

Interrupt Controller

The Standby State equates to the system b eing switched “off” (i.e., no display, and the main oscillator is shut down). If the 18.432–73.72 MHz mode is selected, th e PLL will be shut dow n. In the 13 MHz mode, if the CLKENSL bit is set low, the

CLKEN signal

will be forced low and can, if required, be used to disable an external oscillator.

In Standby State, all system memory an d state is maintained and s ys tem time is kept current. The PLL/on-chip oscillator or external osc illator is disabled and the system i s static, except for the low-power watch crystal (32 kH z) os ci llator and divider chain to the RTC and LED flasher. The the system to power down other system modules.

When the EP73xx i s in Standby State, external address and data buses are driven low.

RUN signal is used internally to force these buses to be driven low. This is done to

The prevent peripherals that are power-down from draining current.

In Standby State, internal peripherals’ signals are set to their Reset States.

Table 4-7 summarizes the five external interrupt sources and the effect they have on

the processor interrupts.

Interrupt

nEXTFIQ

nEINT1–2 Not deglitched

EINT3 Not deglitched

nMEDCHG

Input State

Not deglitched; must be active for 20 µs to be detected

Deglitched by

16.384 kHz clock; must be active for at least 122 µs to be detected

RUN signal is driven low, and can be used externally in

Table 4-7: External Interrupt Sources

Operating

State Latency

Worst-case latency of 20 µs

Worst-case latency of 19.3 µs

Worst-case latency of 141 µs

Idle State Latency Standby State Latency

Worst-case 20 µs: if only single cycle instructions, less than 1 µs

Worst-case latency 141 µs; if any single cycle instructions = 125 µs

Including PLL / osc. settling time, approx. 0.25 sec, or approx. 500 µs when in Idle State if in 13 MHz mode with CLKENSL set

Including PLL / osc. settling time, approx. 0.25 sec, or approx. 500 µs when in Idle State if in 13 MHz mode with CLKENSL set.

As above (note difference if in 13 MHz mode with CLKENSL set)

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Interrupt Controller

Interrupt Register Descriptions

Interrupt Status Register 1 (INTSR1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SSEOTI UMSINT URXINT1 UT XINT1 TINT RTCMI TC2OI TC1OI EINT3 EINT2 EINT1 CS INT MCINT WEINT BLINT EXTFIQ

Address: 0x8000.0240, Read Only Definition: The interrupt status register is a 32-bit read only register. The

interrupt status register reflects the current state of the first 16 interrupt s ources within the EP73xx. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given below.

Bit Descriptions:

RSVD: Unknown during Read. EXTFIQ: External fast interrupt. This interrupt will be active if the

nEXTFIQ

input pin is forced low and is mapped to the FIQ input on the ARM720T processor.

BLINT: Battery low interrupt. This interrupt will be active if no external

supply is present (

BATOK is forced low. This interrupt is de-glitched with a 16 kHz

nEXTPWR is high) and the battery OK input pin

clock, so it will only generate an interrupt if it is active for longer than 125 µs. It is mapped to the FIQ i nput on the ARM720T processor and is c leared by writing to th e BLEOI location. BLINT is disabled during The Standby State.

WEINT: Tick Watch dog exp ired interrupt. This interrupt wi ll become

active on a rising edge of the periodic 64 Hz tick interrupt clock if the tick interrupt is still active (i.e., if a tick interrupthas not been serviced for a complete tick p eriod). It is mapped to the FIQ input on the ARM720T processor and the TEOI location.

Note: WEINT and watchdog timer are disabledduring the StandbyState. The watch

dog timer tick rate is 64 Hz (in 13 MHz and 73.728–18.432MHz modes).

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Interrupt Controller

MCINT: Media changed interrupt. This interrupt will be active after a

rising edge on the input is de-glitched with a 16 kHz clock so it will only generate an interrupt if it is active for longer than 125 µs. It is mapped to the FIQ input on the ARM7TDMI processor and is cleared by writing to the MCEOI location. On power-up, the Media change pin (

nMEDCHG) is used as an input to force the processor to either

boot from the internal Boot ROM, or from external memory. After power-up, the pin can be used as a general purpose FIQ interrupt pin.

CSINT: CODEC sound interrupt, generated when the data FIFO has

reached half full or empty (depending on the interface direction). It is cleared by writing to the COEOI location.

EINT1: External interrupt input 1. This interrupt will be active if the

nEINT1 input is active (low). It is clearedby returning nEINT1 to

the passive (high) s tate.

EINT2: External interrupt input 2. This interrupt will be active if the

nEINT2 input is active (low). It is clearedby returning nEINT2 to

the passive (high) s tate.

nMEDCHG input pin has been detected, This

EINT3: External interrupt input 3. This interrupt will be active if the

input is active (high). It is cleared by returning EINT3 to the passive (low) state.

TC1OI: TC1 under flow interrupt. This interrupt becomes active on the

next falling edge of the timer c ounter 1 clock after the timer counter has under flowed (reached zero). It is cleared by writing to the TC1EOI location.

TC2OI: TC2 under flow interrupt. This interrupt becomes active on the

next falling edge of the timer c ounter 2 clock after the timer counter has under flowed (reached zero). It is cleared by writing to the TC2EOI location.

RTCMI: RTC compare match interrupt. This interrupt becomes active on

the next rising edge of the 1 Hz Real Time Clock (one second later) after the 32-bit ti me written to the Real Time Clock match register exactly matches the current time in the RTC. It is cleared by writing to the RTCEOI location.

TINT: 64 Hz tick interrupt.This interrupt becomes active on every rising

edgeof the internal64 Hz clock signal.This 64 Hz clock is derived from the 15-stage ripple counter that divides the 32.768 kHz oscillator input down to 1 Hz for the Real Time Clock. This interrupt is cleared by writing to the TEOI location. TINT is disabled/turned off during the Standby State.

EINT3

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Interrupt Controller

UTXINT1: Internal UART1 transmit FIFO half-empty interrupt. The function

of this i nterrupt source depends on whether the UART1 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART1 bitrate and line controlregister), this interruptwillbe activewhen thereisnodataintheUART1TXdataholdingregisterandbe cleared by writing to the UART1 data register. I f the FIFO is enabled this interrupt will be active when the UART1 TX FIFO is half or more empty, and is cleared by filling the FIFO to at least half full. The FIFO is 16 bytes deep.

URXINT1: Internal UART1 receive FIFO half full interrupt. The function of

this interrupt source depends on whether the UART1 FIFO i s enabled. If the FIFO is disabled this interrupt will be active when there is valid RX data in the UART1 RX data holding register and be cleared by reading this data. If the FIFO is enabled this interrupt will be active when the UART1 RX FIFO is half or more full or if th e FIFO is non empty and no more characters have been received for a three character time out period. I t is cleared by reading all the data from the RX FIFO. The FIFO is 16 bytes deep.

UMSINT: Internal UART1 modem status changed interrupt. This interrupt

will be active if either of the two modem status lines (CTS or DSR) change state. It is cleared by writing to the UMSEOI location.

SSEOTI: Synchronous serial interfaceend of transfer interrupt. This

interrupt will be active after a complete data transfer to and from the external ADC has been completed. It is cleared by reading the ADC data from the SYNCIO register.

Interrupt Mask Register 1 (INTMR1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SSEOTI UMSINT URXINT1 UTXINT1 TINT RTCMI TC2OI TC1OI EINT3 EINT2 EINT1 CSINT MCINT WEINT BLINT EXTFIQ

Address: 0x8000.0280, Read / Write Definition: This interrupt mask register is a 32-bit read/write register, used to

selectively enable any of the first 16 interrupt sources within the EP73xx. Interrupts associated with bits 0 through 3 generate a fast interrupt request to the ARM720T processor (FIQ), causing a jump to processor vi rtual address 0000.001C. All other interrupts generate a standard interrupt request (IRQ), causing a jump to processor virtual address 0000.0018. Set the appropriate bit in this register to enable the c orresponding interrupt. All bits are cleared by a system reset. Consult the bit definitions for INTSR1 for information about interrupts associated with each mask bit.

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Interrupt Controller

Interrupt Status Register 2 (INTSR2)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD URXINT 2 UTXINT2 RS VD SS2TX SS2RX KB DINT

Address: 0x8000.1240, Read / Write Definition: This register is an extension of INTSR1. This interrupt status register

also reflects the currentstate of the new interruptsources within the EP73xx. Each bit is set if the ap propriate interrupt is active. The interrupt assignment is given below .

Bit Descriptions:

RSVD: Unknown during Read. KBDINT: Keyboard interrupt. This interrupt is generated whenever a key is

pressed, from the logical OR of th e first 6 or all 8 of the P ort A inputs (depending on the state of the KBD6 bit in the SY SCON2 register.The interrupt request is latched and can be de-asserted by writing to the KBDEOI location. KBDINT is not deglitched.

SS2RX: Synchronous serial interface 2 receives FIFO half or greater full

interrupt. This is generated when RX FIFO contains 8 or more half-words. This interrupt is cleared only when the RX FIFO is emptied or one SSI2 clock after RX is disabled.

SS2TX: Synchronous serial interface 2 transmit FIFO less than half empty

interrupt. This is generated when TX FIFO contains fewer than 8 byte pairs. This interrupt gets cleared by loading the FIFO w ith more data or disabling the TX. One synchronization clock is required when disabling the TX side before it takes effect.

UTXINT2: UART2 transmit FIFO half empty interrupt. The function of this

interrupt source depends on whether the UART2 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART2 bit rate and line control register), this interrupt will be active when there is no data in the UART2 TX data holding register and be cleared bywritingtotheUART2dataregister.IftheFIFOisenabled,this interrupt will be active when the UART2 TX FIFO is half or more empty and is cleared by filling the FIFO to at least half full. The FIFO is 16 bytes deep.

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Interrupt Controller

URXINT2: UART2 receiveFIFO half full interrupt. The function of this

interrupt source depends on whether the UART2 FIFO is enabled. If the FIFO is disabled, this interrupt will be active when there is valid RX data in the UART2 RX data holding register and be cleared by reading this data. If the FIFO is enabled, this interrupt will be active when the UART2 RX FIFO is half or more full or if the FIFO i s non-empty, and no more ch aracters have been received for a three-character time-out period, it is cleared by reading all the data from the RX FIFO. The FIFO is 16 bytes deep.

Interrupt Mask Register 2 (INTMR2)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD URXINT2 UTXINT2 RSVD SS2TX SS2RX KBDINT

Address: 0x8000.1280, Read / Write Definition: This register is an extension of INTMR1, containing the interrupt

mask bits. All of the interrupts represented in INTMR2 trigg er the standard interrupt (IRQ) signal of the ARM720T core. Please refer to INTSR2 for individual bit details.

Descriptions:

(See “Interrupt Status Register 2 (INTSR2)” for details)

Interrupt Status Register 3 (INTSR3)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD DAIINT

Address: 0x8000.2240, Read / Write Definition: This register is an extension of INTSR1 and INTSR2 containing only

the status bit for the DAI interface of the EP73xx. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given below.

Bit Descriptions:

RSVD: Unknown during Read. DAIINT: DAI interface interrupt. The cause must be determined by reading

the DAI status register. It is mapped to the FIQ interrupt on the ARM720T processor

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Interrupt Controller

Interrupt Mask Register 3 (INTMR3)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD DAIINT

Address: 0x8000.2280, Read / Write Definition: This register contains the interrupt mask for the DAI interface. This

interrupt triggers the fast interrupt (FIQ) signal of the ARM720T core.

Bit Descriptions:

DAIINT: DAI interface interrupt. The cause must be determined by reading

the DAI status register. It is mapped to the FIQ interrupt on the ARM720T processor.

End-Of-Interrupt Locations

The “End of Interrupt” locations that follow are written to after the app ropriate interrupt has been serviced. The write is performed to clear the interrupt status bit, so other interrupts can be serviced. Any value may be written to these locations.

Battery Low End of Interrupt (BLEOI)

Address: 0x8000.0600 Definition: A write to this location will clear the interrupt generated by a low

battery (falling edge of

Media Change End of Interrupt (MCEOI)

Address: 0x8000.0640 Definition: A write to this location will clear the interrupt generated by a falling

edge of th e

Tick End of Interrupt (TEOI)

Address: 0x8000.0680 Definition: A write to this location will clear the current pending tick interrupt

and tick watch dog interrupt.

TC1 End of Interrupt (TC1EOI)

Address: 0x8000.06C0 Definition: A write to this location will clear the under flow interrupt generated

by TC1.

nMEDCHG input pin.

BATOK with nEXTPWR high).

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

Interrupt Controller

TC1 End of Interrupt (TC2EOI)

Address: 0x8000.0700 Definition: A write to this location will clear the under flow interrupt generated

by TC2.

RTC Match End of Interrupt (RTCEOI)

Address: 0x8000.0740 Definition: A write to this location will clear the RTC match interrupt.

UART1 Modem Status Changed End of Interrupt (UMSEOI)

Address: 0x8000.0780 Definition: A write to this location will clear the modem s tatus changed

interrupt.

CODEC End of Interrupt (COEOI)

Address: 0x8000.07C0 Definition: A write to this location clears the sound interrupt (CSINT).

Keyboard End of Interrupt (KBDEOI)

Address: 0x8000.1700 Definition: A write to this location clears the KBDINT keyboard interrupt.

SSI2 FIFO Overflow End of Interrupt (SRXEOF)

Address: 0x8000.1600 Definition: A write to this location clears the SSI2 RX FIFO ov e rflo w status bit.

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Introduction

The SYSCON and SYSFLG registers control and report the status of the various components of the EP73xx sy stem-on-chip device. There are three read/write SYSCON system configuration registers, and two SYSFLG read on ly system flag registers.

Features

The system registers affect aspects of the following features and peripherals:

Chapter 5

5System Registers

• Keyboard scanner

•Timers

• UART/SIR control

• Buzzer output control

•Debugmodeselect

• SSI/CODEC/DAI/ADC

•LCD

• Expansion clock

•Wakeupcontrol

•SDRAM

•OStimercontrol

•

RUN/CLKEN select

• Clock speed/wait state select

•Version

• Media change detect

•Powerstatus

• RTC subdivide

• Boot mode status

•PartID

•VersionID

• MaverickKey Unique-ID

EP7309/11/12 User’s Manual - DS508UM4 5-1



System Registers

System Register List

Table 5-1: System Registers

Address Name Type Size Description Page

0x8000.0100 SYSCON1 R/W 32 System Control Register 1 page 5-4

0x8000.1100 SYSCON2 R/W 16 System Control Register 2 page 5-7

0x8000.2200 SYSCON3 R/W 16 System Control Register 3 page 5-8

0x8000.0140 SYSFLG1 Read 32 System Status Flag Register page 5-9

0x8000.1140 SYSFLG2 Read 32 System Status Flag Register page 5-12

0x8000.05C0 STFCLR R/W - Clear all Star t-up Reasons Flag page 5-13

0x8000.2440 UNIQID Read 32 32-bit Unique-ID page 5-13

0x8000.2700 RANDID0 Read 32 Bits 31-0 of Random ID page 5-13

0x8000.2704 RANDID1 Read 32 Bits 63-32 of Random ID page 5-13

0x8000.2708 RANDID2 Read 32 Bits 95-64 of Random ID page 5-13

0x8000.270C RANDID3 Read 32 Bits 127-096 of Random ID page 5-13

Programming Example

;*****************************************************************************

; Set SY SCON2 Bit 2 sets x16 SD RAM, Enable UART2

;*****************************************************************************

;

ldr r1,=0x104

add r11,r12,#0x1000

str r1,[r11,#0x100] ;SYSCON2 register at 0x8000.1100

;

;*****************************************************************************

; Set bits 1:2 in S YSCON3 for 74 MHz clock speed

;*****************************************************************************

;

ldr r1, =0x06

add r11,r12,#0x2000

str r1,[r11,#0x200] ;SYSCON3 register at 0x8000.2200

;

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

Operational Overview

Most of the functions represented in the SYSCON and SYSFLG registers are either described thoroughly i n other chapters or require little explanation. Below i s a detailed explanation of th ose that do not get covered sufficiently elsewhere in this manual.

Buzzer

The BUZ output pin on the EP 73xx is intended as a signal source for a basic annunciator. Two hardware sources and one software source are available for controllingthe frequency of the signal. In software mode, the state of the BZTOG bit in SYSCON1. It is the responsibility of the software executing on the EP73xx to toggle BZ TOG at the desired frequency. Software mode can be used to generate au dio tones with a controlled volume by varying the duty cy cle of the pulse that BZTOG is fed. BZMOD must be cleared to enable the use of BZTOG.

System Registers

BUZ output reflects the

Choices of hardware sources for chip timer TC 1. BUZFREQ selects between these two hardware sources. When BUZFREQ is cleared, the buzzer is generated from the TC1 timer underflow bit. The output changes every time the timer wraps around. The frequency depends on how timer TC1 is configured. Prescale mode for timer TC1 provides the greatest flexibility in the s election of a f requency for programming the timers. If B UZFR EQ is set, then a 500 Hz internal timer i s fed to

BUZ. Note that in the externally clocked 13 MHz mode, this clock will be 528 Hz

unless the OSTB bit (bit 12) in SYSCON2 is set.

BUZ is also used to created MCLK for external CODECs when the DAI is enabled. For

annunciator applications,

Debug Mode

Setting the debug mode bit in the SYSCON1 register allows internal memory accesses that would n ormally not be represented to appear on the ex ternal memory bus. In addition, the clock for this bus as well as the two interrupt signals that are generated by the interrupt controller are output on Port E.

When in debug mode, addition to its usual function as an external memory strobe. External memory accesses to the 0x5000.0000-0x5FFF.FFFF range will still cause addition to internal memory accesses.

BUZ include the timer clock and the output of on-

BUZ.SeeChapter 3 for a detailed description of

BUZ for MCLK in the DAI must be disabled.

nCS5 becomes the address strobe for the internal accesses in

nCS5 to assert in

The nFIQ and nIRQ signals between th e interrupt controller and th e ARM720T core will appear on Port E pins when debug mode is enabled. of nIRQ, and output the intern al bus clock. Using these extra signals requiresthat the data direction bits for Port E pins

EP7309/11/12 User’s Manual - DS508UM4 5-3

PE2 will represent nFIQ. To aid in following memory accesses, PE0 will

PE0-PE2 must be set to output.



PE1 will represent the state

System Registers

MaverickKey

™

Unique-ID

MaverickKey registers are unique ID numbers th at are p rogrammed f or use in secure web content and commerce. TheseIDs, burnedinto specificregisterlocations givethe OEMs a method for SD MI (Secure Digital Music Initiative) or any oth er authentication mechanism.

There is a single 32-bit Unique ID as well as a 128-bit random ID and are laser programmed at th e factory. These nu mbers can be used to match secure or copyrighted content with the I D of the 73xx device f or the purpose of transmitting said information over a secure connection.

The Unique ID is located at 0x8000.2440. The 128-bit random ID c an be found at 0x8000.2700-270C.

System Control Register Descriptions

System Control Register 1 (SYSCON1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD IRTXM WAKEDISEXCKE

ADCKSEL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SIREN CDENRX CDE NTXLCDEN DBGEN BZMOD BZTOG UART1ENTC2S TC2M TC1S TC1M Keyboard Scan

Address: 0x8000.0100, Read / Write Definition: The SYSCON1 system control register is a 21-bit read/write register

which controls some of the general configuration parameters for the EP73xx as well as the c ontrol and status of internal peripherals. All bits in this register are cleared upon system reset (nSYSRES).

Bit Descriptions:

Keyboard Scan:This four bit field defines the state of the keyboard column

driver. The following table defines these states.

Table 5-2: Keyboard Column Drive State

Value Column Drive State

0 All high

1 All low

2-7 All Hi-Z (tristate)

8 Column 0 high, all others Hi-Z

9 Column 1 high, all others Hi-Z

10 Column 2 high, all others Hi-Z

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Table 5-2: Keyboard Column Drive State (Continued)

Value Column Drive State

11 Column 3 high, all others Hi-Z

12 Column 4 high, all others Hi-Z

System Registers

13 Column 5 high, all others Hi-Z

14 Column 6 high, all others Hi-Z

15 Column 7 high, all others Hi-Z

TC1M: Timer counter 1 mode. Setting this b it sets TC1 clock to prescale

mode, clearing it sets free running mode.

TC1S: Timer counter 1 clock source. Setting this bit sets the TC1 c lock

source to 512 kHz, clearing it sets the clock source to 2 kHz.

Note: Refer to “Operational Overview” on page 3-2 for more information on timers

whenthePLLissetto90MHz.

TC2M: Timer counter 2 mode. Setting this b it sets TC2 clock to prescale

mode, clearing it sets free running mode.

TC2S: Timer counter 2 clock source. Setting this bit sets the TC2 c lock

source to 512 kHz, clearing it sets the clock source to 2 kHz.

Note: Refer to “Operational Overview” on page 3-2 for more information on timers

whenthePLLissetto90MHz.

UART1EN: Internal UART enable bit. Setting this bit en ables the internal

UART.

BZTOG: Bit to drive (i.e. tog gle) the buzzer output directly when software

mode of operation is selected (i.e. bit BZMOD=0).

BZMOD: Buzzer drive mode select. When set, the buzzer source is

determined by BUZFREQ. When cleared, the the state of the B ZTOG bit.

DBGEN: Forces the internal memory accesses (SRAM, boot ROM , register

space) to appear on the external address/data bus. Also outputs the status of the internal IRQ and FIQ outp uts of the interrupt

controller and the internal bus clock on bits of Port E. LCDEN: Enables the LCD controller when set. CDENTX: CODEC interface TX enable bit. Setting this bit enables the

CODEC interface for data transmission to an external CODEC

device. CDENRX: CODEC interface RX enable bit. Setting this bit enables the

CODEC interface for data reception f rom an external CODEC

device. Note that C DENRX and CDENTX must be enabled in

tandem, otherwise data may be lost. SIREN: SIR protocol encoding bit.This enables the IrDA input and output

from UART1 as opposed to logic level serial.

BUZ output reflects

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System Registers

ADCKSEL: Microwire/SPI peripheral clock speed select. This two bit field

selects the frequency of the ADC sample clock, which is twice the frequency of the synchronous serial ADC interface clock. The table below shows the available frequencies for operation when the CPU is operated in either PLL mode or in 13 MHz external clock mode. Th ese bits are also u sed to select th e master mode shift clock frequency for the SSI2 interface when set into master mode.

Table 5-3: ADC Sample Clock Settings

ADC Sample Frequency (kHz) — SMPCLK ADC Clock Frequency (kHz) — ADCCLK

ADCKSEL

90 MHz PLL Clock 13 MHz EXTCLK 90 MHz PLL Clock 13 MHz EXTCLK

00 9.8 8 8.4 4.9 4 4.2

01 39.2 32 33.8 19.6 16 16.9

10 156.8 128 135.4 78.4 64 67.7

11 313.6 256 270.8 156.8 128 135.4

EXCKEN: External expansion clock enable. If this bit is set, the

EXPCLK is

enabled continuously as a free running clock assuming that the main oscillator is running. Refer to CLKCTL bits[1-2] on SYSCON3.

EXPCLK corresponds to the memory bus frequency in

the table provided. This bit should not be left set all the time for power consumption reasons. If the system enters the Standby State, the

EXPCLK will be active during memory cycles to expansion slots

EXPCLK will become undefined. If this bit is clear,

that have extern al wait state generation enabled only.

WAKEDIS: Setting this bit disables wak ing up from the Standby State, via the

wakeup input.

IRTXM: IrDA TX mode bit. Th is bit controls the IrDA encoding strategy.

Clearing this bit means that each zero bit transmitted i s represented as a pulse of width 3/ 16th of the bit rate period. Setting this bit means each zero bit is represented as a pulse of width 3/16th of the period of 115,200-bit rate clock (i.e., 1.6 ms

regardless of the selected bit rate).

Setting this b it will use less

power, but will probably reduce transmission distances.

* The p ulse width will be reduced by 22.5% when operating at 90.3168 MHz.

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System Registers

System Control Register 2 (SYSCON2)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD BUZFREQCLKENSLOSTB RSVD SS2MAENUART2ENSS2RXE

Address: 0x8000.1100, Read / Write Definition: The SYSCON2 system control register is a 15-bit read/write register

Bit Descriptions:

SERSEL: SSI2/CODEC select. When this bit is cleared, SSI 2 is connected to

the external pins. When it is set, the COD EC interface is

connected. The value of this bi t is overridden when the DAISEL

bit of SYSCON3 is set, attaching the DAI to the pins. KBD6: The state of this bit determines how many of the Port A inputs are

OR’ed together to create the keyboard interrupt. When zero (the

reset state), all eight of the P ort A inputs will generate a keyboard

interrupt. When set high, only Port A bits 0 to 5 will generate an

interrupt from the keyboard. It is assumed that the keyboard row

lines are connected into Port A.

RSVD S S2TXENKBWEN SDRAMZKBD6 SERSEL

SDRAMZ: The bit determines the width of the SDRAM memory interface,

where: 0=32-bit SDRAM and 1=16-bit SDRAM. KBWEN: When set, the CPU will wake from the STANDBY or IDLE states

upon the assertion of a signal on any of the Port A inputs.

Enabling this feature will allow th e CPU to wake up regardless of

the state of the KBD INT interrupt mask (INTMR2 b it 0). SS2TXEN: Transmit enable for the synchronous serial interface 2. The

transmit side of SSI2 will be disabled until this bit is set. When set

low, this bit also disables the

mode, if the receive side is low. SS2RXEN: Receive enable for the synchronous serial interface 2. The receive

side of SSI2 will be disabled until this bit is set. When both

SSI2TXEN and SSI2RXEN are disabled, the SSI2 interface will be

in a power saving state. UART2EN: Internal UART2 enable bit. Setting this bit enables the internal

UART2.

SSICLK pin(to save power)in master

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System Registers

SS2MAEN: Master mode enable for the synchronous serial interface 2. When

low, SSI2 will b e configured for slave mode operation. When high, SSI2 will be configured for master mode operation. This bit also controls the directionality of the interface pins.

OSTB: This bit (operating system timing bit) is for use only with the

13 MHz clock source mode. Normally it w ill be set low, however when set high it will cause a 500 kHz clock to be generated for the timers instead of the 541 kHz which would normally be available. The divider to generate this frequency is not clocked when this bit is set low.

CLKENSL:

BUZFREQ: Selects the hardware source for the

CLKEN select.Whenlow,theCLKEN signal will be output on the RUN/CLKEN pin. When high, the RUN signal will be output on RUN/CLKEN.

BUZ pin. When set, a fixed

500 Hz ( 528 Hz in 13 MHz mode and 612 Hz at 90 MHz) clock is used as the source. When cleared, the overflow bit f rom timer TC1 is used as the clock signal.

System Control Register 3 (SYSCON3)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD ENPD67 128Fs Reserve

Address: 0x8000.2200, Read / Write Definition: The SYSCON3 system control register is a 11-bit read/write register

d-0

VERSN (read-only) ADCCK

NSEN

DAISEL CLKCTL1CLKCTL0ADCCO

Bit Descriptions:

ADCCON: Determines whether the ADC Configuration E xtension field

SYNCIO[16-31] is to be used for ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte SYNCIO[0 7] only is used for backwards compatibility. When this bit = 1, the ADC Configuration Extension field in the SYNCIO register is used for ADC Configuration d ata and the value in the ADC Configuration Byte (SYNCIO[0-6]) selects the length of the data (8-bit to 16-bit).

CLKCTL: This two-bit field determines the clock speed for the ARM720T

core, the clock speed for the memory bus, and the wait state scaling factor. When operating the CPU from an external 13 MHz clock, CLKCTL must be set to 00. The following table lists the options.

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Table 5-4: ARM720T Clock Speed Settings

System Registers

CLKCTL[1-0]

Value

00 18.432 MHz 18.432 MHz 1

01 36.864 MHz 36.864 MHz 2

10 49.152 MHz 36.864 MHz 2

11 73.728 MHz 36.864 MHz 2

DAISEL: When set, selects the DAI interface. Wh en cleared, selects the SSI

ADCCKNSEN:When set, ADC configuration data is transmitted on

VERSN: These read-only bits will always read ‘000’ on th e EP73xx. Reserved-0:This bit must always be set to zero. 128Fs: DAI Frame size select. When set, th e DAI will operate on 128-bit

Processor

Frequency

Refer to the Expansion Bus Controller chapter for explicit details

on programmed wai t states at different bus frequencies.

interface.

at the rising edge of the ADCCLK, and data is read b ack on the

falling edge of the

used.

frames. When cleared, the DAI uses 64-bit f rames.

Memory Bus

Frequency

ADCIN pin. When clear, the opposite edges are

Wait State

Scaling

ADCOUT

ENPD67: Port D bits 6 and 7 enable. When this bit is set, these bits on Port D

are enabled as GPIOs. When cleared, the pins assigned

PD[7] are used as SDQM[0] and SDQM[1] respectively for the

SDRAM interface. ENPD67 mu st be clear in order to properly use

the SDRAM interface.

PD[6] and

System Flag Register 1 (SYSFLG1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VERID ID BOOTBIT1BOOTBIT0SSIBUSYCTXFF CRXFE UTXFF1 URXFE1 RTCDIV

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CLDFLG PFFLG RSTFLG NBFLG UBUSY1DCD DSR CTS DID WUON WUDR DCDET MCDR

Address: 0x8000.0140, Read Only Definition: The SYSFLG1 system flag register is a 32-bit read only register. It

providesinformation regardingthe status of the CPU and associated peripherals.

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System Registers

Bit Descriptions:

MCDR: Media changed direct read. This bit reflects the inverted, non-

latched status of the me dia changed input.

DCDET: This bit will be set if a non-battery operated power supply is

powering the system (it is the i nverted state of the input pin).

WUDR: Wake up direct read. This bit reflects the non-latched state of the

wakeup signal.

WUON: This bit will be set if the system has been brought out of the

Standby State by a rising edge on the wakeup signal. It is cleared by a s ystem reset or by writing to the HALT or STDBY locations.

DID: Display ID nibble. This 4-bit nibb le reflects the l a tched state of the

four LCD data lines. The state of the four LCD data lines is latched by the LCDEN bit, and so it will always reflect the last state of these lines before the LCD controller was enabled.

CTS: This bit reflects the current status of the clear to send (CTS)

modem control input to UART1.

nEXTPWR

DSR: This bit reflects the current status of the data set ready (DSR)

modem control input to UART1.

DCD: This bit reflects the current status of the da ta carrier de tect (DCD)

modem control input to UART1.

UBUSY1: UART1 transmitter busy. This bit is set while UART1is busy

transmitting data, it is guaranteed to remain set until the complete byte has been sent, including all stop bits.

NBFLG: New battery flag. This bit will be set if a low to high transition has

occurred on the STFCLR location.

RSTFLG: Reset flag. This bit will be set if the RESET button has been

pressed, forcing the the STFCLR location.

PFFLG: Power Fail Flag. This bit will be set if the system has been reset by

the

nPWRFL input pin, it is cleared by writing to the STFCLR

location.

CLDFLG: Cold start flag. This bit will be set if the EP73xx has been reset

with a power on reset, it is cleared by writing to the STFCLR location.

nBATCHG input, it is cleared by writing to the

nURESET input low. It is cleared by writing to

RTCDIV: This 6-bit field reflects the number of 64 Hz ticks that have passed

since the last increment of the RTC. It is the output of the divide by 64 c hain that divides the 64 Hz tick clock down to 1 Hz for the RTC. The MSB is the 32 Hz output, the LSB is the 1 Hz output.

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System Registers

URXFE1: UART1 receiver FIFO empty. The meaning of this bit dep ends on

thestateoftheUFIFOENbitintheUART1bitrateandlinecontrol

holding register is empty. If the FIFO is enabled, the URXFE bit

will be set when the RX FIFO is empty.

UTXFF1: UART1 transmitFIFO full. The meaningof thisbit depends onthe

state of the UFIFOENbit in the UART1 bit rate and line control

holding register is full. If the FIFO is enabled, the UTXFF bit will

be set when the TX FIFO is full. CRXFE: CODEC RX FIFO empty bit. This will be set if the 16-byte CODEC

RX FIFO is empty. CTXFF: CODEC TX FIFO ful l bit. This will be set if the 16-byte CODEC TX

FIFO is full. SSIBUSY: Synchronous serial interface busy bit. This bit will be set while

data is being shifted in or out of the synchronous serial interface,

when clear d ata is valid to read. BOOTBIT[0-1]:These bits indicate the default (power-on reset) bus width of

the ROM interface. See Memory Configuration Registers for more

details on the ROM interface bus width. T he state of these bits

reflect the state of

table below.

Table 5-5: Default (Power-on Reset) Bus Width Settings

PE[1]

(BOOTBIT1)

(BOOTBIT0)

PE[0-1] during power on reset, as shown in the

PE[0]

Boot Option

0032-bit

018-bit

1016-bit

11Reserved

ID: Will always read “1” for the EP73xx device VERID: Version ID bits. Thes e 2 bits determine the version ID for the

EP73xx. Will read “01” for the initial version.

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System Registers

System Flag Register 2 (SYSFLG2)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD UTXFF2 URXFE2 RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD UBUSY

Address: 0x8000.1140, Read Only Definition: The SYSFLG2 system flag register is a 32-bit read only register. It

RSVD CKMODESS2TXUFSS2TX FFSS2RXFERESFRMRESVAL SS2RX

providesinformation regardingthe status of the CPU and associated peripherals.

Bit Descriptions:

SS2RXOF: Master/slave SSI2 RX FIFO overflow. This bit is s et when a write

is attempted to a full RX FIFO (i.e., wh en RX is still receiving data and the FIFO is full). This can be clearedin one of two ways:

1) Empty the FIFO (remove data from FIFO) and then

write to

SRXEOF l ocation.

2) Disable the RX (affects of disabling the RX will not take place until a full SSI2 clock cycle after it is disabled)

RESVAL: Master/slave SSI2 RX FIFO residual b yte present, cleared by

popping the residual byte into the SSI2 RX FIFO or by a new R X frame sync pulse.

RESFRM: Master/slave SSI2 RX FIFO residual byte present, cleared only by

anewRXframesyncpulse.

SS2RXFE: Master/slave SSI2 RX FIFO empty bit. This will be s et if the

16 x 1 6 RX FIFO is empty.

SS2TXFF: Master/slave SSI2 TX FIFO full b it. This will be set if the 16 x 16

TX FIFO is full. This will get cleared when data is removed from the FIFO or the EP73xx is reset.

SS2TXUF: Master/slave SSI2 TX FIFO Underflow bit. This wi ll be set if there

is attempt to transmit when TX FIFO is empty. This will be cleared when FIFO gets loaded with data.

CKMODE: This bit reflects the status of the

during

nPOR. When low, the PLL is running and the chip is

CLKSEL (PE[2])input,latched

operating in 18.432–73.728 MHz mode. When high the c hip is operating from an external 13 MHz clock.

UBUSY2: UART2 transmitter busy. This bit is set while UART2is busy

transmitting data; it is guaranteed to remain set until the complete byte has been sent, including all stop bits.

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System Registers

URXFE2: UART2 receiver FIFO empty. The meaning of this bit dep ends on

thestateoftheUFIFOENbitintheUART2bitrateandlinecontrol register. If the FIFO is disabled, this bit will be set when the RX holding register contains is empty. If the FIFO is enabled, the URXFE bit will be set when the RX FIFO is empty.

UTXFF2: UART2 transmitFIFO full. The meaningof thisbit depends onthe

state of the UFIFOENbit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set when the TX holding register is full. If the FIFO is enabled, the UTXFF bit will be set when the TX FIFO is full.

Clear all Start-up Reason Flag Register (STFCLR)

Address: 0x8000.05C0, Write Definition: A write to this location will clear all ‘Start-up reason’ flags in the

system flag status register SYSFLG. The SYSFLG register should be read to determine the reason why the chip was or entered operating state: (i.e., new battery installed). Any value may be written to this location.

32-bit Unique ID Register (UNIQID)

Address: 0x8000.2440, Read Only Definition: Unique-ID for SDMI compliance for secure internet applications.

This register is read-only, and is laser programmed at the factory.

Random ID 0 Register, bits 31-0 (RANDID0)

Address: 0x8000.2700, Read Only Definition: This represents th e first 32 bits of a 128 bit random ID created at the

factory. This is a read only register.

Random ID 1 Register, bits 63-32 (RANDID1)

Address: 0x8000.2700, Read Only Definition: This represents the second 32 bits of a 128 bit random I D created at

the factory. This is a read only register

Random ID 2 Register, bits 95-64 (RANDID2)

Address: 0x8000.2700, Read Only Definition: This represents the third 32 bit register of a 128 bit random ID

created at the factory. This is a read only register

Random ID 3 Register, bits 127-96 (RANDID3)

Address: 0x8000.2700, Read Only Definition: This represents the upper 32 bits of a 128 bi t random ID created at

the factory. This is a read only register

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System Registers

This page intentionally blank.

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Introduction

The EP73xx processor h as an internal and external boot mode. In each instance, the processor will fetch from ROM memory, either internal or external ROM respectively. The processor, in either mode, can be configured to interface with a big or little endian device.

Features

Chapter 6

6Processor Support

• Internal Boot ROM for bootloader as sistance

• External BOOT mode for system boot

• Big/little endian Configuration

Operational Overview

The EP73xx processor has two boot modes: internal and external. Each mode dictates the memory map and how the processor will perform. The p rocessor w ill boot into either mode by latching values s een on on the value, the processor will look to the internal BOOT ROM or to an external ROM (

Internal Boot Mode Characteristics

External Boot Mode

CS0) and being fetching instructions from there.

•Uniquememorymap

• Boots from internal Boot ROM

•WaitsforinputfromUART1

•Uniquememorymap

•Bootsbyfetchinginstructionsfromaddress0x0

nMEDCHG pin during power on reset. Based

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Processor Support

Internal Boot Mode

The 128 bytes of on-chip Boot ROM contain an instruction sequence that configure UART1 to receive up to 2 Kbytes of serial data which is then placed in the on -chip SRAM. Once the download is complete, the program counter jumps to SRAM to begin executing th e downloaded data. The purpose of this mode is to allow the downloaded code to facilitate programming of F LASH or other ROM device. See

Appendix A for code details.

Selection of the internal Boot ROM is accomplished by setting before power-on-reset. Th e value read is latched at the rising edge of

The processor at power-on-reset is in Standby state in this mode and

nMEDCHG (active low)

nPOR. WAKEUP must

be asserted in accordance with the power-up sequence to wake up the processor and putitintoOperatingState.

The memory map is as follows:

Table 6-1: Chip Select Address Ranges for On-Chip Boot ROM

Address Range Chip Select

0000.0000–0FFF.FFFF

1000.0000–1FFF.FFFF

2000.0000–2FFF.FFFF nCS[5]

3000.0000–3FFF.FFFF nCS[4]

4000.0000–4FFF.FFFF nCS[3]

5000.0000–5FFF.FFFF nCS[2]

6000.0000–6FFF.FFFF nCS[1]

7000.0000–7FFF.FFFF nCS[0]

CS[7] (Inter nal only)

CS[6] (Inter nal only)

External Boot Mode

Normal boot mode here involves the processor sensing that nMEDGHG is not active and then c hecks for boot width by looking at the pin values on the width of the boot device. Table 6-2 below is the interpretation by the processor.

Table 6-2: Boot Options

PE[1] PE[0] Boot Block (nCS0)

0032-bit

0 1 8-bit

1016-bit

1 1 Undefined

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PE[1:0] to determine

Processor Support

External ROM i.e., FLASH or EEP ROM will be configured for access by CS0 and the processor will begin fetching instructions from address 0x0. Before this will occur, the processor must be put into operating state as described in the power-up sequence. The default m emory map before the MMU is enabled and configured is as seen below. Note that any of the chip selects can be reconfigured once the processor is in operatingstateandproperlyfetchinginstructions. with the maximum number of wait states for either random or s equential accesses which will require re-programming of the MEMCFG1 register to optimize performance for ROM accesses.

Table 6-3: Memory Map in External Boot Mode

Address Contents Size

0xF000.0000 Reserved 256 Mbytes

0xE000.0000 Reserved 256 Mbytes

0xD000.0000 Reserved 256 Mbytes

0xC000.0000 SDRAM 64 Mbytes

0x8000.4000 Unused ~1 Gbyte

0x8000.0000 Internal registers 16 Kbytes

0x7000.0000 Boot ROM (nCS[7]) 128 bytes

0x6000.0000 SRAM (nCS[6]) 48,400 bytes

0x5000.0000 Expansion (nCS[5]) 256 Mbytes

0x4000.0000 Expansion (nCS[4]) 256 Mbytes

0x3000.0000 Expansion (nCS[3]) 256 Mbytes

0x2000.0000 Expansion (nCS[2]) 256 Mbytes

0x1000.0000 ROM Bank 1 (nCS[1]) 256 Mbytes

0x0000.0000 ROM Bank 0 (nCS[0]) 256 Mbytes

CS0 by default will a ccess memory

Note: For configuration of the individual chip selects, refer to the SDRAM/SRAM

chapter of the manual for full details.

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Processor Support

Endianess

The EP73xx uses little endian configuration for the internal registers. However, it is possible to connect to a big endian external memory device. The big-endian/littleendian bit in the i nternal registers sets whether the EP73xx treatswords in memory as being stored in big endian or little endian format.

• Big endian - least significant byte (LSB) read as most significant byte (MSB)

• Little endian - LSB read a s LSB

Table 6-4: Effect of Endianess on Read Operations

Data in

Address

(W/B)

Word + 0(W) 11223344 44 33 22 11 44 33 22 11 11223344 11223344

Word + 1(W) 11223344 44 33 22 11 44 33 22 11 44112233 44112233

Word + 2(W) 11223344 44 33 22 11 44 33 22 11 33441122 33441122

Word + 3(W) 11223344 44 33 22 11 44 33 22 11 22334411 22334411

Word + 0 (H) 11223344 44 33 22 11 44 33 22 11 00001122 00003344

Word + 1(H) 11223344 44 33 22 11 44 33 22 11 220000011 44000033

Word + 2(H) 11223344 44 33 22 11 44 33 22 11 00003344 00001122

Word + 3(H) 11223344 44 33 22 11 44 33 22 11 44000033 22000011

Word + 0 (B) 11223344 dc dc dc 11 44 dc dc dc 00000011 00000044

Word + 1 (B) 11223344 dc dc 22 dc dc 33 dc dc 00000022 00000033

Word + 2 (B) 11223344 dc 33 dc dc dc dc 22 dc 00000033 00000022

Word + 3 (B) 11223344 44 dc dc dc dc dc dc 11 00000044 00000011

Note: dc = don’t care

Memory

(as seen

by the

EP73xx)

Bold indicates active byte lane.

7:0 15:8 23:16 31:24 7:0 15:8 23: 16 31: 24 Big Endian

Byte Lanes to Memory/Ports/Registers

R0 Contents

Big Endian Memory Little Endian Memory

Little

Endian

Table 6-5: Effect on Endianess on Write Operations

Byte Lanes to Memory / Ports / Registers

Address

(W/B)

Word + 0 (W) 11223344 44 33 22 11 44 33 22 11

Word + 1 (W) 11223344 44 33 22 11 44 33 22 11

Word + 2 (W) 11223344 44 33 22 11 44 33 22 11

Word + 3 (W) 11223344 44 33 22 11 44 33 22 11

Word + 0 (H) 11223344 44 33 44 33 44 33 44 33

Word + 1 (H) 11223344 44 33 44 33 44 33 44 33

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Contents

Big Endian Memory Little Endian Memory

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24



Address

(W/B)

Table 6-5: Effect on Endianess on Write Operations (Continued)

Byte Lanes to Memory / Ports / Registers

Contents

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24

Big Endian Memory Little Endian Memory

Processor Support

Word + 2 (H) 11223344 44 33 44 33 44 33 44 33

Word + 3 (H) 11223344 44 33 44 33 44 33 44 33

Word + 0 (B) 11223344 44 44 44 44 44 44 44 44

Word + 1 (B) 11223344 44 44 44 44 44 44 44 44

Word + 2 (B) 11223344 44 44 44 44 44 44 44 44

Word + 3 (B) 11223344 44 44 44 44 44 44 44 44

Note: Bold indicates active byte lane.

Values seen above are not values stored into memory but what is actually seen on the memory bus. Given the architecture, only load and store instructions will be affected by endianess. For more information, refer to ARM Application Note 61, Big and Little

Endian Byte Addressing.

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Processor Support

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Introduction

External SDRAM on the EP7311 and EP 7312 is supported via the SDRAM controller. It allows industry standard SDRAM memories to be used within the address space of the EP73xx with no software overhead. The controller is attached to the ARM core through the internal high speed bus. It operates at a m aximum clock speed of

36.864 MHz (45 MHz when is CPU running at 90 MHz), providing all the necessary connections to interface to two banks of SDRAM. For information on implementing external SDRAM with the EP7312, s ee the Application N ote, “Interfacing the EP7312

with SDRAM” (AN218). The EP7309 does not include the SDRAM controller.

Features

Chapter 7

7SDRAM Controller

The SDRAM controller wi thin the EP7311 and EP7312 provides a convenient method for usinginexpensiveSDRAM devices as local memory.

It supports:

• Standard NEC or compatible devices in s izes of 16 to 256 Mbit, yielding a total memory capacity of 2 to 64 MByte

•UptotwoexternalbanksofSDRAM internal banks for each SDRAM device.

• A programmable bus width for accessing 16 or 32 bit wide banks

• Putting the SDRAM devices into self-refresh mode when the C P U is put into Standby

•Quadwordorquadhalfwordaccesseswithbytemaskselectsforshort reads

• Internal multiplexing of address lines for contiguous memory access

• Automatic JEDEC Standard No. 21-C compliant SDRAM initialization

SDRAM Register List

SDCS[0:1],andcontroloffour

Table 7-1: SDRAM Registers

Address Name Type Size Description Page

0x8000.2300 SDCONF R/W 16 SDRAM Control Register page 7-3

0x8000.2340 SDRFPR R/W 16 SDRAM Refresh Period Register page 7-4

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

SDRAM Controller

Programming Example

;*****************************************************************************

; Sample initialization code for the SDRAM controller on th e EDB7312:

;*****************************************************************************

;

ldr r0,=0x80000000 ; internal registers

ldr r3,=0x2000 ; local offset for memory

add r4,r3,r0 ; add & store offset in r4

mov r1,#0x522 ; CASLAT=2, SDSIZE=64 Mb, SDWIDTH=16, CLKCTL=0, SDACTIVE=1

str r1,[r4,#0x300] ; store in SDCONF

mov r1,#0x100 ; REFRATE=7.11 µS at 36 MHz BCLK

str r1,[r4,#0x340] ; store value in SDRFPR

;

Operational Overview

System Initialization

When the EP73xx encounters a power-on reset or a user reset, the SDRAM controller is disabled. T o configure the SDRAM controller:

1. Before initializing the controller, insure that the ENDP67 bit in the SYSCON3 register is set to its default value of 0, and the DRAMZ bit in SYSCON2 is s et for the appropriate SD RAM access width.

2. Load the requested refresh rate into the SDRFPR register.

3. Write the SDCONF with a configuration word containing the desired CASLAT,SDSIZE, SDWIDTH, and CLKCTL for your SDRAM devices plus a 1 i n the SDA CTIVE bit field to activate the controller.

4. Cache (MMU ) must be enabled for the SDRAM memory regions allocated to the sy stem software.

Immediately after initializing the controller, the SDRAM controller:

1. Sends a PRECHARGE comman d to all c onfigured SDRAM banks.

2. Sends a LOAD MOD E REGISTER command to all SDRAM devices in all banks.

3. Loads the mode registers on all SDRAM devices with a configuration word containing the CAS latency set in the CASLAT bits of SDCONF, a burst length of 4, and the configuration bits to enable sequential programmed length bursts.

4. Performs eight CBR (auto) refresh cycles to complete the initialization sequence.

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The SDRAM controller will continue to provide refresh cycles at the rate set in SDRFPR until the SDACTIVE bit is set to 0 or the CPU is reset.

Byte Masks

Pins PD6 and PD7 are multiplexed with the SDQM0 and SDQM1 signals, respectively. ENPD67, bit 10 in the SYSCON3 register, enables pins when set. This is useful in applications which do not involve the SDRAM interface. When cleared, pins from the SDRAM controller. ENPD67 must be cleared in order to properly use the SDRAM interface.

PD6 and PD7 represent the SDQM0 and SDQM1 output signals

SDRAM Register Descriptions

SDRAM Control Register (SDCONF)

SDRAM Controller

PD6 and PD7 as GPIO bits

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD SDACTIVE CLKCTL SDWIDTH[1:0] SDSIZE[1:0] RSVD CASLAT[1:0]

Address: 0x8000.2300, Read / Write Definition: SDRAM Configuration Data Register.

Bit Descriptions:

RSVD: Reserved. Unknown during read. CASLAT[1:0]: Number of clock cycles after CAS before the device is ready f or

reading or writing: 00 = reserved 01 = reserved 10 = CAS latency = 2 11 = CAS latency = 3 The default value is ‘10’ for CAS latency = 2.

SDSIZE[1:0]: Indicates the capacity of each SDRAM device:

00 = 16 Mbit 01 = 64 Mbit 10 = 128 Mbit 11 = 256 Mbit

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SDRAM Controller

SDWIDTH[1:0]: The width of each SD RAM device:

00 = 4 bits 01 = 8 bits 10 = 16 bits 11 = 32 bits This value is independent of the bus width setting and is necessary to differentiate the individual devices within a bank.

CLKCTL: Control over th e SDRAM c lock:

0 = SDRAM clock is permanently enabled except when in standby mode. 1 = SDRAM clock stops when the EP73xx is put into the STANDBY state or SDA CTIVE = ‘0’. There will be an additional delay of one clock cycle for any access request made when the SDRAM clock is stopped.

SDACTIVE: Enables the SDRAM controller:

0 = Disable SDRAM controller 1 = En able SDRAM c ontroller Thedefaultstateis‘0’.

SDRAM Refresh Period Register (SDRFPR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REFRATE

Address: 0x80002340, Read / Write Definition: SDRFPR is a register containing a 16-bit value representing the

interval between SDRAM refresh commands. The value programmed is in bus clock cycles. The following example calculates the value for REFRATE for a 16 µSrefreshperiodwitha bus clockof 36 MHz:

16E-6 * 36E6 = 576

The refresh timer is set to 256 by nPOR to ensure a refresh tim e of better than 16 µS even at 13 MHz. This register should not be programmed to a value below 2. Otherwise, the bus may become locked.

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Introduction

The SRAM/Expansion bus controller allows for control and access to internal/external SRAM memory as well as external peripherals th at require read/write access to the EP73xx memory bus. The following description will encompass both situations and detail the programming and configuration of each of bus.

Features

Chapter 8

8SRAM/Expansion Bus Controller

• Six programmable chip selects CS0-CS5

• CS6 (Internal SRAM) chip select pre-programmed

•

CS7 (Internal Boot ROM) chip select pre-programmed

• Wait states programmable from 0-8

• Bus width programmable from 8-32 bits wide

SRAM / Expansion Bus Register List

Table 8-1: SRAM / Expansion Bus Registers

Address Name Type Size Description Page

0x8000.0180 MEMCFG1 R/W 32 Memory Config. Reg 1 page 8-3

0x8000.01C0 MEMCFG2 R/W 32 Memory Config. Reg 2 page 8-5

Programming Example

;*****************************************************************************

; Expansion bu s settings in this example are based on the bootmode pins PE1 and

PE0 at nPOR (power-on-reset) as (0,0) with the PLL clock set at 74 MHz

;

nCS0 = 32-bit, 3 wait states

;

nCS1 = 32-bit, 2 wait states

;

nCS2 = 16-bit, 8 wait states

; ;

nCS3 = 32-bit, 1 wait state

nCS4 =8-bit,1waitstate

;

nCS5 = 32-bit, 8 wait states

;

;*****************************************************************************

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

SRAM/Expansion Bus Controller

MemConfig1value EQU 0x3c011814 ; CS0-CS3 configuration values

MemConfig2value EQU 0x0000001e ; CS6(Internal SRAM) CS7(Internal Boot ROM)

;*****************************************************************************

;configurenCS0 - nCS3

;*****************************************************************************

;

ldr r1, =MemConfig1value

str r1,[r12,#0x0180] ; MEMCFG1 = 0x8000.0180

;

;*****************************************************************************

;configurenCS4 - nCS5

;*****************************************************************************

;

ldr r1, =MemConfig2value

str r1,[r12,#0x01c0] ; MEMCFG2 = 0x8000.01c0

;

Operational Overview

All chip selects can be configured as 8, 16, or 32-bit wide memory to interface to a wide range of external hardware. Each chip select has a default address at power on reset, but can change based on how the pagetable in th e MMU remaps the memory.

At power on reset, the initial setting for the Bus width for all chip selects will depend on the state of selects. Wait states are programmable f rom 1-8 additional clocks.

PE1 and PE0 at that time. Th e software can then reconfigure the chip

There are two internal registers for p rogramming the chip selects: MEMCFG1 and MEMCFG2. These registers are described below.

Note: At power-on-reset or system reset, all values are cleared.

There are a total of six chip selects CS0-CS5, that are user controlledto access memory or devices throughout th e system. Programming includes, bus width from 8-32 bits, wait states, and bus clock access, in the event that the interface is not asynchronous.

Note: The memory area decode by CS[6] is reserved for on-chip SRAM and does not require programming.The default configuration is 32-bit wide and no wait states.CS[7]accesses internal boot ROM and defaults to 8-bit wide and no wait states. No additional programming is possible.

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SRAM/Expansion Bus Controller

SRAM / Expansion Bus Register Descriptions

Memory Configuration Register 1 (MEMCFG1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

nCS[3] Configur ation nCS[2] Configuration

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nCS[1] Configur ation nCS[0] Configuration

Address: 0x8000.0180, Read / Write Definition: Each of the chip selects contain the same 8-bit programmable bit

fields that make up the entire configuration. The table below describes each 0-7 bit configuration for all of the chip selects in MEMCFG1 and MEMCFG2.

76 5:2 1:0

CLKENB SQAEN Wait States Field Bus width

Bit Descriptions:

Bus Width[0:1]:The table below indicates what to program into the 2-bit field.

PE1 and PE0 are examined at power-on-reset. Based on those

values,theBusWidthfieldvaluescanbedetermined.Thiswill require examining the external hardware to know the default state of each pin at power-on-reset.

PE1 and PE0 are both low at nPOR,thebuswidthfield

Ex. If would then be 00 for the chip select to be programmed. This assumes the external memory is 32 bits wide.

Table 8-2: Bus Width Selection Settings

Bus Width Field Expansion Transfer Mode

00 32-bit wide bus access Low, Low

01 16-bit wide bus access Low, Low

10 8-bit wide bus access Low, Low

11 Reserved Low, Low

00 8-bit wide bus access Low, High

01 Reserved Low, High

10 32-bit wide bus access Low, High

11 16-bit wide bus access Low, High

00 16-bit wide bus access High, Low

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

Port E bits 1,0 during

nPOR reset

SRAM/Expansion Bus Controller

Table 8-2: Bus Width Selection Settings

Bus Width Field Expansion Transfer Mode

01 32-bit wide bus access High, Low

10 Reserved High, Low

11 8-bit wide bus access High, Low

Port E bits 1,0 during

nPOR reset

Wait States Field[2:5]: There are two tables to use to program a chip select wi th

a specific number of wait states. One table is specifically for 13 and 18 MHz operation and the other is for 36 MHz and above. The operating speed of the bu s will determine which table is used.

Table 8-3: Wait States at 13 / 18 MHz Operation

13 MHz / 18 MHz Operation

Bit 3 Bit 2 Bit 1 Bit 0 Wait States Random Wait States Sequential

xx00 4 3

xx01 3 2

xx10 2 1

xx11 1 0

Table 8-4: Wait States at 36 MHz Operation

36 MHz Operation

Bit 3 Bit 2 Bit 1 Bit 0 Wait States Random Wait States Sequential

0000 8 3

0001 7 3

0010 6 3

0011 5 3

0100 4 2

0101 3 2

0110 2 2

0111 1 2

1000 8 1

1001 7 1

1010 6 1

1011 5 1

1100 4 0

1101 3 0

1110 2 0

1111 1 0

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SRAM/Expansion Bus Controller

SQAEN[6]: Sequential access enable. Settingthis bit will enable the sequential

accesses that are on a quad word boundary to take advantage of faster access times from devices that s upport page mode. The sequential accesses will be fau lted after four words (to allow video refresh cy cles to occur), even if the access is part of a longer sequential access. In addition, when this bit is not set, nonsequential accesses will have a single idle cycle inserted at least every four cycles so that the chip select is de-asserted periodically between accesses for easier debug.

CLKENB[7]: Expansion clock enable. Setting this bit enables the

active during accesses to the s elected expansion device. This will provide a timing reference for devices that need to extend bus cycles using the page mode) accesses will result in a continuous clock. This bit will only affect

18.432 MHz mode. ) When operating in 13 MHz mode, the

EXPCLK pinisaninput,soitisnotaffectedbythisregisterbit.To

saver power internally, it should always be set to zero when operating at 13 MHz m ode.

Memory Configuration Register 2 (MEMCFG2)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

nCS[7] Configur ation nCS[6] Configuration

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nCS[5] Configur ation nCS[4] Configuration

Address: 0x8000.01C0, Read / Write Definition: See “Memory Configuration Register 1 (MEMCFG1)” details for

programming the remaining chip selects. Same programming features and requirements apply.

EXPRDY input. Back-to-back (but not necessarily

EXPCLK when the PLL is being used (i.e., in 73.728-

EXPCLK to be

Note: CS6 and CS7 are not configurable.

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SRAM/Expansion Bus Controller

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Introduction

The LCD interface provides all the necessary control signals to interface directly to a single panel multiplexed LCD. It is programmable for different line lengths, bits-perpixel and refresh rates. The frame buffer can reside in either SDRAM and RAM memory. 1/4 VGA support is typical but 1/2 VGA (monochrome) support is possible assuming a refresh rate above 40 Hz is not required.When the CPU speed is set to 74 MHz, the bus speed will be 36 MHz. When the CPU speed is set to 90 Mhz, the bus speed will be 45 MHz. Calculations made using the formulas in this chapter must take C PU and bus speed variables into account.

Features

Chapter 9

9LCD Interface

• 1-2-4 bpp (bits per pixel)

• Programmable panel size to a maximum of 1024x256 at 4 bps

• Relocatable Frame Buffer (SRAM or SD RAM)

• Programmable refresh rates

•16grayscalevalues

• Color screen interface capability

LCD Register List

Address Name Type Size Description Page

0x8000.02C0 LCDCON R/W 32 LCD Control Register page 9-7

0x8000.0580 PALLSW R/W 32 Least Sig. Word Palette page 9-8

0x8000.540 PALMSW R/W 32 Most Sig Word Palette page 9-8

0x8000.1000 FBADDR R/W 4

Table 9-1: LCD Registers

Frame Buffer Start Address

page 9-9

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

LCD Interface

Programming Example

;************************************************************************

; LCD Controller C onfiguration for a 640x240x4 b pp LCD Panel (ALPS) ; AC P rescale = 0x18 (LCD Manufacturer Nu mber) ;RefreshRate=60Hz ; LCD Palettes require 1 to 1 mapping between pixel value to intensity ; Pixel Prescale = 3

;************************************************************************

;

LCDCON EQU 0xF01CF2BF ; Value for LCDCON register for above req.

PALLSW EQU 0x76543210 ; 1-1 mapping for least sig. palette reg.

PALMSW EQU 0xFECDBA98 ; 1-1 mapping for most sig. palette reg.

LCDFRAME EQU 0xC ; LCD Frame Buffer Start Location (physical)

ldr r1, =LCDCON

str r1, [r12, #0x02C0] ; store to LCDCON at 0x8000.02C0

ldr r1, =PALLSW

str r1, [r12, #0x0580] ; store to PALLSW at 0x8000.0580

ldr r1, =PALMSW

str r1, [r12, #0x0540] ; store to PALMSW at 0x8000.0540

ldr r1, =LCDFRAME

mov r1,r1, lsl #28 ; 0xC in upper 8 bits

ldr r11, =0x80001000

str r1, [r11, #0x0] ; OxC for location 0xC0000000(SDRAM)

;*****************************************************************************

; Configuration Complete. LCD Controller can now be turned on

;*****************************************************************************

;

ldr r1, =0x1000 ; Enable LCDEN bit

ldr r0, [r12, #0x100] ; Load value from SYSCON1

orr r0,r0,r1

str r0, [r12, #0x100] ; LCDEN bit set in SYSCON1

;

Operational Overview

LCD Controller External Memory

The LCD frame buffer is m app ed to any external SRAM or SDRAM by means of the frame bufferstart address registers FBA DD R. The eight bit value stored in the register represents th e physical location of this memory region (before the MMU is turned on), not the virtual memory region. This memory must be controlled by one of the processor chip selects.

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

The frame buffer start address begins with 0x0000000 within each memory region to the value programmed with the FBADDR will define only the most significant byte of the start address. F or instance, programming the register with 0xC will define the frame buffer start address to be 0xC0000000. The register can therefore be programmed with values from 0x1 to 0xC, d epending on the external RAM/SDRAM memory location. Values0x7 and 0x8 are dedicated system memory for the p rocessor Boot ROM and internal registers respectively so these values are not valid for the LCD frame buffer. This region cannot be used. If internal SRAM is used (FBADDR = 0x6), the amount of storage is limited to 48 Kbytes but i s accessible. Calculating total memory requirements will be necessary prior to using this fixed memory region.

The screen is mapped as on contiguous b lock of memory where each horizontal line of pixels is mapped to a set of consecutive bytes or words. Pixel 0 represent the LSB in a word wide access of the frame buffer memory consistent with l ittle endian configuration.

LCD DMA Controller

LCD Interface

The DMA controller for the LCD controller is dedicated to the controller and is designed to fetch from the frame buffer memory and fill a nine-word deep FIFO. Once the controller is enabled, it will continue to operate without requiring service from the CPU. The DMA controller will request data when there are only 5 words remainingin the FIFO. The DMA bandwidth canbe calculatedbased on the following criteria:

•refreshrate

• panel size

•bitsperpixel

1/2 VGA with 4 bpp@ 80 Hz refresh = (640x240) x 4 bps x 80 Hz = 6.14 Mb ytes/s. This assumes that the frame buffer is stored in a 32-bit-wide memory. Sixteen-bitwidememorycanbeusedwhichwilldoubletheaccesstimeandtheDMAlatency

DMA latency calculations are based on a 32-bit-wide memory. Assuming 1/2 VGA, 5 words for a FIFO fill, 80 Hz refresh rate at 4 bpp, the maximum allowable latency can only be ap proximately:

(5 words x 32 bits/word)/(640x240x4 bppx80 Hz) = 3.25 µs.

This number represents the worst case latency or the total number of cycles from when the DMA request appears to when the first DMA data word actually becomes available or is written to the FIFO. DMA has the highest priority in the system so the FIFO fill will always occur next in sequence.

The maximum number of cycles between a DMA request for data and the first word seen in the FIFO is 42. At 13 MHz bu s speed (77 n s cycle time), th e latency is approximately 3.23us. At 18 MHz, the latency is reduced to 2.26 µs. At 36 MHz bus speed, or 74 MHz internal CPU speed, the number is even furth er reduce to about

1.49 µs. The calculation is m ore c omplex. The total n umber of cycles at 36 MHz is (12x4) + 7 = 55.

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LCD Interface

Latency and access times will need to be calculated prior to selecting an LCD panel to guarantee available bandwidth for the rest of the system. It should be noted that the refresh rate is not affected by the total number of pixels.

Gray Scale

The figure below shows the organization of the video map for all bits-per-pixel combinations. As seen the in the diagram, the gray s cale blocks represent the two 32bit palette registers. Each palette register represents eight 4-bit n ibbles for a total of 16 nibbles.

Gray scale creates an intensity for each of the pixel values stored in memory. Four bits-per-pixel corresponds to a theoretical color depth of 16. Two bits-per-pixel corresponds to a color depth of four and so on. Since gray s cale values 7 and 8 create the same intensity, the actual color depth for 4bpp is 15. The effect is created by simply controlling the amount of time the pixel remains on. See the Gray scale value to Color Mapping diagram for more details.

An example of this would be the value 12, that is stored in a nibble in the framebuffer memory. If the 4 bpp is programmed into the controller, the value 12 is mapped to the LCD palette register for gray scale value for pixel value 12, assuming a one-to-one correspondence between the number 12 in memory, and the i ntensity (Gray scale value), this pixel will have a duty cycle of about 11/15 or will be lit approximately

73.3% of the time. Programming the controller includes the following

• LCDCON: Configuration interface for a specific LCD panel

• PALLSW/PALMSW: Sets the palette registers

• FBADDR: Sets the start location in system memory for the LCD frame buffer

• SYSCON1: LCDEN bit turns LCD controller on (enabled).

Note: LCD controllermust not be enabled until the above r egisters are programmed.

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Pixel 1 Pixel 2 Pixel 3 Pixel 4

LCD Interface

Gray scale

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

4 Bits per pixel

Pixel 1 Pixel 2 Pixel 3 Pixel 4

Gray scale Gray scale

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

2 Bits per pixel

Pixel 1 Pixel 2 Pixel 3 Pixel 4

Gray scale

Gray scale Gray scale

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Figure 9-1. Pixel Gray Scale Mapping

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Gray scale Gray scale

1 Bit per pixel

LCD Interface

Hardware Interface

DD3 DD2 DD0DD1

1,1 1,2

1,3

1,4

1,640

640x240 LCD Screen

240,1

Figure 9-2. LCD Data to Pixel Mapping

DD3-DD0 carries the data that is output from th e gray scale palette registers. D ata for

240,640

each pixel will begin with the first nibble (assuming 4 bpp) at the beginning of the framebufferwhich willcorrespond to the first pixel location as seen above. For 2 bpp and 1 bp p, the same h ardware interface applies.

Color LCDs

The EP73xx does not directly support color LCDs. However, with minimal external logic and a slight modification to the LCD driver, color can be supported. There are no changes required for the control registers, on ly the data stored in the frame buffer.

• Maximum 3,375 simultaneous c olor s upport (i.e. 15 different colors per sub-pixel)

• 1/4 VGA color STN display maximum size

• 120 x 320 x 8 b pp VGA color TFT display maximum size.

The external hardware splits will be routed through a shift register, the other ha lf route to the LCD screen directly. CL2 (pixel cl ock) is halved by means of a D-flip flop which is fed to both the LCD screen and the shift register. The result is 8 bits of data present at the LCD screen at the same time along with its pixel clock and remaining control signals. See

Application Note 179 for a completeschematic.

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DD3-DD0 to create 8 bits of information. Half of the data

LCD Register Descriptions

LCD Control Register (LCDCON)

LCD Interface

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GSMD GSEN AC Prescale Pixel Prescale Line

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Length VIdeo Buffer Size

Address: 0x8000.02C0, Read / Write

Bit Descriptions:

Video Bu ffer Size [0:12]:Total number of bits in the video display buffer.

Formula: (Total bits in video buffer/128) - 1 ex. 640x240 LCD with 4 bits-per-pixel Video Buffer: 640x240x4 = 614400 Video Buffer Size = (614400/128)-1 = 4799 or 0x12BF

Note: Minimum value for this field is 3.

Line Length[13:18]:Number of p ixels in one com plete line (row).

Formula: (Number of pixels per line/16) - 1 ex. 640x240 LCD Line length = (640/16) - 1 = 39 or 0x27

Note: Minimum value for this field is 1.

Pixel Prescale[19:24]: Sets the pixel rate prescale and is always derived from

36 MHz clock when in PLL mode or 13 M Hz when using the external 13 MHz external c rystal. Pixel Prescale = ((CPU clock (Hz))/(Refresh Rate x Total pixels) - 1 Pixel Rate = (CPU Clock (MHz)/(Pixel P rescale + 1) ex. 640x240 in PLL mode(18-74 MHz CPU clock). 70 Hz refresh rate is desired.

Pixel Prescale = (36x10 down)

Pixel rate = (36x10 rate is: 12.288x10

Note: If the EP73xx is running at 90 M Hz, the data bus r ate would increase f rom 36 to

45 MHz.

AC prescale[24:19]: Sets the LCD AC bias frequency. This frequency is the

requiredAC bias frequency for a given manufacturer’s LC D p late. it is derived from the frequency of the line clock (CL[1]). The LCD M signal will toggle after n+1 counts of the line clock where is M is the number programmed into this field.

EP7309/11/12 User’s Manual - DS508UM4 9-7

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)/(70x640x240) - 1 = 2.428 or 2 (round

)/((2 + 1) = 12.288 MHz so the actual refresh

/(640x240) = 80 Hz

LCD Interface

GSEN[30]: Gray scale enable bit. Enables gray scale output to the LCD.

When cleared, each bi t in the vi deo map directly corresponds to a pixel in the display.

GSMD[31]: Gray scale mode bit. Clearing this bit sets the controller to 2 bpp

(4-gray scale). Setting this bits enables 4 bpp (16-gray scale).

LCD Palette Registers

Least S ignificant Word (PALLSW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Gray scale value for pixel value 7 Gray scale value for pixel value 6 Gray scale value for pixel value 5 Gray scale value for pixel value 4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Gray scale value for pixel value 4 Gray scale value for pixel value 3 Gray scale value for pixel value 2 Gray scale value for pixel value 1

Address: 0x8000.0580, Read / Write

Most S ignificant Word (PALMSW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Gray scale value for pixel value 15 Gray scale value for pixel value 14 Gray scale value for pixel value 13 Gray scale value for pixel value 12

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Gray scale value for pixel value 11 Gray scale value for pixel value 10 Gray scale value for pixel value 9 Gray scale value for pixel value 8

Address: 0x8000.0540, Read / Write

Bit Descriptions:

The least and most significant word of the LCD palette registers (read/write) map the pixel value stored i n the frame buffer to a physical gray scale level. The two 32-bit registers define all gray scale levels for a total of 4 bpp. If 2 bpp is required, only the palette least significant word need be programmed. At 1 bpp, only the first two nibbles in the least significant register are required to be programmed.

Table 9-2 on page 9-8 represents the mapping of the pixel value from memory to the

gray scale value programmed into the registers.

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Table 9-2: Gray Scale Value to Color Mapping

Gray scale Value Duty Cycle % Pixels Lit % Step Change

0 0 0% 11.1%

1 1/9 11.1% 8.9%

2 1/5 20.0% 6.7%

3 4/15 26.7% 6.6%

4 3/9 33.3% 6.7%

5 2/5 40.0% 5.4%

6 4/9 44.4% 5.6%

7 1/2 50.0% 0.0%

8 1/2 50.0% 5.6%

9 5/9 55.6% 5.4%

10 3/5 60.0% 6.7%

11 6/9 66.7% 6.6%

12 11/15 73.3% 6.7%

13 4/5 80.0% 8.9%

14 8/9 88.9% 11.1%

15 1 100%

LCD Interface

LCD Frame Buffer Start Address (FBADDR)

Address: 0x8000.1000, Read / Write Definition: This register contains the start address for the LCD Frame Buffer. It

assumes that the frame buffer starts at location 0x0000000 within each chip select memory region. Value programmed will set the start address in system memory. On reset, th e default value i s 0xC which corresponds to the physical l ocation of 0xC0000000.

The register is 4 bits wide and m ust only be programmed when the LCD is disabled (LCDEN bit in SYSCON1 is cleared).

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LCD Interface

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Cirrus Logic EP73xx User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

List of Figures

List of Tables

Overview

Processor

Chapter 1

1Introduction

Peripherals

Memory Map and Register List

Global Memory Map

Internal Register Map

Pin Description

External Signal Functions

DAI/CODEC/SSI2 Pin Multiplexing

Output B i-Directional Pins

Block Diagrams

References

Introduction

Features

Chapter 2

2CPU Core

Programming Register List

Block Diagram

Programming Examples

Operational Overview

Cache

Write Buffer

Debug Interface

CPU Register Definitions

ARM720T Core Coprocessor Registers

CPU Clocks

Real Time Clock (RTC)

Real Time Clock Characteristics and Interface Requirements

On-Chip PLL

PLL Clock Characteristics and Interface Requirements

Programming Example

PLL Multiplier Write Register (PLLW)

PLL Multiplier Read Register (PLLR)

CPU State Control

Standby State

Clock Status

State Control Register Descriptions

Enter the Standby State Register (STDBY)

Idle State

Enter the Idle State Register (HALT)

Power Up Sequence

RESET

Introduction

Features

Chapter 3

3Timers

Timer Register List

Programming Example

Operational Overview

Free Running Mode

Prescale Mode

RTC Timer

Timer Register Descriptions

Timer Counter 1 Data Register (TC1D)

Timer Counter 2 Data Register(TC2D)

Real Time Clock Data Register (RTCDR)

Real Time Clock Match Register (RTCMR)

Introduction

Features

Chapter 4

4Interrupt Controller

Interrupt Register List

Programming Examples

Operational Overview

Interrupt Types and Priorities

Interrupt Operation

Interrupt Listing

Interrupt Latencies in Different States

Operating State

Idle State

Standby State