Cirrus Logic EP7309 User Manual

FEATURES

LCD

Controller

Boot ROM

MaverickKey

ARM720T

ARM7TDMI CPU Core

MMU

8 KB

Cache

Write

Buffer

Internal Data Bus

EPB Bus

SRAM &

FLASH I/F

On-chip SRAM

48 KB

ICE-JTAG

Clocks &

Timers

Keypad&

Touch

Screen I/F

Interrupts,

PWM & GPIO

Bus

Bridge

(2) UARTs

w/ IrDA

Power

Management

Serial

Interface

Digital

Audio

Interface

ARM720T Processor

— ARM7TDMI CPU — 8 KB of four-way set-associative cache — MMU with 64-entry TLB — Thumb code support enabled

Ultra low power

— 90 mW at 74 MHz typical — 30 mW at 18 MHz typical — 10 mW in the Idle State — <1 mW in the Standby State

Advanced audio decoder/decompression capability

— Supports bit streams with adaptive bit rates — Allows for support of multiple audio decompression

algorithms (MP3, WMA, AAC, ADPCM, Audible, etc.)

EP7309 Data Sheet

High-performance,

Low-power, System-on-chip

with Enhanced

Digital Audio Interface

OVERVIEW

The Maverick™ EP7309 is designed for ultra-low-power applications such as digital music players, internet appliances, smart cellular phones or any hand-held device that features the added capability of digital audio decompression. The corelogic functionality of the device is built around an ARM720T processor with 8 KB of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like Microsoft Windows® CE and Linux®.

BLOCK DIAGRAM

http://www.cirrus.com

(cont.)

USER INTERFACE

SERIAL PORTS

MEMORY AND STORAGE

Copyright Cirrus Logic, Inc. 2011

DS507F2

EP7309

High-Performance, Low-Power System on Chip

FEATURES (cont)

Dynamically programmable clock speeds of 18, 36, 49, and

74 MHz

48 KB of on-chip SRAM

™

MaverickKey

IDs — 32-bit unique ID can be used for SDMI compliance — 128-bit random ID

LCD controller

— Interfaces directly to a single-scan panel monochrome

STN LCD

— Interfaces to a single-scan panel color STN LCD with

minimal external glue logic

Full JTAG boundary scan and Embedded ICE



support

Integrated Peripheral Interfaces

— 8/32/16-bit SRAM/FLASH/ROM Interface — Digital Audio Interface providing glueless interface to

low-power DACs, ADCs and CODECs

— Two Synchronous Serial Interfaces (SSI1, SSI2)

OVERVIEW (cont.)

— CODEC Sound Interface —88 Keypad Scanner — 27 General Purpose Input/Out put pins — Dedicated LED flasher pin from the RTC

Internal Peripherals

— Two 16550 compatible UARTs — IrDA Interface — Two PWM Interfaces — Real-time Clock — T wo general purpose 16-bit timers — Interrupt Controller — Boot ROM

Package

—208-Pin LQFP —256-Ball PBGA

The fully static EP7309 is optimized for low power

dissipation and is fabricated on a 0.25 micron CMOS process

The EP7309 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of

2.5 V–3.3 V. The device has three basic power states: operating, idle and standby.

MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism.

The EP7309 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal‚ CS43L41/42/43 low-power audio DACs and the Crystal‚ CS53L32 low-power ADC. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions.

Simply by adding desired memory and peripherals to the highly integrated EP7309 completes a low-power system solution. All necessary interface logic is integrated on-chip.

2 Copyright Cirrus Logic, Inc. 2011

EP7309

High-Performance, Low-Power System on Chip

Table of Contents

FEATURES ..................................................................................................................................................................2

OVERVIEW..................................................................................................................................................................2

Processor Core - ARM720T ..................................................................................................................................6

Power Management ..............................................................................................................................................6

MaverickKey™ Unique ID .....................................................................................................................................6

Memory Interfaces .............................. ... .... ... ... ... ... .... ... ....................................... ... ... ... .... .....................................6

Digital Audio Capability ... ...................................... .... ... ... ... .... ... ... ... ......................................................................6

Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................6

Digital Audio Interface (DAI) .. ... .... ... ... ... .......................................... .... ... ... ... ... .... ... ... ... .........................................7

CODEC Interface ..... ... .... ... ... ... .... ... ... ... .... ... ....................................... ... ... ... ... .... ... ... ... .... .....................................7

SSI2 Interface ........................................................................................................................................................7

Synchronous Serial Interface ................................................................................................................................8

LCD Controller .......................................................................................................................................................8

Interrupt Controller ................................................................................................................................................8

Real-Time Clock ....................................................................................................................................................8

PLL and Clocking ..................................................................................................................................................9

DC-to-DC converter interface (PWM) ....................................................................................................................9

Timers ...................................................................................................................................................................9

General Purpose Input/Output (GPIO) ..................................................................................................................9

Hardware debug Interface .....................................................................................................................................9

Internal Boot ROM ........................... ... ... .... ... ....................................... ... ... ... ... .... ... ... ..........................................10

Packaging ..................................... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ... ....... .............................................10

Pin Multiplexing ...................................................................................................................................................10

System Design ....................................................................................................................................................11

ELECTRICAL SPECIFICATIONS .................................................... ................. ................ ................ .12

Absolute Maximum Ratings .................................................................................................................................12

Recommended Operating Conditions .................................................................................................................12

DC Characteristics ....................................... ... ....................................... ... ... ... .... ... ... ... .... ...................................12

Timings ........................................................................................... .............. ............................ ..........14

Timing Diagram Conventions ...................... ....................................... ... .... ... ... ... .... ... ... ... ... .... ... ................14

Timing Conditions ..................... ... .... ... ... ... ... ....................................... ... .... ... ... ... .... ... ... .............................14

Static Memory ......................................................................................................................................................15

Static Memory Single Read Cycle .............................................................................................................16

Static Memory Single Write Cycle ..............................................................................................................17

Static Memory Burst Read Cycle ...............................................................................................................18

Static Memory Burst Write Cycle ...............................................................................................................19

SSI1 Interface ......................................................................................................................................................20

SSI2 Interface ......................................................................................................................................................21

LCD Interface ......................................................................................................................................................22

JTAG Interface ................................ ... ... ....................................... ... .... ... ... ... ... .... ................................................23

Packages ...................................................................................................................... .............. ........24

208-Pin LQFP Package Characteristics ..............................................................................................................24

208-Pin LQFP Package Specifications ......................................................................................................24

208-Pin LQFP Pin Diagram .......................................................................................................................25

208-Pin LQFP Numeric Pin Listing ............................................................................................................26

256-Ball PBGA Package Characteristics ............................................................................................................29

256-Ball PBGA Package Specifications ....................................................................................................29

256-Ball PBGA Pinout (Top View)) ............................................................................................................30

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EP7309

High-Performance, Low-Power System on Chip

256-Ball PBGA Ball Listing ........................................................................................................................ 30

JTAG Boundary Scan Signal Ordering ............ ... ... ... ... .......................................... .... ... ...................................... 34

CONVENTIONS .................................................................................................................................39

Acronyms and Abbreviations .............................................................................................................................. 39

Units of Measurement ......................................................................................................................................... 39

General Conventions .......................................................... ... ... .... ... ... ... .... ... ... ... ... ............................................. 40

Pin Description Conventions ............................................................................................................................... 40

.................................................................................................................................................................. 40

Ordering Information .......................................................................................................................41

Environmental, Manufacturing, & Handling Information .............................................................41

Revision History ..............................................................................................................................42

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EP7309

High-Performance, Low-Power System on Chip

List of Figures

Figure 1. A Maximum EP7309 Based System ....... ... ....................................... ... ... ... .... ................................................11

Figure 2. Legend for Timing Diagrams .........................................................................................................................14

Figure 3. Static Memory Single Read Cycle Timing Measurement ...............................................................................16

Figure 4. Static Memory Single Write Cycle Timing Measurement .................. ................................... ..........................17

Figure 5. Static Memory Burst Read Cycle Timing Measurement ................................................................................18

Figure 6. Static Memory Burst Write Cycle Timing Measurement ................................................................................19

Figure 7. SSI1 Interface Timing Measurement .............................................................................................................20

Figure 8. SSI2 Interface Timing Measurement .............................................................................................................21

Figure 9. LCD Controller Timing Measurement ............................................................................................................22

Figure 10. JTAG Timing Measurement ........................ .............................................................. ...................................23

Figure 11. 208-Pin LQFP Package Outline Drawing ....................................................................................................24

Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ..........................................................................25

Figure 13. 256-Ball PBGA Package ..............................................................................................................................29

List of Tables

Table 1. Power Management Pin Assignments ..............................................................................................................6

Table 2. Static Memory Interface Pin Assignments ........................................................................................................6

Table 3. Universal Asynchronous Receiver/Transmitters Pin Assignments ....................... ... .... ... ... ... ... .... ... ... ... .. ..........7

Table 4. DAI Interface Pin Assignments .........................................................................................................................7

Table 5. CODEC Interface Pin Assignments ..................................................................................................................7

Table 6. SSI2 Interface Pin Assignments .......................................................................................................................7

Table 7. Serial Interface Pin Assignments ......................................................................................................................8

Table 8. LCD Interface Pin Assignments ........................................................................................................................8

Table 9. Keypad Interface Pin Assignments ................................ .... ... ... ... .... ... ... ... .........................................................8

Table 10. Interrupt Controller Pin Assignments ..............................................................................................................8

Table 11. Real-Time Clock Pin Assignments ............ ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ...............................9

Table 12. PLL and Clocking Pin Assignments ................................................................................................................9

Table 13. DC-to-DC Converter Interface Pin Assignments .................... ................................ .........................................9

Table 14. General Purpose Input/Output Pin Assignments ............................................................................................9

Table 15. Hardware Debug Interface Pin Assignments ..................................................................................................9

Table 16. LED Flasher Pin Assignments ............... ... ... ... .... ... ... ... .... ... ....................................... ... ... ...............................9

Table 17. DAI/SSI2/CODEC Pin Multiplexing ............................................... ................................................................10

Table 18. Pin Multiplexing ............... ... .... ... ....................................................................................................................10

Table 19. 208-Pin LQFP Numeric Pin Listing ...............................................................................................................26

Table 20. 256-Ball PBGA Ball Listing ...........................................................................................................................30

Table 21. JTAG Boundary Scan Signal Ordering ........................ .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ..........................34

Table 22. Acronyms and Abbreviations .................... ... ... .... ... .......................................... ... ... .... ... ................................39

Table 23. Unit of Measurement .......... .... ... ... ....................................... ... ... .... ... ... ... ... .... ... ... ... .......................................39

Table 24. Pin Description Conventions ............... ... ... ... ... .... ... ... .......................................... ... .......................................40

DS507F2 Copyright Cirrus Logic, Inc. 2011

EP7309

High-Performance, Low-Power System on Chip

Processor Core - ARM720T

The EP7309 incorporates an ARM 32-bit RISC microcontroller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include:

• ARM (32-bit) and Thumb (16-bit compressed) instruction sets

• Enhanced MMU for Microsoft Windows CE and other operating systems

• 8 KB of 4-way set-associative cache.

• Translation Look Aside Buffers with 64 Translated Entries

Power Management

The EP7309 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of

2.5 V–3.3 V allowing the device to achieve a performance

level equivalent to 60 MIPS. The device has three basic power states:

• Operating — This state is the full performance state. All the clocks and peripheral logic are enabled.

• Idle — This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press.

• Standby — This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wake-up the processor.

Pin Mnemonic I/O Pin Description

BATOK I Battery ok input

nEXTPWR I

nPWRFL I Power fail sense input nBATCHG I Battery changed sense input

Table 1. Power Management Pin Assignments

External power supply sense input

MaverickKey™ Unique ID

Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7309 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7309 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances.

Memory Interfaces

The EP7309 is equiped with a ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burst-mode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32-bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industry-leading code density.

Pin Mnemonic I/O Pin Description

nCS[5:0] O Chip select out A[27:0] O Address output D[31:0] I/O Data I/O nMOE O ROM expansion OP enable nMWE O ROM expansion write enable

HALFWORD O

WORD O Word access select output WRITE O Transfer direction

Table 2. Static Memory Interface Pin Assignments

Halfword access select output

Digital Audio Capability

The EP7309 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7309

Universal Asynchronous Receiver/Transmitters (UARTs)

The EP7309 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-by te FIFOs for receiving and transmitting data. The UARTs support bit

6 Copyright Cirrus Logic, Inc. 2011

EP7309

High-Performance, Low-Power System on Chip

rates up to 115.2 kbps. An IrDA SIR protocol encoder/ decoder can be optionally switched into the RX/TX signals to/from UART 1 to enable these signals to drive an infrared communication interface directly.

Pin Mnemonic I/O Pin Description

TXD[1] O UART 1 transmit RXD[1] I UART 1 receive CTS I UART 1 clear to send DCD I UART 1 data carrier detect DSR I UART 1 data set ready TXD[2] O UART 2 transmit RXD[2] I UART 2 receive LEDDRV O Infrared LED drive output PHDIN I Photo diode input

Table 3. Universal Asynchronous Receiver/Transmitters Pin

Assignments

Digital Audio Interface (DAI)

The EP7309 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal Crystal feature digital bass and treble boost, digital volume control and compressor-limiter functions.

SCLK O Serial bit clock SDOUT O Serial data out SDIN I Serial data in LRCK O Sample clock MCLKIN I Master clock input MCLKOUT O Master clock output

‚

CS43L41/42/43 low-power audio DACs and the

‚

CS53L32 low-power ADC. Some of these devices

Pin Mnemonic I/O Pin Description

Table 4. DAI Interface Pin Assignments

communications systems. The CODEC interface is multiplexed to the same pins as the DAI and SSI2.

Pin Mnemonic I/O Pin Description

PCMCLK O Serial bit clock PCMOUT O Serial data out PCMIN I Serial data in PCMSYNC O Frame sync

Table 5. CODEC Interface Pin Assignments

Note: See Table 17 on page 10 for information on pin

multiplexes.

SSI2 Interface

An additional SPI/Microwire1-compatible interface is available for both master and slave mode communications. The SSI2 unit shares the same pins as the DAI and CODEC interfaces through a multiplexer.

• Synchronous clock speeds of up to 512 kHz

• Separate 16 entry TX and RX half-word wide FIFOs

• Half empty/full interrupts for FIFOs

• Separate RX and TX frame sync signals for asymmetric traffic

Pin Mnemonic I/O Pin Description

SSICLK I/O Serial bit clock SSITXDA O Serial data out SSIRXDA I Serial data in SSITXFR I/O Transmit frame sync SSIRXFR I/O Receive frame sync

Table 6. SSI2 Interface Pin Assignments

Note: See Table 17 on page 10 for information on pin

multiplexes.

Note: See Table 17 on page 10 for information on pin

multiplexes.

CODEC Interface

The EP7309 includes an interface to telephony-type CODECs for easy integration into voice-over-IP and other voice

DS507F2 Copyright Cirrus Logic, Inc. 2011

EP7309

High-Performance, Low-Power System on Chip

Synchronous Serial Interface

• ADC (SSI) Interface: Master mode only; SPI and Microwire1-compatible (128 kbps operation)

• Selectable serial clock polarity

Pin Mnemonic I/O Pin Description

ADCLK O SSI1 ADC serial clock ADCIN I SSI1 ADC serial input ADCOUT O SSI1 ADC serial output nADCCS O SSI1 ADC chip select SMPCLK O SSI1 ADC sample clock

Table 7. Serial Interface Pin Assignments

LCD Controller

A DMA address generator is provided that fetches video display data for the LCD controller from memory. The display frame buffer start address is programmable, allowing the LCD frame buffer to be in SDRAM, internal SRAM or external SRAM.

• Interfaces directly to a single-scan panel monochrome STN LCD

• Interfaces to a single-scan panel color STN LCD with minimal external glue logic

• Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments

• Video frame buffer size programmable up to 128 KB

• Bits per pixel of 1, 2, or 4 bits

• Column outputs can be individually set high with the remaining bits left at high-impedance

• Column outputs can be driven all-low, all-high, or all-highimpedance

• Keyboard interrupt driven by OR'ing together all Port A bits

• Keyboard interrupt can be used to wake up the system

•88 keyboard matrix usable with no external logic, extra keys can be added with minimal glue logic

Pin Mnemonic I/O Pin Description

COL[7:0] O

Table 9. Keypad Interface Pin Assignments

Keyboard scanner column drive

Interrupt Controller

When unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled. The EP7309 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources.

• Supports 22 interrupts from a variety of sources (such as UARTs, SSI1, and key matrix.)

• Routes interrupt sources to the ARM720T’s IRQ or FIQ (Fast IRQ) inputs

• Five dedicated off-chip interrupt lines operate as level sensitive interrupts

Pin Mnemonic I/O Pin Description

CL1 O LCD line clock CL2 O LCD pixel clock out DD[3:0] O LCD serial display data bus FRM O LCD frame synchronization pulse M O LCD AC bias drive

Table 8. LCD Interface Pin Assignments

Pin Mnemonic I/O Pin Description

nEINT[2:1] I External interrupt EINT[3] I External interrupt nEXTFIQ I External Fast Interrupt input nMEDCHG/nBROM (Note) I Media change interrupt input

Table 10. Interrupt Controller Pin Assignments

Note: Pins are multiplexed. See Table 18 on page 10 for

more information.

64-Keypad Interface

Matrix keyboards and keypads can be easily read by the EP7309. A dedicated 8-bit column driver output generates strobes for each keyboard column signal. The pins of Port A, when configured as inputs, can be selectively OR'ed together to provide a keyboard interrupt that is capable of waking the system from a STANDBY or IDLE state.

8 Copyright Cirrus Logic, Inc. 2011

Real-Time Clock

The EP7309 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt.

• Driven byan external 32.768 kHz crystal oscillator

EP7309

High-Performance, Low-Power System on Chip

Pin Mnemonic Pin Description

RTCIN Real-Time Clock Oscillator Input RTCOUT Real-Time Clock Oscillator Output VDDRTC Real-Time Clock Oscillator Power VSSRTC Real-Time Clock Oscillator Ground

Table 11. Real-Time Clock Pin Assignments

PLL and Clocking

• Processor and Peripheral Clocks operate from a single

3.6864 MHz crystal or external 13 MHz clock

• Programmable clock speeds allow the peripheral bus to run at 18 MHz when the processor is set to 18 MHz and at 36 MHz when the processor is set to 36, 49 or 74 MHz

Pin Mnemonic Pin Description

MOSCIN Main Oscillator Input MOSCOUT Main Oscillator Output VDDOSC Main Oscillator Power VSSOSC Main Oscillator Ground

Table 12. PLL and Clocking Pin Assignments

DC-to-DC converter interface (PWM)

• Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a positive or negative DC to DC converter

Pin Mnemonic I/O Pin Description

DRIVE[1:0] I/O PWM drive output FB[1:0] I PWM feedback input

Table 13. DC-to-DC Converter Interface Pin Assignments

Timers

• Internal (RTC) timer

• Two internal 16-bit programmable hardware count-down timers

Pin Mnemonic I/O Pin Description

PA[7:0] I/O GPIO port A PB[7:0] I/O GPIO port B PD[0]/LEDFLSH (Note) I/O GPIO port D PD[5:1] I/O GPIO port D PD[7:6]/SDQM[1:0] (Note) I/O GPIO port D PE[1:0]/BOOTSEL[1:0] (Note) I/O GPIO port E PE[2]/CLKSEL (Note) I/O GPIO port E

Table 14. General Purpose Input/Output Pin Assignments

Note: Pins are multiplexed. See Table 18 on page 10 for

more information.

Hardware debug Interface

• Full JTAG boundary scan and Embedded ICE support

Pin Mnemonic I/O Pin Description

TCLK I JTAG clock TDI I JTAG data input TDO O JTAG data output nTRST I JTAG async reset input TMS I JTAG mode select

Table 15. Hardware Debug Interface Pin Assignments

LED Flasher

A dedicated LED flasher module can be used to generate a low frequency signal on Port D pin 0 for the purpose of blinking an LED without CPU intervention. The LED flasher feature is ideal as a visual annunciator in battery powered applications, such as a voice mail indicator on a portable phone or an appointment reminder on a PDA.

• Software adjustable flash period and duty cycle

• Operates from 32 kHz RTC clock

• Will continue to flash in IDLE and STANDBY states

• 4 mA drive current

General Purpose Input/Output (GPIO)

• Three 8-bit and one 3-bit GPIO ports

• Supports scanning keyboard matrix

DS507F2 Copyright Cirrus Logic, Inc. 2011

Pin Mnemonic I/O Pin Description

PD[0]/LEDFLSH (Note) O LED flasher driver

Table 16. LED Flasher Pin Assignments

Note: Pins are multiplexed. See Table 18 on page 10 for

more information.

EP7309

High-Performance, Low-Power System on Chip

Internal Boot ROM

The internal 128 byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH.

Packaging

The EP7309 is available in a 208-pin LQFP package, 256-ball PBGA package or a 204-ball TFBGA package.

Pin Multiplexing

The following table shows the pin multiplexing of the DAI, SSI2 and the CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. The choice between the SSI2, CODEC, and the DAI is controlled by the DAISEL bit in SYSCON3 (see the EP7309 User’s Manual for more information).

Mnemonic

SSICLK I/O SCLK SSICLK PCMCLK SSITXDA O SDOUT SSITXDA PCMOUT SSIRXDA I SDIN SSIRXDA PCMIN

Table 17. DAI/SSI2/CODEC Pin Multiplexing

I/O DAI SSI2 CODEC

Mnemonic

SSITXFR I/O LRCK SSITXFR PCMSYNC SSIRXFR I MCLKIN SSIRXFR p/u BUZ O MCLKOUT

Table 17. DAI/SSI2/CODEC Pin Multiplexing

I/O DAI SSI2 CODEC

The following table shows the pins that have been multiplexed in the EP7309.

Signal Block Signal Block

RUN

nMEDCHG

PD[0] GPIO LEDFLSH LED Flasher

PE[1:0] GPIO BOOTSEL[1:0]

PE[2] GPIO CLKSEL

System Configuration

Interrupt Controller

Table 18. Pin Multiplexing

CLKEN

nBROM

System Configuration

Boot ROM select

System Configuration

10 Copyright Cirrus Logic, Inc. 2011

System Design

LCD

KEYBOARD

BATTER Y

DC-TO-DC

CONVERTERS

ADC

DIGITIZER

IR LED AND

PHOTODIODE

2RS-232

TRANSCEIVERS

ADDITIONAL I/O

PC CARD

CONTROLLER

PC CARD

SOCKET

nCS[4] PB0 EXPCLK

DD[0-3]

CL1 CL2

FRM

D[0-31] A[0-27]

COL[0-7]

PA[0-7]

INPUT

nMOE WRITE

PB[0-7]

PD[0-7]

PE[0-2]

nPOR

nPWRFL

BATOK nEXTPWR nBATCHG

RUN

WAKEUP

nCS[0] nCS[1]

DRIVE[0-1]

FB[0-1]

EP7309

ADCCLK nADCCS

ADCOUT

ADCIN

SMPCLK

LEDDRV

PHDIN

RXD1/2

TXD1/2

DSR

CTS

DCD

CS[n] WORD

nCS[2] nCS[3]

16

FLASH

16

FLASH

6

FLASH

EXTERNAL MEMORY MAPPED EXPANSION

BUFFERS

AND

LATCHES

16

FLASH

POWER

SUPPLY UNIT

AND

COMPARATORS

CRYSTAL

CODEC/SSI2/

DAI

SSICLK

SSITXFR SSITXDA SSIRXDA SSIRXFR

RTCIN

LEDFLSH

CRYSTAL

MOSCIN

EP7309

High-Performance, Low-Power System on Chip

As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7309

completes a low-power system solution. All necessary interface logic is integrated on-chip.

Note: A system can only use one of the following peripheral

Figure 1. A Maximum EP7309 Based System

interfaces at any given time: SSI2,CODEC or DAI.

EP7309

High-Performance, Low-Power System on Chip

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

DC Core, PLL, and RTC Supply Voltage 2.9 V

DC I/O Supply Voltage (Pad Ring) 3.6 V

DC Pad Input Current 10 mA/pin; 100 mA cumulative

Storage Temperature, No Power –40C to +125C

Recommended Operating Conditions

DC core, PLL, and RTC Supply Voltage 2.5 V  0.2 V

DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.5 V

DC Input / Output Voltage O–I/O supply voltage

Operating Temperature

Extended -20C to +70C; Commercial 0C to +70C; Industrial -40C to +85C

DC Characteristics

All characteristics are specified at V

DDCORE

for all frequencies of operation. The current consumption figures have test conditions specified per parameter.”

Symbol Parameter Min Typ Max Unit Conditions

VIH CMOS input high voltage

VIL CMOS input low voltage

VT+

VT-

Vhst Schmitt trigger hysteresis 0.1 - 0.4 V VIL to VIH

VOH

Schmitt trigger positive going threshold

Schmitt trigger negative going threshold

CMOS output high voltage Output drive 1 Output drive 2

a a

= 2.5 V , V

0.65 V

DDIO

 0.3

--2.1V

0.8 - - V

VDD – 0.2

2.5

= 3.3 V and VSS = 0 V over an operating temperature of 0°C to +70°C

DDIO

+ 0.3

DDIO

0.25 V

DDIO

V V V

= 2.5 V

DDIO

= 2.5 V

DDIO

IOH = 0.1 mA IOH = 4 mA IOH = 12 mA

CMOS output low voltage

VOL

IIN Input leakage current - - 1.0 µA

IOZ

CIN Input capacitance 8 - 10.0 pF

COUT Output capacitance 8 - 10.0 pF

Output drive 1 Output drive 2

Bidirectional 3-state leakage current

a a

b c

25 - 100 µA

0.3

0.5

12 Copyright Cirrus Logic, Inc. 2011

V V V

IOL = –0.1 mA IOL = –4 mA IOL = –12 mA

VIN = V

VOUT = V

or GND

High-Performance, Low-Power System on Chip

Symbol Parameter Min Typ Max Unit Conditions

CI/O Transceiver capacitance 8 - 10.0 pF

EP7309

Only nPOR, nPWRFAIL,

IDD

STANDBY

@ 25 C

Standby current consumption Core, Osc, RTC @2.5 V I/O @ 3.3 V

77 41

µA

nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = V

VIL = GND ± 0.1 V

Only nPOR, nPWRFAIL,

IDD

STANDBY

@ 70 C

Standby current consumption Core, Osc, RTC @2.5 V I/O @ 3.3 V

570 111

µA

nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = V

VIL = GND ± 0.1 V

Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = V

IDD

STANDBY

@ 85 C

Standby current consumption Core, Osc, RTC @2.5 V

I/O @ 3.3 V

1693

163

µA

VIL = GND ± 0.1 V

Both oscillators running, CPU static, Cache enabled, LCD disabled, VIH = V

= GND ± 0.1 V

IDD

idle

at 74 MHz

Idle current consumption Core, Osc, RTC @2.5 V I/O @ 3.3 V

Minimum standby voltage for

VDD

Standby supply voltage 2.0 - - V

STANDBY

state retention, internal SRAM cache, and RTC operation only

a. Refer to the strength column in the pin assignment tables for all package types. b. Assumes buffer has no pull-up or pull-down resistors. c. The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.

± 0.1 V,

± 0.1 V, VIL

Note: 1) Total power consumption = IDD

CORE x

2) A typical design will provide 3.3 V to the I/O supply (i.e., V compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).

2) Pull-up current = 50 µA typical at V

= 3.3 V.

2.5 V + IDD

IO x

3.3 V ), and 2.5 V to the remaining logic. This is to allow the I/O to be

DDIO

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