Cirrus Logic EP7309 User Manual

FEATURES

LCD

Controller

Boot
ROM

MaverickKey

TM

ARM720T

ARM7TDMI CPU Core

MMU

8 KB

Cache

Write

Buffer

Internal Data Bus

EPB Bus

SRAM &

FLASH I/F

On-chip SRAM

48 KB

ICE-JTAG

Clocks &

Timers

Keypad&

Touch

Screen I/F

Interrupts,

PWM & GPIO

Bus

Bridge

(2) UARTs

w/ IrDA

Power

Management

Serial

Interface

Digital

Audio

Interface

ARM720T Processor

— ARM7TDMI CPU
— 8 KB of four-way set-associative cache
— MMU with 64-entry TLB
— Thumb code support enabled

Ultra low power

— 90 mW at 74 MHz typical
— 30 mW at 18 MHz typical
— 10 mW in the Idle State
— <1 mW in the Standby State

Advanced audio decoder/decompression capability

— Supports bit streams with adaptive bit rates
— Allows for support of multiple audio decompression

algorithms (MP3, WMA, AAC, ADPCM, Audible,
etc.)

EP7309 Data Sheet

High-performance,

Low-power, System-on-chip

with Enhanced

Digital Audio Interface

OVERVIEW

The Maverick™ EP7309 is designed for ultra-low-power
applications such as digital music players, internet appliances,
smart cellular phones or any hand-held device that features the
added capability of digital audio decompression. The core­logic functionality of the device is built around an ARM720T
processor with 8 KB of four-way set-associative unified cache
and a write buffer. Incorporated into the ARM720T is an
enhanced memory management unit (MMU) which allows for
support of sophisticated operating systems like Microsoft
Windows® CE and Linux®.

®

BLOCK DIAGRAM

http://www.cirrus.com

(cont.)

(cont.)

USER INTERFACE

SERIAL PORTS

MEMORY AND STORAGE

Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) MAR ‘11

DS507F2

EP7309

High-Performance, Low-Power System on Chip

FEATURES (cont)

Dynamically programmable clock speeds of 18, 36, 49, and

74 MHz

48 KB of on-chip SRAM

™

MaverickKey

IDs
— 32-bit unique ID can be used for SDMI compliance
— 128-bit random ID

LCD controller

— Interfaces directly to a single-scan panel monochrome

STN LCD

— Interfaces to a single-scan panel color STN LCD with

minimal external glue logic

Full JTAG boundary scan and Embedded ICE



support

Integrated Peripheral Interfaces

— 8/32/16-bit SRAM/FLASH/ROM Interface
— Digital Audio Interface providing glueless interface to

low-power DACs, ADCs and CODECs

— Two Synchronous Serial Interfaces (SSI1, SSI2)

OVERVIEW (cont.)

— CODEC Sound Interface
—88 Keypad Scanner
— 27 General Purpose Input/Out put pins
— Dedicated LED flasher pin from the RTC

Internal Peripherals

— Two 16550 compatible UARTs
— IrDA Interface
— Two PWM Interfaces
— Real-time Clock
— T wo general purpose 16-bit timers
— Interrupt Controller
— Boot ROM

Package

—208-Pin LQFP
—256-Ball PBGA

The fully static EP7309 is optimized for low power

dissipation and is fabricated on a 0.25 micron CMOS
process

The EP7309 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of

2.5 V–3.3 V. The device has three basic power states:
operating, idle and standby.

MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.

The EP7309 integrates an interface to enable a direct
connection to many low cost, low power, high quality audio
converters. In particular, the DAI can directly interface with
the Crystal‚ CS43L41/42/43 low-power audio DACs and the
Crystal‚ CS53L32 low-power ADC. Some of these devices
feature digital bass and treble boost, digital volume control and
compressor-limiter functions.

Simply by adding desired memory and peripherals to the
highly integrated EP7309 completes a low-power system
solution. All necessary interface logic is integrated on-chip.

2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

EP7309

High-Performance, Low-Power System on Chip

Table of Contents

FEATURES ..................................................................................................................................................................2

OVERVIEW..................................................................................................................................................................2

Processor Core - ARM720T ..................................................................................................................................6

Power Management ..............................................................................................................................................6

MaverickKey™ Unique ID .....................................................................................................................................6

Memory Interfaces .............................. ... .... ... ... ... ... .... ... ....................................... ... ... ... .... .....................................6

Digital Audio Capability ... ...................................... .... ... ... ... .... ... ... ... ......................................................................6

Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................6

Digital Audio Interface (DAI) .. ... .... ... ... ... .......................................... .... ... ... ... ... .... ... ... ... .........................................7

CODEC Interface ..... ... .... ... ... ... .... ... ... ... .... ... ....................................... ... ... ... ... .... ... ... ... .... .....................................7

SSI2 Interface ........................................................................................................................................................7

Synchronous Serial Interface ................................................................................................................................8

LCD Controller .......................................................................................................................................................8

Interrupt Controller ................................................................................................................................................8

Real-Time Clock ....................................................................................................................................................8

PLL and Clocking ..................................................................................................................................................9

DC-to-DC converter interface (PWM) ....................................................................................................................9

Timers ...................................................................................................................................................................9

General Purpose Input/Output (GPIO) ..................................................................................................................9

Hardware debug Interface .....................................................................................................................................9

Internal Boot ROM ........................... ... ... .... ... ....................................... ... ... ... ... .... ... ... ..........................................10

Packaging ..................................... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ... ....... .............................................10

Pin Multiplexing ...................................................................................................................................................10

System Design ....................................................................................................................................................11

ELECTRICAL SPECIFICATIONS .................................................... ................. ................ ................ .12

Absolute Maximum Ratings .................................................................................................................................12

Recommended Operating Conditions .................................................................................................................12

DC Characteristics ....................................... ... ....................................... ... ... ... .... ... ... ... .... ...................................12

Timings ........................................................................................... .............. ............................ ..........14

Timing Diagram Conventions ...................... ....................................... ... .... ... ... ... .... ... ... ... ... .... ... ................14

Timing Conditions ..................... ... .... ... ... ... ... ....................................... ... .... ... ... ... .... ... ... .............................14

Static Memory ......................................................................................................................................................15

Static Memory Single Read Cycle .............................................................................................................16

Static Memory Single Write Cycle ..............................................................................................................17

Static Memory Burst Read Cycle ...............................................................................................................18

Static Memory Burst Write Cycle ...............................................................................................................19

SSI1 Interface ......................................................................................................................................................20

SSI2 Interface ......................................................................................................................................................21

LCD Interface ......................................................................................................................................................22

JTAG Interface ................................ ... ... ....................................... ... .... ... ... ... ... .... ................................................23

Packages ...................................................................................................................... .............. ........24

208-Pin LQFP Package Characteristics ..............................................................................................................24

208-Pin LQFP Package Specifications ......................................................................................................24

208-Pin LQFP Pin Diagram .......................................................................................................................25

208-Pin LQFP Numeric Pin Listing ............................................................................................................26

256-Ball PBGA Package Characteristics ............................................................................................................29

256-Ball PBGA Package Specifications ....................................................................................................29

256-Ball PBGA Pinout (Top View)) ............................................................................................................30

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 3

EP7309

High-Performance, Low-Power System on Chip

256-Ball PBGA Ball Listing ........................................................................................................................ 30

JTAG Boundary Scan Signal Ordering ............ ... ... ... ... .......................................... .... ... ...................................... 34

CONVENTIONS .................................................................................................................................39

Acronyms and Abbreviations .............................................................................................................................. 39

Units of Measurement ......................................................................................................................................... 39

General Conventions .......................................................... ... ... .... ... ... ... .... ... ... ... ... ............................................. 40

Pin Description Conventions ............................................................................................................................... 40

.................................................................................................................................................................. 40

Ordering Information .......................................................................................................................41

Environmental, Manufacturing, & Handling Information .............................................................41

Revision History ..............................................................................................................................42

4 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

EP7309

High-Performance, Low-Power System on Chip

List of Figures

Figure 1. A Maximum EP7309 Based System ....... ... ....................................... ... ... ... .... ................................................11

Figure 2. Legend for Timing Diagrams .........................................................................................................................14

Figure 3. Static Memory Single Read Cycle Timing Measurement ...............................................................................16

Figure 4. Static Memory Single Write Cycle Timing Measurement .................. ................................... ..........................17

Figure 5. Static Memory Burst Read Cycle Timing Measurement ................................................................................18

Figure 6. Static Memory Burst Write Cycle Timing Measurement ................................................................................19

Figure 7. SSI1 Interface Timing Measurement .............................................................................................................20

Figure 8. SSI2 Interface Timing Measurement .............................................................................................................21

Figure 9. LCD Controller Timing Measurement ............................................................................................................22

Figure 10. JTAG Timing Measurement ........................ .............................................................. ...................................23

Figure 11. 208-Pin LQFP Package Outline Drawing ....................................................................................................24

Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ..........................................................................25

Figure 13. 256-Ball PBGA Package ..............................................................................................................................29

List of Tables

Table 1. Power Management Pin Assignments ..............................................................................................................6

Table 2. Static Memory Interface Pin Assignments ........................................................................................................6

Table 3. Universal Asynchronous Receiver/Transmitters Pin Assignments ....................... ... .... ... ... ... ... .... ... ... ... .. ..........7

Table 4. DAI Interface Pin Assignments .........................................................................................................................7

Table 5. CODEC Interface Pin Assignments ..................................................................................................................7

Table 6. SSI2 Interface Pin Assignments .......................................................................................................................7

Table 7. Serial Interface Pin Assignments ......................................................................................................................8

Table 8. LCD Interface Pin Assignments ........................................................................................................................8

Table 9. Keypad Interface Pin Assignments ................................ .... ... ... ... .... ... ... ... .........................................................8

Table 10. Interrupt Controller Pin Assignments ..............................................................................................................8

Table 11. Real-Time Clock Pin Assignments ............ ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ...............................9

Table 12. PLL and Clocking Pin Assignments ................................................................................................................9

Table 13. DC-to-DC Converter Interface Pin Assignments .................... ................................ .........................................9

Table 14. General Purpose Input/Output Pin Assignments ............................................................................................9

Table 15. Hardware Debug Interface Pin Assignments ..................................................................................................9

Table 16. LED Flasher Pin Assignments ............... ... ... ... .... ... ... ... .... ... ....................................... ... ... ...............................9

Table 17. DAI/SSI2/CODEC Pin Multiplexing ............................................... ................................................................10

Table 18. Pin Multiplexing ............... ... .... ... ....................................................................................................................10

Table 19. 208-Pin LQFP Numeric Pin Listing ...............................................................................................................26

Table 20. 256-Ball PBGA Ball Listing ...........................................................................................................................30

Table 21. JTAG Boundary Scan Signal Ordering ........................ .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ..........................34

Table 22. Acronyms and Abbreviations .................... ... ... .... ... .......................................... ... ... .... ... ................................39

Table 23. Unit of Measurement .......... .... ... ... ....................................... ... ... .... ... ... ... ... .... ... ... ... .......................................39

Table 24. Pin Description Conventions ............... ... ... ... ... .... ... ... .......................................... ... .......................................40

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 5

EP7309

High-Performance, Low-Power System on Chip

Processor Core - ARM720T

The EP7309 incorporates an ARM 32-bit RISC
microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key features
include:

• ARM (32-bit) and Thumb (16-bit compressed) instruction
sets

• Enhanced MMU for Microsoft Windows CE and other
operating systems

• 8 KB of 4-way set-associative cache.

• Translation Look Aside Buffers with 64 Translated Entries

Power Management

The EP7309 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of

2.5 V–3.3 V allowing the device to achieve a performance

level equivalent to 60 MIPS. The device has three basic power
states:

• Operating — This state is the full performance state.
All the clocks and peripheral logic are enabled.

• Idle — This state is the same as the Operating State,
except the CPU clock is halted while waiting for an
event such as a key press.

• Standby — This state is equivalent to the computer
being switched off (no display), and the main
oscillator shut down. An event such as a key press
can wake-up the processor.

Pin Mnemonic I/O Pin Description

BATOK I Battery ok input

nEXTPWR I

nPWRFL I Power fail sense input
nBATCHG I Battery changed sense input

Table 1. Power Management Pin Assignments

External power supply sense
input

MaverickKey™ Unique ID

MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.

Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7309 through the use of laser probing
technology. These IDs can then be used to match secure
copyrighted content with the ID of the target device the
EP7309 is powering, and then deliver the copyrighted
information over a secure connection. In addition, secure
transactions can benefit by also matching device IDs to server
IDs. MaverickKey IDs provide a level of hardware security
required for today’s Internet appliances.

Memory Interfaces

The EP7309 is equiped with a ROM/SRAM/FLASH-style
interface that has programmable wait-state timings and
includes burst-mode capability, with six chip selects decoding
six 256 MB sections of addressable space. For maximum
flexibility, each bank can be specified to be 8-, 16-, or 32-bits
wide. This allows the use of 8-bit-wide boot ROM options to
minimize overall system cost. The on-chip boot ROM can be
used in product manufacturing to serially download system
code into system FLASH memory. To further minimize system
memory requirements and cost, the ARM Thumb instruction
set is supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-leading
code density.

Pin Mnemonic I/O Pin Description

nCS[5:0] O Chip select out
A[27:0] O Address output
D[31:0] I/O Data I/O
nMOE O ROM expansion OP enable
nMWE O ROM expansion write enable

HALFWORD O

WORD O Word access select output
WRITE O Transfer direction

Table 2. Static Memory Interface Pin Assignments

Halfword access select
output

Digital Audio Capability

The EP7309 uses its powerful 32-bit RISC processing engine
to implement audio decompression algorithms in software. The
nature of the on-board RISC processor, and the availability of
efficient C-compilers and other software development tools,
ensures that a wide range of audio decompression algorithms
can easily be ported to and run on the EP7309

Universal Asynchronous Receiver/Transmitters (UARTs)

The EP7309 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-by te FIFOs
for receiving and transmitting data. The UARTs support bit

6 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

EP7309

High-Performance, Low-Power System on Chip

rates up to 115.2 kbps. An IrDA SIR protocol encoder/ decoder
can be optionally switched into the RX/TX signals to/from
UART 1 to enable these signals to drive an infrared
communication interface directly.

Pin Mnemonic I/O Pin Description

TXD[1] O UART 1 transmit
RXD[1] I UART 1 receive
CTS I UART 1 clear to send
DCD I UART 1 data carrier detect
DSR I UART 1 data set ready
TXD[2] O UART 2 transmit
RXD[2] I UART 2 receive
LEDDRV O Infrared LED drive output
PHDIN I Photo diode input

Table 3. Universal Asynchronous Receiver/Transmitters Pin

Assignments

Digital Audio Interface (DAI)

The EP7309 integrates an interface to enable a direct
connection to many low cost, low power, high quality audio
converters. In particular, the DAI can directly interface with
the Crystal
Crystal
feature digital bass and treble boost, digital volume control and
compressor-limiter functions.

SCLK O Serial bit clock
SDOUT O Serial data out
SDIN I Serial data in
LRCK O Sample clock
MCLKIN I Master clock input
MCLKOUT O Master clock output

‚

CS43L41/42/43 low-power audio DACs and the

‚

CS53L32 low-power ADC. Some of these devices

Pin Mnemonic I/O Pin Description

Table 4. DAI Interface Pin Assignments

communications systems. The CODEC interface is
multiplexed to the same pins as the DAI and SSI2.

Pin Mnemonic I/O Pin Description

PCMCLK O Serial bit clock
PCMOUT O Serial data out
PCMIN I Serial data in
PCMSYNC O Frame sync

Table 5. CODEC Interface Pin Assignments

Note: See Table 17 on page 10 for information on pin

multiplexes.

SSI2 Interface

An additional SPI/Microwire1-compatible interface is
available for both master and slave mode communications. The
SSI2 unit shares the same pins as the DAI and CODEC
interfaces through a multiplexer.

• Synchronous clock speeds of up to 512 kHz

• Separate 16 entry TX and RX half-word wide FIFOs

• Half empty/full interrupts for FIFOs

• Separate RX and TX frame sync signals for asymmetric
traffic

Pin Mnemonic I/O Pin Description

SSICLK I/O Serial bit clock
SSITXDA O Serial data out
SSIRXDA I Serial data in
SSITXFR I/O Transmit frame sync
SSIRXFR I/O Receive frame sync

Table 6. SSI2 Interface Pin Assignments

Note: See Table 17 on page 10 for information on pin

multiplexes.

Note: See Table 17 on page 10 for information on pin

multiplexes.

CODEC Interface

The EP7309 includes an interface to telephony-type CODECs
for easy integration into voice-over-IP and other voice

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 7

EP7309

High-Performance, Low-Power System on Chip

Synchronous Serial Interface

• ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)

• Selectable serial clock polarity

Pin Mnemonic I/O Pin Description

ADCLK O SSI1 ADC serial clock
ADCIN I SSI1 ADC serial input
ADCOUT O SSI1 ADC serial output
nADCCS O SSI1 ADC chip select
SMPCLK O SSI1 ADC sample clock

Table 7. Serial Interface Pin Assignments

LCD Controller

A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The display
frame buffer start address is programmable, allowing the LCD
frame buffer to be in SDRAM, internal SRAM or external
SRAM.

• Interfaces directly to a single-scan panel monochrome STN
LCD

• Interfaces to a single-scan panel color STN LCD with
minimal external glue logic

• Panel width size is programmable from 32 to 1024 pixels in
16-pixel increments

• Video frame buffer size programmable up to
128 KB

• Bits per pixel of 1, 2, or 4 bits

• Column outputs can be individually set high with the
remaining bits left at high-impedance

• Column outputs can be driven all-low, all-high, or all-high­impedance

• Keyboard interrupt driven by OR'ing together all Port A
bits

• Keyboard interrupt can be used to wake up the system

•88 keyboard matrix usable with no external logic, extra
keys can be added with minimal glue logic

Pin Mnemonic I/O Pin Description

COL[7:0] O

Table 9. Keypad Interface Pin Assignments

Keyboard scanner column
drive

Interrupt Controller

When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the same
time, a fixed priority system determines the order in which
they are handled. The EP7309 interrupt controller has two
interrupt types: interrupt request (IRQ) and fast interrupt
request (FIQ). The interrupt controller has the ability to control
interrupts from 22 different FIQ and IRQ sources.

• Supports 22 interrupts from a variety of sources (such as
UARTs, SSI1, and key matrix.)

• Routes interrupt sources to the ARM720T’s IRQ or FIQ
(Fast IRQ) inputs

• Five dedicated off-chip interrupt lines operate as level
sensitive interrupts

.

Pin Mnemonic I/O Pin Description

CL1 O LCD line clock
CL2 O LCD pixel clock out
DD[3:0] O LCD serial display data bus
FRM O LCD frame synchronization pulse
M O LCD AC bias drive

Table 8. LCD Interface Pin Assignments

Pin Mnemonic I/O Pin Description

nEINT[2:1] I External interrupt
EINT[3] I External interrupt
nEXTFIQ I External Fast Interrupt input
nMEDCHG/nBROM (Note) I Media change interrupt input

Table 10. Interrupt Controller Pin Assignments

Note: Pins are multiplexed. See Table 18 on page 10 for

more information.

64-Keypad Interface

Matrix keyboards and keypads can be easily read by the
EP7309. A dedicated 8-bit column driver output generates
strobes for each keyboard column signal. The pins of Port A,
when configured as inputs, can be selectively OR'ed together
to provide a keyboard interrupt that is capable of waking the
system from a STANDBY or IDLE state.

8 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

Real-Time Clock

The EP7309 contains a 32-bit Real Time Clock (RTC) that can
be written to and read from in the same manner as the timer
counters. It also contains a 32-bit output match register which
can be programmed to generate an interrupt.

• Driven byan external 32.768 kHz crystal oscillator

EP7309

High-Performance, Low-Power System on Chip

Pin Mnemonic Pin Description

RTCIN Real-Time Clock Oscillator Input
RTCOUT Real-Time Clock Oscillator Output
VDDRTC Real-Time Clock Oscillator Power
VSSRTC Real-Time Clock Oscillator Ground

Table 11. Real-Time Clock Pin Assignments

PLL and Clocking

• Processor and Peripheral Clocks operate from a single

3.6864 MHz crystal or external 13 MHz clock

• Programmable clock speeds allow the peripheral bus to run
at 18 MHz when the processor is set to 18 MHz and at
36 MHz when the processor is set to 36, 49 or 74 MHz

Pin Mnemonic Pin Description

MOSCIN Main Oscillator Input
MOSCOUT Main Oscillator Output
VDDOSC Main Oscillator Power
VSSOSC Main Oscillator Ground

Table 12. PLL and Clocking Pin Assignments

DC-to-DC converter interface (PWM)

• Provides two 96 kHz clock outputs with programmable
duty ratio (from 1-in-16 to 15-in-16) that can be used to
drive a positive or negative DC to DC converter

Pin Mnemonic I/O Pin Description

DRIVE[1:0] I/O PWM drive output
FB[1:0] I PWM feedback input

Table 13. DC-to-DC Converter Interface Pin Assignments

Timers

• Internal (RTC) timer

• Two internal 16-bit programmable hardware count-down
timers

Pin Mnemonic I/O Pin Description

PA[7:0] I/O GPIO port A
PB[7:0] I/O GPIO port B
PD[0]/LEDFLSH (Note) I/O GPIO port D
PD[5:1] I/O GPIO port D
PD[7:6]/SDQM[1:0] (Note) I/O GPIO port D
PE[1:0]/BOOTSEL[1:0] (Note) I/O GPIO port E
PE[2]/CLKSEL (Note) I/O GPIO port E

Table 14. General Purpose Input/Output Pin Assignments

Note: Pins are multiplexed. See Table 18 on page 10 for

more information.

Hardware debug Interface

• Full JTAG boundary scan and Embedded ICE support

Pin Mnemonic I/O Pin Description

TCLK I JTAG clock
TDI I JTAG data input
TDO O JTAG data output
nTRST I JTAG async reset input
TMS I JTAG mode select

Table 15. Hardware Debug Interface Pin Assignments

LED Flasher

A dedicated LED flasher module can be used to generate a low
frequency signal on Port D pin 0 for the purpose of blinking an
LED without CPU intervention. The LED flasher feature is
ideal as a visual annunciator in battery powered applications,
such as a voice mail indicator on a portable phone or an
appointment reminder on a PDA.

• Software adjustable flash period and duty cycle

• Operates from 32 kHz RTC clock

• Will continue to flash in IDLE and STANDBY states

• 4 mA drive current

General Purpose Input/Output (GPIO)

• Three 8-bit and one 3-bit GPIO ports

• Supports scanning keyboard matrix

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 9

Pin Mnemonic I/O Pin Description

PD[0]/LEDFLSH (Note) O LED flasher driver

Table 16. LED Flasher Pin Assignments

Note: Pins are multiplexed. See Table 18 on page 10 for

more information.

EP7309

High-Performance, Low-Power System on Chip

Internal Boot ROM

The internal 128 byte Boot ROM facilitates download of saved
code to the on-board SRAM/FLASH.

Packaging

The EP7309 is available in a 208-pin LQFP package, 256-ball
PBGA package or a 204-ball TFBGA package.

Pin Multiplexing

The following table shows the pin multiplexing of the DAI,
SSI2 and the CODEC. The selection between SSI2 and the
CODEC is controlled by the state of the SERSEL bit in
SYSCON2. The choice between the SSI2, CODEC, and the
DAI is controlled by the DAISEL bit in SYSCON3 (see the
EP7309 User’s Manual for more information).

Pin

Mnemonic

SSICLK I/O SCLK SSICLK PCMCLK
SSITXDA O SDOUT SSITXDA PCMOUT
SSIRXDA I SDIN SSIRXDA PCMIN

Table 17. DAI/SSI2/CODEC Pin Multiplexing

I/O DAI SSI2 CODEC

Pin

Mnemonic

SSITXFR I/O LRCK SSITXFR PCMSYNC
SSIRXFR I MCLKIN SSIRXFR p/u
BUZ O MCLKOUT

Table 17. DAI/SSI2/CODEC Pin Multiplexing

I/O DAI SSI2 CODEC

The following table shows the pins that have been multiplexed
in the EP7309.

Signal Block Signal Block

RUN

nMEDCHG

PD[0] GPIO LEDFLSH LED Flasher

PE[1:0] GPIO BOOTSEL[1:0]

PE[2] GPIO CLKSEL

System
Configuration

Interrupt
Controller

Table 18. Pin Multiplexing

CLKEN

nBROM

System
Configuration

Boot ROM
select

System
Configuration

System
Configuration

10 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

System Design

LCD

KEYBOARD

BATTER Y

DC-TO-DC

CONVERTERS

ADC

DIGITIZER

IR LED AND

PHOTODIODE

2RS-232

TRANSCEIVERS

ADDITIONAL I/O

PC CARD

CONTROLLER

PC CARD

SOCKET

nCS[4]
PB0
EXPCLK

DD[0-3]

CL1
CL2

FRM

M

D[0-31]
A[0-27]

COL[0-7]

PA[0-7]

DC

INPUT

nMOE
WRITE

PB[0-7]

PD[0-7]

PE[0-2]

nPOR

nPWRFL

BATOK
nEXTPWR
nBATCHG

RUN

WAKEUP

nCS[0]
nCS[1]

DRIVE[0-1]

FB[0-1]

EP7309

ADCCLK
nADCCS

ADCOUT

ADCIN

SMPCLK

LEDDRV

PHDIN

RXD1/2

TXD1/2

DSR

CTS

DCD

CS[n]
WORD

nCS[2]
nCS[3]

16

FLASH

16

FLASH

6

FLASH

EXTERNAL MEMORY ­MAPPED EXPANSION

BUFFERS

BUFFERS

AND

LATCHES

16

FLASH

POWER

SUPPLY UNIT

AND

COMPARATORS

CRYSTAL

CODEC/SSI2/

DAI

SSICLK

SSITXFR
SSITXDA
SSIRXDA
SSIRXFR

RTCIN

LEDFLSH

CRYSTAL

MOSCIN

EP7309

High-Performance, Low-Power System on Chip

As shown in system block diagram, simply adding desired
memory and peripherals to the highly integrated EP7309

completes a low-power system solution. All necessary
interface logic is integrated on-chip.

Note: A system can only use one of the following peripheral

DS507F2 Copyright Cirrus Logic, Inc. 2011

Figure 1. A Maximum EP7309 Based System

interfaces at any given time: SSI2,CODEC or DAI.

(All Rights Reserved) 11

EP7309

High-Performance, Low-Power System on Chip

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

DC Core, PLL, and RTC Supply Voltage 2.9 V

DC I/O Supply Voltage (Pad Ring) 3.6 V

DC Pad Input Current 10 mA/pin; 100 mA cumulative

Storage Temperature, No Power –40C to +125C

Recommended Operating Conditions

DC core, PLL, and RTC Supply Voltage 2.5 V  0.2 V

DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.5 V

DC Input / Output Voltage O–I/O supply voltage

Operating Temperature

Extended -20C to +70C; Commercial 0C to +70C;
Industrial -40C to +85C

DC Characteristics

All characteristics are specified at V

DDCORE

for all frequencies of operation. The current consumption figures have test conditions specified per parameter.”

Symbol Parameter Min Typ Max Unit Conditions

VIH CMOS input high voltage

VIL CMOS input low voltage

VT+

VT-

Vhst Schmitt trigger hysteresis 0.1 - 0.4 V VIL to VIH

VOH

Schmitt trigger positive going
threshold

Schmitt trigger negative going
threshold

CMOS output high voltage
Output drive 1
Output drive 2

a
a

a

= 2.5 V , V

0.65 V

DDIO

 0.3

V

SS

--2.1V

0.8 - - V

VDD – 0.2

2.5

2.5

= 3.3 V and VSS = 0 V over an operating temperature of 0°C to +70°C

DDIO

+ 0.3

-

-

-

-

-

V

DDIO

0.25 V

-

-

-

DDIO

V

V

V
V
V

V

= 2.5 V

DDIO

= 2.5 V

V

DDIO

IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA

CMOS output low voltage

VOL

IIN Input leakage current - - 1.0 µA

IOZ

CIN Input capacitance 8 - 10.0 pF

COUT Output capacitance 8 - 10.0 pF

Output drive 1
Output drive 2

Bidirectional 3-state leakage
current

a
a

b c

a

-

-

-

25 - 100 µA

-

-

-

0.3

0.5

0.5

12 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

V
V
V

IOL = –0.1 mA
IOL = –4 mA
IOL = –12 mA

VIN = V

VOUT = V

or GND

DD

DD

or GND

High-Performance, Low-Power System on Chip

Symbol Parameter Min Typ Max Unit Conditions

CI/O Transceiver capacitance 8 - 10.0 pF

EP7309

Only nPOR, nPWRFAIL,

IDD

STANDBY

@ 25 C

Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V

1

-

-

77
41

-

µA

-

nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V

VIL = GND ± 0.1 V

Only nPOR, nPWRFAIL,

IDD

STANDBY

@ 70 C

Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V

1

-

-

-

-

570
111

µA

nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V

VIL = GND ± 0.1 V

Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = V

IDD

STANDBY

@ 85 C

Standby current consumption
Core, Osc, RTC @2.5 V

I/O @ 3.3 V

1

-

-

-

-

1693

163

µA

VIL = GND ± 0.1 V

Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = V

= GND ± 0.1 V

IDD

idle

at 74 MHz

Idle current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V

1

-

-

10

6

-

mA

-

Minimum standby voltage for

VDD

Standby supply voltage 2.0 - - V

STANDBY

state retention, internal SRAM
cache, and RTC operation only

a. Refer to the strength column in the pin assignment tables for all package types.
b. Assumes buffer has no pull-up or pull-down resistors.
c. The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.

± 0.1 V,

DD

± 0.1 V,

DD

± 0.1 V,

DD

± 0.1 V, VIL

DD

Note: 1) Total power consumption = IDD

CORE x

2) A typical design will provide 3.3 V to the I/O supply (i.e., V
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).

2) Pull-up current = 50 µA typical at V

= 3.3 V.

DD

2.5 V + IDD

IO x

3.3 V
), and 2.5 V to the remaining logic. This is to allow the I/O to be

DDIO

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 13

EP7309

Clock

High to Low

High/Low to High

Bus Change

Bus Valid

Undefined/Invalid

V a lid B u s to T ris ta te

Bus/Signal O m ission

Figure 2. Legend for Timing Diagrams

High-Performance, Low-Power System on Chip

Timings

Timing Diagram Conventions

This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are
clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at
V

= 3.1 - 3.5 V and VSS = 0 V over an operating temperature of -40C to +85C. Pin loadings is 50 pF. The timing values are

DDIO

referenced to 1/2 V

14 Copyright Cirrus Logic, Inc. 2011

DD

.

(All Rights Reserved) DS507F2

EP7309

High-Performance, Low-Power System on Chip

Static Memory

Figure 3 through Figure 6 define the timings associated with all phases of the Static Memory. The following table contains the

values for the timings of each of the Static Memory modes.

Parameter Symbol Min Typ Max Unit

EXPCLK rising edge to nCS assert delay time

EXPCLK falling edge to nCS deassert hold time

EXPCLK rising edge to A assert delay time

EXPCLK falling edge to A deassert hold time

EXPCLK rising edge to nMWE assert delay time

EXPCLK rising edge to nMWE deassert hold time

EXPCLK falling edge to nMOE assert delay time

EXPCLK falling edge to nMOE deassert hold time

EXPCLK falling edge to HALFWORD deassert delay time

EXPCLK falling edge to WORD assert delay time

EXPCLK rising edge to data valid delay time

EXPCLK falling edge to data invalid delay time

Data setup to EXPCLK falling edge time

EXPCLK falling edge to data hold time

t

CSd

t

CSh

t

Ad

t

Ah

t

MWd

t

MWh

t

MOEd

t

MOEh

t

HWd

t

WDd

t

Dv

t

Dnv

t

Ds

t

Dh

2 8 20 ns

2 7 20 ns

4 9 16 ns

31019ns

3 6 10 ns

3 6 10 ns

3 7 10 ns

2 7 10 ns

2 8 20 ns

2 8 16 ns

81321ns

61530ns

--1ns

--3ns

EXPCLK rising edge to WRITE assert delay time

EXPREADY setup to EXPCLK falling edge time

EXPCLK falling edge to EXPREADY hold time

t

WRd

t

EXs

t

EXh

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 15

51123ns

--0ns

--0ns

EP7309

EXPCLK

nCS

A

nMWE

HALF-

WORD

WORD

D

WRITE

nMOE

t

CSd

t

Ad

t

CSh

t

MOEh

t

Dh

t

Ds

t

HWd

t

WDd

t

WRd

t

MOEd

EXPRDY

t

EXh

t

EXs

Figure 3. Static Memory Single Read Cycle Timing Measurement

High-Performance, Low-Power System on Chip

Static Memory Single Read Cycle

Note: 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

2. Address, Halfword, Word, and Write hold state until next cycle.

16 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

Static Memory Single Write Cycle

EXPCLK

nCS

A

nMWE

HALF-

WORD

WORD

D

WRITE

t

HWd

t

WDd

t

CSd

t

Ad

t

MWd

t

Dv

t

MWh

t

CSh

nMOE

EXPRDY

t

EXh

t

EXs

Figure 4. Static Memory Single Write Cycle Timing Measurement

EP7309

High-Performance, Low-Power System on Chip

Note: 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.

3. Address, Data, Halfword, Word, and Write hold state until next cycle.

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 17

EP7309

EXPCLK

nCS

A

nMOE

HALF

WORD

WORD

D

nMWE

EXPRDY

WRITE

t

CSd

t

Ad

t

Ah

t

Ah

t

Ah

t

CSh

t

MOEh

t

MOEd

t

EXstEXh

tDst

Dh

t

Ds

t

Ds

t

Ds

t

Dh

t

Dh

t

Dh

t

WRd

t

HWd

t

WDd

Figure 5. Static Memory Burst Read Cycle Timing Measurement

High-Performance, Low-Power System on Chip

Static Memory Burst Read Cycle

Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive

cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.

2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.

4. Address, Halfword, Word, and Write hold state until next cycle.

18 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

Static Memory Burst Write Cycle

EXPCLK

nCS

A

nMOE

HALF

WORD

WORD

D

nMWE

EXPRDY

WRITE

t

CSd

t

Ad

t

MWd

t

MWh

t

MWd

t

MWd

t

MWd

t

MWh

t

MWh

t

MWh

t

Ah

t

Ah

t

Ah

t

EXs

t

EXh

t

CSh

t

Dv

t

Dv

t

Dv

t

Dnv

t

Dnv

t

Dnv

t

Dv

t

HWd

t

WDd

Figure 6. Static Memory Burst Write Cycle Timing Measurement

EP7309

High-Performance, Low-Power System on Chip

Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive

cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.

2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is

sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with

valid timing under zero wait state conditions.

4. Address, Data, Halfword, Word, and Write hold state until next cycle.

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 19

EP7309

ADC

CLK

nADC

CSS

ADCIN

ADC

OUT

t

INs

t

INh

t

Cd

t

Od

t

Ovd

Figure 7. SSI1 Interface Timing Measurement

High-Performance, Low-Power System on Chip

SSI1 Interface

Parameter Symbol Min Max Unit

ADCCLK falling edge to nADCCSS deassert delay time

ADCIN data setup to ADCCLK rising edge time

ADCIN data hold from ADCCLK rising edge time

ADCCLK falling edge to data valid delay time

ADCCLK falling edge to data invalid delay time

t

t

t

t

t

Cd

INs

INh

Ovd

Od

910ms

-15ns

-14ns

 713ns

 23ns

20 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

SSI2 Interface

SSI

CLK

SSIRXFR/

SSITXFR

SSI

TXDA

SSI

RXDA

D1D7

D7

D2

D2 D1

D0

D0

t

clk_per

t

clk_high

t

clk_low

t

FRd

t

FR_per

t

RXs

t

TXd

t

FRa

t

RXh

t

clkrf

t

TXv

Figure 8. SSI2 Interface Timing Measurement

EP7309

High-Performance, Low-Power System on Chip

Parameter Symbol Min Max Unit

SSICLK period (slave mode)

SSICLK high time

SSICLK low time

SSICLK rise/fall time

SSICLK rising edge to RX and/or TX frame sync high time

SSICLK rising edge to RX and/or TX frame sync low time

SSIRXFR and/or SSITXFR period

SSIRXDA setup to SSICLK falling edge time

SSIRXDA hold from SSICLK falling edge time

SSICLK rising edge to SSITXDA data valid delay time

SSITXDA valid time

t

clk_per

t

clk_high

t

clk_low

t

clkrf

t

FRd

t

FRa

t

FR_per

t

RXs

t

RXh

t

TXd

t

TXv

185 2050 ns

925 1025 ns

925 1025 ns

318ns

-3ns

-8ns

960 990 ns

37ns

37ns

-2ns

960 990 ns

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 21

EP7309

CL[2]

CL[1]

FRM

M

DD [3 :0 ]

t

CL1d

t

FRMd

t

Md

t

DDd

t

CL2d

Figure 9. LCD Controller Timing Measurement

High-Performance, Low-Power System on Chip

LCD Interface

Parameter Symbol Min Max Unit

CL[2] falling to CL[1] rising delay time

CL[1] falling to CL[2] rising delay time

CL[1] falling to FRM transition time

CL[1] falling to M transition time

CL[2] rising to DD (display data) transition time

t

CL1d

t

CL2d

t

FRMd

t

Md

t

DDd

 10 25 ns

80 3,475 ns

300 10,425 ns

 10 20 ns

 10 20 ns

22 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

JTAG Interface

TDO

TCK

TDI

TMS

t

JPh

t

clk_high

t

clk_low

t

JPzx

t

JPco

t

JPxz

t

clk_per

t

JPs

Figure 10. JTAG Timing Measurement

EP7309

High-Performance, Low-Power System on Chip

Parameter Symbol Min Max Units

TCK clock period

TCK clock high time

TCK clock low time

JTAG port setup time

JTAG port hold time

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

t

clk_per

t

clk_high

t

clk_low

t

JPs

t

JPh

t

JPco

t

JPzx

t

JPxz

2-ns

1-ns

1-ns

-0ns

-3ns

-10ns

-12ns

-19ns

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 23

EP7309

Figure 11. 208-Pin LQFP Package Outline Drawing

Pin 1 Indicator

29.60 (1.165)

30.40 (1.197)

0.17 (0.007)

0.27 (0.011)

27.80 (1.094)

28.20 (1.110)

0.50

(0.0197)

BSC

29.60 (1.165)

30.40 (1.197)

27.80 (1.094)

28.20 (1.110)

1.35 (0.053)

1.45 (0.057)

0 MIN
7 MAX

0.09 (0.004)

0.20 (0.008)

1.40 (0.055)

0.45 (0.018)

0.75 (0.030)

0.05 (0.002)

1.00 (0.039) BSC

Pin 1

Pin 208

1.60 (0.063)

0.15 (0.006)

EP7309

208-Pin LQFP

High-Performance, Low-Power System on Chip

Packages

208-Pin LQFP Package Characteristics

208-Pin LQFP Package Specifications

Note: 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.

2) Drawing above does not reflect exact package pin count.

3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.

4) For pin locations, please see Figure 12. For pin descriptions see the EP7309 User’s Manual.

24 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

208-Pin LQFP Pin Diagram

160

159

158

157

53

54

55

56

57

58

59

60

61

62

63

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

106

107

108

109

110

112

113

114

115

116

117

118

119

120

121

64

65

67

68

69

70

71

72

73

74

75

66

98

99

100

101

102

103

104

122

124

125

126

127

128

129

130

105

131

132

133

134

156

155

154

153

152

151

150

149

148

147

146

145

144

143

140

139

138

137

136

141

142

135

161
162
163
164
165
166
167
168
169
170
171
172
173
174

180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199

201
202
203
204
205
206
207
208

200

175
176
177
178
179

123

111

EP7309

208-Pin LQFP

(Top View)

2345678910111213141516171819202122232425262728293031323334353637383940414243444546474849515052

1

nEXTPWR

BATOK

nPOR

VSSOSC

VDDOSC

MOSCIN

MOSCOUT

nURESET

WAKEUP

A[6]
D[6]
A[5]
D[5]

VDDIO

VSSIO

A[4]
D[4]
A[3]

D[3]

nPWRFL

A[2]
D[2]

A[1]
A[0]

D[0]

VDDCORE

VSSIO
VDDIO

CL[2]
CL[1]

FRM

M
DD[2]
DD[1]

DD[0]

N/C
N/C

N/C

VDDIO

VSSIO

N/C

nMWE

nMOE

nCS[0]
nCS[1]
nCS[2]

nCS[3]

D[7]

A[7]

D[8]

A[8]

D[9]

D[10]

A[10]

VSSIO

VDDIO

A[11]

D[12]

A[12]

D[13]

A[13]

D[14]

DD[3]

D[17]

D[15]

A[17]

nTRST

VSSIO

VDDIO

D[18]

A[18

D[19]

A[19]

D[20]

VSSIO

A[21]

D[22]

D[23]

A[23]

D[24]

VSSIO

VDDIO

A[24]

HALFWORD

A[14]

nBATCHG

A[25]

D[25]

D[27]
A[27]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]

ADCOUT
ADCCLK
DRIVE[0]

VDDIO

PD[2]

VSSIO
VSSCORE

nADCCS
ADCIN

SSIRXDA

SSIRXFR
SSITXDA

SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]

PD[3]

A[22]

PD[4]

VDDIO
PD[5]

PD[6]

DRIVE[1]

PD[7]

D[26]

A[15]

D[16]

A[16]

nCS[4]

VDDCORE

A[26]

D[21]

TMS

A[20]

SMPCLK

D[11]

A[9]

D[1]

VSSCORE

N/C

N/C

VSSIO

VSSIO

VSSIO

VSSIO

EXPCLK

WORD

WRITE

RUN/CLKEN

EXPRDY

PB[7]

PB[6]

PB[5]

PB[4]

PB[3]

PB[2]

PB[1]

VSSIO

TDI

VDDIO

TDO

PE[2]/CLKSEL

nEXTFIQ

PA[6]

PA[5]

PA[4]

PA[3]

PA[2]

PA[1]

PA[0]

LEDDRV

TXD[2]

PHDIN

CTS

RXD[2]

DCD

DSR

RTCOUT

RTCIN

VSSIO

PA[7]

VDDIO

VSSIO

nCS[5]

PB[0]

TXD[1]

RXD[1]

nTEST[1]

nTEST[0]

EINT[3]

nEINT[2]

nEINT[1]

PE[1]BOOTSEL[1]

PE[0]BOOTSEL[0]

N/C

VSSRTC

VDDRTC

Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

nMEDCHG/nBROM

EP7309

High-Performance, Low-Power System on Chip

Note: 1. N/C should not be grounded but left as no connects.

2. Pin differences between the EP7212 and the EP7309 are bolded.

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 25

EP7309

High-Performance, Low-Power System on Chip

208-Pin LQFP Numeric Pin Listing

Table 19. 208-Pin LQFP Numeric Pin Listing

Pin
No.

1nCS[5] O 1 High
2 VDDIO Pad Pwr
3 VSSIO Pad Gnd
4 EXPCLK I/O 1
5 WORD Out 1 Low
6 WRITE Out 1 Low
7 RUN/CLKEN O 1 Low
8 EXPRDY I 1

9 TXD[2] O 1 High
10 RXD[2] I
11 TDI I with p/u*
12 VSSIO Pad Gnd
13 PB[7] I/O 1 Input
14 PB[6] I/O 1 Input
15 PB[5] I/O 1 Input
16 PB[4] I/O 1 Input
17 PB[3] I/O 1 Input
18 PB[2] I/O 1 Input
19 PB[1]/PRDY2 I/O 1 Input
20 PB[0]/PRDY1 I/O 1 Input
21 VDDIO Pad Pwr
22 TDO O 1 Three state
23 PA[7] I/O 1 Input
24 PA[6] I/O 1 Input
25 PA[5] I/O 1 Input
26 PA[4] I/O 1 Input
27 PA[3] I/O 1 Input
28 PA[2] I/O 1 Input
29 PA[1] I/O 1 Input
30 PA[0] I/O 1 Input
31 LEDDRV O 1 Low
32 TXD[1] O 1 High
33 VSSIO Pad Gnd 1 High
34 PHDIN I
35 CTS I
36 RXD[1] I

Signal Type Strength

Reset

State

Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

37 DCD I
38 DSR I
39 nTEST[1] I With p/u*
40 nTEST[0] I With p/u*
41 EINT[3] I
42 nEINT[2] I
43 nEINT[1] I
44 nEXTFIQ I
45 PE[2]/CLKSEL I/O 1 Input

46

47

48 VSSRTC RTC Gnd
49 RTCOUT O
50 RTCIN I
51 VDDRTC RTC power
52 N/C
53 PD[7] I/O 1 Low
54 PD[6] I/O 1 Low
55 PD[5] I/O 1 Low
56 PD[4] I/O 1 Low
57 VDDIO Pad Pwr
58 TMS I with p/u*
59 PD[3] I/O 1 Low
60 PD[2] I/O 1 Low
61 PD[1] I/O 1 Low
62 PD[0]/LEDFLSH I/O 1 Low
63 SSICLK I/O 1 Input
64 VSSIO Pad Gnd
65 SSITXFR I/O 1 Low
66 SSITXDA O 1 Low
67 SSIRXDA I
68 SSIRXFR I/O Input
69 ADCIN I
70 nADCCS O 1 High
71 VSSCORE Core Gnd
72 VDDCORE Core Pwr

Signal Type Strength

PE[1]/

BOOTSEL[1]

PE[0]/

BOOTSEL[0]

I/O 1 Input

I/O 1 Input

Reset

State

26 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

EP7309

High-Performance, Low-Power System on Chip

Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

73 VSSIO Pad Gnd
74 VDDIO Pad Pwr

75 DRIVE[1] I/O 2

76 DRIVE[0] I/O 2

77 ADCCLK O 1 Low
78 ADCOUT O 1 Low
79 SMPCLK O 1 Low
80 FB[1] I
81 VSSIO Pad Gnd
82 FB[0] I
83 COL[7] O 1 High
84 COL[6] O 1 High
85 COL[5] O 1 High
86 COL[4] O 1 High
87 COL[3] O 1 High
88 COL[2] O 1 High
89 VDDIO Pad Pwr
90 TCLK I
91 COL[1] O 1 High
92 COL[0] O 1 High
93 BUZ O 1 Low
94 D[31] I/O 1 Low
95 D[30] I/O 1 Low
96 D[29] I/O 1 Low
97 D[28] I/O 1 Low
98 VSSIO Pad Gnd

99 A[27] O 2 Low
100 D[27] I/O 1 Low
101 A[26] O 2 Low
102 D[26] I/O 1 Low
103 A[25] O 2 Low
104 D[25] I/O 1 Low
105 HALFWORD O 1 Low
106 A[24] O 1 Low
107 VDDIO Pad Pwr —
108 VSSIO Pad Gnd —
109 D[24] I/O 1 Low

Signal Type Strength

Reset

State

High /

Low

High /

Low

Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

110 A[23] O 1 Low
111 D[23] I/O 1 Low
112 A[22] O 1 Low
113 D[22] I/O 1 Low
114 A[21] O 1 Low
115 D[21] I/O 1 Low
116 VSSIO Pad Gnd
117 A[20] O 1 Low
118 D[20] I/O 1 Low

119 A[19] O 1 Low
120 D[19] I/O 1 Low
121 A[18] O 1 Low
122 D[18] I/O 1 Low
123 VDDIO Pad Pwr
124 VSSIO Pad Gnd
125 nTRST I
126 A[17] O 1 Low
127 D[17] I/O 1 Low
128 A[16] O 1 Low
129 D[16] I/O 1 Low
130 A[15] O 1 Low
131 D[15] I/O 1 Low
132 A[14] O 1 Low
133 D[14] I/O 1 Low
134 A[13] O 1 Low
135 D[13] I/O 1 Low
136 A[12] O 1 Low
137 D[12] I/O 1 Low
138 A[11] O 1 Low
139 VDDIO Pad Pwr
140 VSSIO Pad Gnd
141 D[11] I/O 1 Low
142 A[10] O 1 Low
143 D[10] I/O 1 Low
144 A[9] O 1 Low
145 D[9] I/O 1 Low
146 A[8] O 1 Low
147 D[8] I/O 1 Low

Signal Type Strength

Reset

State

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 27

EP7309

High-Performance, Low-Power System on Chip

Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

148 A[7] O 1 Low
149 VSSIO Pad Gnd
150 D[7] I/O 1 Low
151 nBATCHG I
152 nEXTPWR I
153 BATOK I
154 nPOR I Schmitt

155

156 nURESET I Schmitt
157 VDDOSC Osc Pwr
158 MOSCIN Osc
159 MOSCOUT Osc
160 VSSOSC Osc Gnd
161 WAKEUP I Schmitt
162 nPWRFL I
163 A[6] O 1 Low
164 D[6] I/O 1 Low
165 A[5] Out 1 Low
166 D[5] I/O 1 Low
167 VDDIO Pad Pwr
168 VSSIO Pad Gnd
169 A[4] O 1 Low
170 D[4] I/O 1 Low
171 A[3] O 2 Low
172 D[3] I/O 1 Low
173 A[2] O 2 Low
174 VSSIO Pad Gnd
175 D[2] I/O 1 Low
176 A[1] O 2 Low
177 D[1] I/O 1 Low
178 A[0] O 2 Low
179 D[0] I/O 1 Low
180 VSS CORE Core Gnd
181 VDD CORE Core Pwr
182 VSSIO Pad Gnd
183 VDDIO Pad Pwr
184 CL[2] O 1 Low
185 CL[1] O 1 Low

Signal Type Strength

nMEDCHG/

nBROM

I

Reset

State

Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)

Pin
No.

186 FRM O 1 Low
187 M O 1 Low
188 DD[3] I/O 1 Low
189 DD[2] I/O 1 Low
190 VSSIO Pad Gnd
191 DD[1] I/O 1 Low
192 DD[0] I/O 1 Low
193 N/C O 1 High
194 N/C O 1 High
195 N/C I/O 2 Low
196 N/C I/O 2 Low
197 VDDIO Pad Pwr
198 VSSIO Pad Gnd
199 N/C I/O 2 Low
200 N/C I/O 2 Low
201 nMWE O 1 High
202 nMOE O 1 High
203 VSSIO Pad Gnd
204 nCS[0] O 1 High
205 nCS[1] O 1 High
206 nCS[2] O 1 High
207 nCS[3] O 1 High
208 nCS[4] O 1 High

Signal Type Strength

*With p/u’ means with internal pull-up on the pin.

Reset

State

28 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

256-Ball PBGA Package Characteristics

TOP VI EW

17.00 (0.669)

15.00

(0.590)

SIDE VIEW

BOTTOM VIEW

A

B
C
D

E

F
G
H

J

K

L
M
N

P
R

T

1.00 (0.040)

Pin 1 Indicator

Pin 1 Corner

Pin 1 Corner

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

15.00

(0.590)

2 Layer

17.00 (0.669)

17.00 (0.669)

1.00 (0.040)

1.00 (0.040)

1.00 (0.040)

30° TYP

REF

REF

0.50

3 Places

0.85 (0.034)
±0.05 (.002)

0.40 (0.016)
±0.05 (.002)

0.36 (0.014)

17.00 (0.669)

R

D1

E1

D

E

±0.20 (.008)

±0.20 (.008)

±0.20 (.008)

±0.20 (.008)

±0.09 (0.004)

JEDEC #: MO-151
Ball Diameter: 0.50 mm ± 0.10 mm
17 ¥ 17 ¥ 1.61 mm body

256-Ball PBGA Package Specifications

EP7309

High-Performance, Low-Power System on Chip

Note: 1) For pin locations see Table 20.

2) Dimensions are in millimeters (inches), and controlling dimension is millimeter

3) Before beginning any new EP7309 design, contact Cirrus Logic for the latest package information.

Figure 13. 256-Ball PBGA Package

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 29

EP7309

High-Performance, Low-Power System on Chip

256-Ball PBGA Pinout (Top View))

1 2 3 4 5 6 7 8 9 10 11 12 13 141516

A VDDIO nCS[4] nCS[1] N/C N/C DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] MOSCOUT VDDOSC VSSIO A

B nCS[5] VDDIO nCS[3] nMOE VDDIO N/C DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET B

C VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO nPOR nEXTPWR C

D WRITE EXPRDY VSSIO VDDIO nCS[2] nMWE N/C CL[2] VSSRTC D[4] nPWRFL MOSCIN VDDIO VSSIO D[7] D[8] D

E RXD[2] PB[7] TDI WORD VSSIO nCS[0] N/C FRM A[0] D[5] VSSOSC VSSIO

F PB[5] PB[3] VSSIO TXD[2]

G PB[1] VDDIO TDO PB[4] PB[6] VSSRTC VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] G

H PA[7] PA[5] VSSIO PA[4] PA[6] PB[0] PB[2] VSSRTC VSSRTC A[10] A[11] A[12] A[13] VSSIO D[14] D[15] H

J PA[3] PA[1] VSSIO PA[2] PA[0] TXD[1] CTS VSSRTC VSSRTC A[17] A[16] A[15] A[14] nTRST D[16] D[17] J

K LEDDRV PHDIN VSSIO DCD nTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO K

L RXD[1] DSR VDDIO nEINT[1]

M nTEST[0] nEINT[2] VDDIO

N nEXTFIQ

P VSSRTC RTCOUT VSSIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO D[24] VDDIO P

R RTCIN VDDIO PD[4] PD[1] SSITXDA nADCCS VDDIO ADCOUT COL[7] COL[3] COL[1] D[30] A[27] A[25] VDDIO A[24] R

T VDDRTC PD[7] PD[6] PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28] A[26] D[25] VSSIO T

PE[1]/

BOOTSEL[1]

VSSIO VDDIO PD[5] PD[2] SSIRXDA ADCCLK SMPCLK COL[2] D[29] D[26] HALFWORD VSSIO D[22] D[23] N

PE[0]/

BOOTSEL[0]

RUN/

CLKEN

PE[2]/

CLKSEL

VSSIO N/C DD[3] A[1] D[6] VSSRTC BATOK nBATCHG VSSIO D[11] VDDIO F

VSSRTC

TMS VDDIO SSITXFR DRIVE[1] FB[0] COL[0] D[27] VSSIO A[23] VDDIO A[20] D[21] M

PD[0]/

LEDFLSH

VSSRTC COL[6] D[31] VSSRTC A[22] A[21] VSSIO A[18] A[19] L

nMEDCHG/

nBROM

VDDIO D[9] D[10] E

256-Ball PBGA Ball Listing

The list is ordered by ball location.

Table 20. 256-Ball PBGA Ball Listing

Ball Location Name Type Description

A1 VDDIO Pad power Digital I/O power, 3.3V
A2 nCS[4] O Chip select out
A3 nCS[1] O Chip select out
A4 N/C O
A5 N/C O
A6 DD[1] O LCD serial display data
A7 M O LCD AC bias drive
A8 VDDIO Pad power Digital I/O power, 3.3V

A9 D[0] I/O Data I/O
A10 D[2] I/O Data I/O
A11 A[3] O System byte address

Ball Location Name Type Description

30 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

Table 20. 256-Ball PBGA Ball Listing (Continued)

A12 VDDIO Pad power Digital I/O power, 3.3V
A13 A[6] O System byte address
A14 MOSCOUT O Main oscillator out

A15 VDDOSC

A16 VSSIO Pad ground I/O ground

B1 nCS[5] O Chip select out
B2 VDDIO Pad power I/O ground
B3 nCS[3] O Chip select out
B4 nMOE O ROM, expansion OP enable
B5 VDDIO Pad power Di gital I/O power, 3.3V
B6 N/C O

Oscillator

power

Oscillator power in, 2.5V

EP7309

High-Performance, Low-Power System on Chip

Table 20. 256-Ball PBGA Ball Listing (Continued)

Ball Location Name Type Description

B7 DD[2] O LCD serial display data
B8 CL[1] O LCD line clock
B9 VDDCORE Core power Digital core power, 2.5V

B10 D[1] I/O Data I/O

B11 A[2] O System byte address
B12 A[4] O System byte address
B13 A[5] O System byte address
B14 WAKEUP I System wake up input
B15 VDDIO Pad power Digital I/O power, 3.3V
B16 nURESET I User reset input

C1 VDDIO Pad power Digital I/O power, 3.3V
C2 EXPCLK I Expansion clock input
C3 VSSIO Pad ground I/O ground
C4 VDDIO Pad power Digital I/O power, 3.3V
C5 VSSIO Pad ground I/O ground
C6 VSSIO Pad ground I/O ground
C7 VSSIO Pad ground I/O ground
C8 VDDIO Pad power Digital I/O power, 3.3V

C9 VSSIO Pad ground I/O ground
C10 VSSIO Pad ground I/O ground
C11 VSSIO Pad ground I/O ground
C12 VDDIO Pad power Digital I/O power, 3.3V
C13 VSSIO Pad ground I/O ground
C14 VSSIO Pad ground I/O ground
C15 nPOR I Power-on reset input
C16 nEXTPWR I External power supply sense input

D1 WRITE O Transfer direction

D2 EXPRDY I Expansion port ready input

D3 VSSIO Pad ground I/O ground

D4 VDDIO Pad power Digital I/O power, 3.3V

D5 nCS[2] O Chip select out

D6 nMWE O ROM, expansion write enable

D7 N/C O

D8 CL[2] O LCD pixel clock out

D9 VSSRTC Core ground Real time clock ground
D10 D[4] I/O Data I/O
D11 nPWRFL I Power fail sense input
D12 MOSCIN I Main oscillator input
D13 VDDIO Pad power Digital I/O power, 3.3V
D14 VSSIO Pad ground I/O ground
D15 D[7] I/O Data I/O
D16 D[8] I/O Data I/O

E1 RXD[2] I UART 2 receive data input

E2 PB[7] I GPIO port B

E3 TDI I JTAG data input

E4 WORD O Word access select output

E5 VSSIO Pad ground I/O ground

E6 nCS[0] O Chip select out

Table 20. 256-Ball PBGA Ball Listing (Continued)

Ball Location Name Type Description

E7 N/C O
E8 FRM O LCD frame synchronization pulse
E9 A[0] O System byte address

E10 D[5] I/O Data I/O

E11 VSSOSC

E12 VSSIO Pad ground I/O ground

E13 nMEDCHG/nBROM I

E14 VDDIO Pad power Digital I/O power, 3.3V
E15 D[9] I/O Data I/O
E16 D[10] I/O Data I/O

F1 PB[5] I GPIO port B
F2 PB[3] I GPIO port B
F3 VSSIO Pad ground I/O ground
F4 TXD[2] O UART 2 transmit data output
F5 RUN/CLKEN O Run output / clock enable output
F6 VSSIO Pad ground I/O ground
F7 N/C O
F8 DD[3] O LCD serial display data
F9 A[1] O System byte address

F10 D[6] I/O Data I/O

F11 VSSRTC RTC ground Real time clock ground
F12 BATOK I Battery ok input
F13 nBATCHG I Battery changed sense input
F14 VSSIO Pad ground I/O ground
F15 D[11] I/O Data I/O
F16 VDDIO Pad power Digital I/O power, 3.3V

G1 PB[1]/PRDY[2] I

G2 VDDIO Pad power Digital I/O power, 3.3V
G3 TDO O JTAG data out
G4 PB[4] I GPIO port B
G5 PB[6] I GPIO port B
G6 VSSRTC Core ground Real time clock ground
G7 VSSRTC RTC ground Real time clock ground
G8 DD[0] O LCD serial display data

G9 D[3] I/O Data I/O
G10 VSSRTC RTC ground Real time clock ground
G11 A[7] O System byte address
G12 A[8] O System byte address
G13 A[9] O System byte address
G14 VSSIO Pad ground I/O ground
G15 D[12] I/O Data I/O
G16 D[13] I/O Data I/O

H1 PA[7] I GPIO port A

H2 PA[5] I GPIO port A

H3 VSSIO Pad ground I/O ground

H4 PA[4] I GPIO port A

H5 PA[6] I GPIO port A

Oscillator

ground

PLL ground

Media change interrupt input / internal
rom boot enable

GPIO port B / CL-PS6700 interface
signal

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 31

EP7309

High-Performance, Low-Power System on Chip

Table 20. 256-Ball PBGA Ball Listing (Continued)

Ball Location Name Type Description

H6 PB[0]/PRDY[1] I

H7 PB[2] I GPIO port B
H8 VSSRTC RTC ground Real time clock ground

H9 VSSRTC RTC ground Real time clock ground
H10 A[1 0] O System byte address
H11 A[11] O System byte address
H12 A[1 2] O System byte address
H13 A[13] O System byte address
H14 VSSIO Pad ground I/O ground
H15 D[14] I/O Data I/O
H16 D[15] I/O Data I/O

J1 PA[3] I GPIO port A
J2 PA[1] I GPIO port A
J3 VSSIO Pad ground I/O ground
J4 PA[2] I GPIO port A
J5 PA[0] I GPIO port A
J6 TXD[1] O UART 1 transmit data out
J7 CTS I UART 1 clear to send input
J8 VSSRTC RTC ground Real time clock ground

J9 VSSRTC RTC ground Real time clock ground
J10 A[17] O System byte address
J11 A[16] O System byte address
J12 A[15] O System byte address
J13 A[14] O System byte address
J14 nTRST I JTAG async reset input
J15 D[16] I/O Data I/O
J16 D[17] I/O Data I/O

K1 LEDDRV O IR LED drivet
K2 PHDIN I Photodiode input
K3 VSSIO Pad ground I/O ground
K4 DCD I UART 1 data carrier detect
K5 nTEST[1] I Test mode select input
K6 EINT[3] I External interrupt
K7 VSSRTC RTC ground Real time clock ground
K8 ADCIN I SSI1 ADC serial input

K9 COL[4] O Keyboard scanner column drive
K10 TCLK I JTAG clock
K11 D[20] I/O Data I/O
K12 D[19] I/O Data I/O
K13 D[18] I/O Data I/O
K14 VSSIO Pad ground I/O ground
K15 VDDIO Pad power Digital I/O power, 3.3V
K16 VDDIO Pad power Digital I/O power, 3.3V

L1 RXD[1] I UART 1 receive data input
L2 DSR I UART 1 data set ready input
L3 VDDIO Pad power Digital I/O power, 3.3V
L4 nEINT[1] I External interrupt input
L5 PE[2]/CLKSEL I GPIO port E / clock input mode select

GPIO port B / CL-PS6700 interface
signal

Table 20. 256-Ball PBGA Ball Listing (Continued)

Ball Location Name Type Description

L6 VSSRTC RTC ground Real time clock ground
L7 PD[0]/LEDFLSH I/O GPIO port D / LED blinker output
L8 VSSRTC Core ground Real time clock ground

L9 COL[6] O Keyboard scanner column drive
L10 D[31] I/O Data I/O
L11 VSSRTC RTC ground Real time clock ground
L12 A[22] O System byte address
L13 A[21] O System byte address
L14 VSSIO Pad ground I/O ground
L15 A[18] O System byte address
L16 A[19] O System byte address
M1 nTEST[0] I Test mode select input
M2 nEINT[2] I External interrupt input
M3 VDDIO Pad power Digital I/O power, 3.3V
M4 PE[0]/BOOTSEL[0] I GPIO port E / Boot mode select
M5 TMS I JTAG mode select
M6 VDDIO Pad power Digital I/O power, 3.3V
M7 SSITXFR I/O DAI/CODEC/SSI2 frame sync
M8 DRIVE[1] I/O PWM drive output
M9 FB[0] I PWM feedback input

M10 COL[0] O Keyboard scanner column drive
M11 D[27] I/O Data I/O
M12 VSSIO Pad ground I/O ground
M13 A[23] O System byte address
M14 VDDIO Pad power Digital I/O power, 3.3V
M15 A[20] O System byte address
M16 D[21] I/O Data I/O

N1 nEXTFIQ I External fast interrupt input

N2 PE[1]/BOOTSEL[1] I GPIO port E / boot mode select

N3 VSSIO Pad ground I/O ground

N4 VDDIO P ad power Digital I/O power, 3.3V

N5 PD[5] I/O GPIO port D

N6 PD[2] I/O GPIO port D

N7 SSIRXDA I/O DAI/CODEC/SSI2 serial data input

N8 ADCCLK O SSI1 ADC serial clock

N9 SMPCLK O SSI1 ADC sample clock

N10 COL[2] O Keyboard scanner column drive
N11 D[29] I/O Data I/O
N12 D[26] I/O Data I/O
N13 HALFWORD O Halfword access select output
N14 VSSIO Pad ground I/O ground
N15 D[22] I/O Data I/O
N16 D[23] I/O Data I/O

P1 VSSRTC RTC ground Real time clock ground

P2 RTCOUT O Real time clock oscillator output

P3 VSSIO Pad ground I/O ground

P4 VSSIO Pad ground I/O ground

P5 VDDIO Pad power Digital I/O power, 3.3V

32 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

Table 20. 256-Ball PBGA Ball Listing (Continued)

Ball Location Name Type Description

P6 VSSIO Pad ground I/O ground
P7 VSSIO Pad ground I/O ground
P8 VDDIO Pad power Digital I/O power, 3.3V
P9 VSSIO Pad ground I/O ground

P10 VDDIO Pad power Digital I/O power, 3.3V

P11 VSSIO Pad ground I/O ground
P12 VSSIO Pad ground I/O ground
P13 VDDIO Pad power Digital I/O power
P14 VSSIO Pad ground I/O ground
P15 D[24] I/O Data I/O
P16 VDDIO Pad power Digital I/O power, 3.3V

R1 RTCIN I/O Real time clock oscillator input
R2 VDDIO Pad power Digital I/O power, 3.3V
R3 PD[4] I/O GPIO port D
R4 PD[1] I/O GPIO port D
R5 SSITXDA O DAI/CODEC/SSI2 serial data output
R6 nADCCS O SSI1 ADC chip select
R7 VDDIO Pad power Digital I/O power, 3.3V
R8 ADC OUT O S SI1 ADC serial data output

R9 COL[7] O Keyboard scanner column drive
R10 COL[3] O Keyboard scanner column drive
R11 COL[1] O Keyboard scanner column drive
R12 D[30] I/O Data I/O
R13 A[27] O System byte address
R14 A[25] O System byte address
R15 VDDIO Pad power Digital I/O power, 3.3V
R16 A[24] O System byte address

T1 VDDRTC RTC power Real time clock power, 2.5V
T2 PD[7] I/O GPIO port D
T3 PD[6] I/O GPIO port D
T4 PD[3] I/O GPIO port D
T5 SSICLK I/O DAI/CODEC/SSI2 serial clock
T6 SSIRXFR – DAI/CODEC/SSI2 frame sync
T7 VDDCORE Core power Core power, 2.5V
T8 DRIVE[0] I/O PWM drive output

T9 FB[1] I PWM feedback input
T10 COL[5] O Keyboard scanner column drive
T11 VDDIO Pad power Digital I/O power, 3.3V
T12 BUZ O Buzzer drive output
T13 D[28] I/O Data I/O
T14 A[26] O S ystem byte address
T15 D[25] I/O Data I/O
T16 VSSIO Pad ground I/O ground

EP7309

High-Performance, Low-Power System on Chip

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 33

EP7309

High-Performance, Low-Power System on Chip

JTAG Boundary Scan Signal Ordering

Table 21. JTAG Boundary Scan Signal Ordering

LQFP

Pin No.

1B1 nCS[5] O 1
4 C2 EXPCLK I/O 3
5E4 WORD O 6
6D1 WRITE O 8
7 F5 RUN/CLKEN O 10
8 D2 EXPRDY I 13

9F4 TXD2 O14
10 E1 RXD2 I 16
13 E2 PB[7] I/O 17
14 G5 PB[6] I/O 20
15 F1 PB[5] I/O 23
16 G4 PB[4] I/O 26
17 F2 PB[3] I/O 29
18 H7 PB[2] I/O 32
19 G1 PB[1]/PRDY2 I/O 35
20 H6 PB[0]/PRDY1 I/O 38
23 H1 PA[7] I/O 41
24 H5 PA[6] I/O 44
25 H2 PA[5] I/O 47
26 H4 PA[4] I/O 50
27 J1 PA[3] I/O 53
28 J4 PA[2] I/O 56
29 J2 PA[1] I/O 59
30 J5 PA[0] I/O 62
31 K1 LEDDRV O 65
32 J6 TXD1 O 67
34 K2 PHDIN I 69
35 J7 CTS I 70
36 L1 RXD1 I 71
37 K4 DCD I 72
38 L2 DSR I 73
39 K5 nTEST1 I 74
40 M1 nTEST0 I 75
41 K6 EINT3 I 76
42 M2 nEINT2 I 77
43 L4 nEINT1 I 78

PBGA

Ball

Signal Type Position

34 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

High-Performance, Low-Power System on Chip

Table 21. JTAG Boundary Scan Signal Ordering (Continued)

EP7309

LQFP

Pin No.

44 N1 nEXTFIQ I 79
45 L5 PE[2]/CLKSEL I/O 80
46 N2 PE[1]/BOOTSEL1 I/O 83
47 M4 PE[0]/BOOTSEL0 I/O 86
53 T2 PD[7] I/O 89
54 T3 PD[6] I/O 92
55 N5 PD[5] I/O 95
56 R3 PD[4] I/O 98
59 T4 PD[3] I/O 101
60 N6 PD[2] I/O 104
61 R4 PD[1] I/O 107
62 L7 PD[0]/LEDFLSH O 110
68 T6 SSIRXFR I/O 122
69 K8 ADCIN I 125
70 R6 nADCCS O 126
75 M8 DRIVE1 I/O 128
76 T8 DRIVE0 I/O 131
77 N8 ADCCLK O 134
78 R8 ADCOUT O 136
79 N9 SMPCLK O 138
80 T9 FB1 I 140
82 M9 FB0 I 141
83 R9 COL7 O 142
84 L9 COL6 O 144
85 T10 COL5 O 146
86 K9 COL4 O 148
87 R10 COL3 O 150
88 N10 COL2 O 152
91 R11 COL1 O 154
92 M10 COL0 O 156
93 T12 BUZ O 158
94 L10 D[31] I/O 160
95 R12 D[30] I/O 163
96 N11 D[29] I/O 166
97 T13 D[28] I/O 169

99 R13 A[27] Out 172
100 M11 D[27] I/O 174
101 T14 A[26] O 177

PBGA

Ball

Signal Type Position

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 35

EP7309

High-Performance, Low-Power System on Chip

Table 21. JTAG Boundary Scan Signal Ordering (Continued)

LQFP

Pin No.

102 N12 D[26] I/O 179
103 R14 A[25] O 182
104 T15 D[25] I/O 184
105 N13 HALFWORD O 187
106 R16 A[24] O 189
109 P15 D[24] I/O 191
110 M13 A[23] O 194
111 N16 D[23] I/O 196
112 L12 A[22] O 199
113 N15 D[22] I/O 201
114 L13 A[21] O 204
115 M16 D[21] I/O 206
117 M15 A[20] O 209
118 K11 D[20] I/O 211
119 L16 A[19] O 214
120 K12 D[19] I/O 216
121 L15 A[18] O 219
122 K13 D[18] I/O 221
126 J10 A[17] O 224
127 J16 D[17] I/O 226
128 J11 A[16] O 229
129 J15 D[16] I/O 231
130 J12 A[15] O 234
131 H16 D[15] I/O 236
132 J13 A[14] O 239
133 H15 D[14] I/O 241
134 H13 A[13] O 244
135 G16 D[13] I/O 246
136 H12 A[12] O 249
137 G15 D[12] I/O 251
138 H11 A[11] O 254
141 F15 D[11] I/O 256
142 H10 A[10] O 259
143 E16 D[10] I/O 261
144 G13 A[9] O 264
145 E15 D[9] I/O 266
146 G12 A[8] O 269
147 D16 D[8] I/O 271

PBGA

Ball

Signal Type Position

36 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

High-Performance, Low-Power System on Chip

Table 21. JTAG Boundary Scan Signal Ordering (Continued)

EP7309

LQFP

Pin No.

148 G11 A[7] O 274
150 D15 D[7] I/O 276
151 F13 nBATCHG I 279
152 C16 nEXTPWR I 280
153 F12 BATOK I 281
154 C15 nPOR I 282
155 E13 nMEDCHG/nBROM I 283
156 B16 nURESET I 284
161 B14 WAKEUP I 285
162 D11 nPWRFL I 286
163 A13 A[6] O 287
164 F10 D[6] I/O 289
165 B13 A[5] O 292
166 E10 D[5] I/O 294
169 B12 A[4] O 297
170 D10 D[4] I/O 299
171 A11 A[3] O 302
172 G9 D[3] I/O 304
173 B11 A[2] O 307
175 A10 D[2] I/O 309
176 F9 A[1] O 312
177 B10 D[1] I/O 314
178 E9 A[0] O 317
179 A9 D[0] I/O 319
184 D8 CL2 O 322
185 B8 CL1 O 324
186 E8 FRM O 326
187 A7 M O 328
188 F8 DD[3] I/O 330
189 B7 DD[2] I/O 333
191 A6 DD[1] I/O 336
192 G8 DD[0] I/O 339
193 B6 N/C O 342
194 D7 N/C O 344
195 A5 N/C I/O 346
196 E7 N/C I/O 349
199 F7 N/C I/O 352
200 A4 N/C I/O 355

PBGA

Ball

Signal Type Position

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 37

EP7309

High-Performance, Low-Power System on Chip

Table 21. JTAG Boundary Scan Signal Ordering (Continued)

LQFP

Pin No.

201 D6 nMWE O 358
202 B4 nMOE O 360
204 E6 nCS[0] O 362
205 A3 nCS[1] O 364
206 D5 nCS[2] O 366
207 B3 nCS[3] O 368
208 A2 nCS[4] O 370

1) See EP7309 Users’ Manual for pin naming / functionality.

2) For each pad, the JTAG connection ordering is input,
output, then enable as applicable.

PBGA

Ball

Signal Type Position

38 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

EP7309

High-Performance, Low-Power System on Chip

CONVENTIONS

This section presents acronyms, abbreviations, units of
measurement, and conventions used in this data sheet.

Acronyms and Abbreviations

Table 22 lists abbreviations and acronyms used in this data
sheet.

Table 22. Acronyms and Abbreviations

Acronym/

Abbreviation

A/D analog-to-digital
ADC analog-to-digital converter
CODEC coder / decoder
D/A digital-to-analog
DMA direct-memory access
EPB embedded peripheral bus
FCS frame check sequence
FIFO first in / first out
FIQ fast interrupt request
GPIO general purpose I/O
ICT in circuit test
IR infrared
IRQ standard interrupt request
IrDA Infrared Data Association
JTAG Joint Test Action Group
LCD liquid crystal display
LED light-emitting diode
LQFP low profile quad flat pack
LSB least significant bit
MIPS millions of instructions per second
MMU memory management unit
MSB most significant bit
PBGA plastic ball grid array
PCB printed circuit board
PDA personal digital assistant
PLL phase locked loop
p/u pull-up resistor
RISC reduced instruction set computer
RTC Real-Time Clock
SIR slow (9600–115.2 kbps) infrared
SRAM static random access memory
SSI synchronous serial interface

Definition

Table 22. Acronyms and Abbreviations (Continued)

Acronym/

Abbreviation

TAP test access port
TLB translation lookaside buffer
UART universal asynchronous receiver

Definition

Units of Measurement

Table 23. Unit of Measurement

Symbol Unit of Measure

C

fs sample frequency
Hz hertz (cycle per second)
kbps kilobits per second
KB kilobyte (1,024 bytes)
kHz kilohertz
k kilohm
Mbps megabits (1,048,576 bits) per second
MB megabyte (1,048,576 bytes)
MBps megabytes per second
MHz megahertz (1,000 kilohertz)

A microampere
Fmicrofarad
Wmicrowatt
s microsecond (1,000 nanoseconds)

mA milliampere
mW milliwatt
ms millisecond (1,000 microseconds)
ns nanosecond
Vvolt
Wwatt

degree Celsius

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 39

EP7309

High-Performance, Low-Power System on Chip

General Conventions

Hexadecimal numbers are presented with all letters in
uppercase and a lowercase “h” appended or with a 0x at the
beginning. For example, 0x14 and 03CAh are hexadecimal
numbers. Binary numbers are enclosed in single quotation
marks when in text (for example, ‘11’ designates a binary
number). Numbers not indicated by an “h”, 0x or quotation
marks are decimal.

Registers are referred to by acronym, with bits listed in
brackets separated by a colon (:) (for example, CODR[7:0]),
and are described in the EP7309 User’s Manual. The use of
“TBD” indicates values that are “to be determined,” “n/a”
designates “not available,” and “n/c” indicates a pin that is a
“no connect.”

Pin Description Conventions

Abbreviations used for signal directions are listed in Table 24.

Table 24. Pin Description Conventions

Abbreviation Direction

I Input
O Output
I/O Input or Output

40 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2

High-Performance, Low-Power System on Chip

Ordering Information

Model T emperature Package

EP7309-CBZ 0 to +70 °C
EP7309-IBZ -40 to +85 °C
EP7309-CVZ 0 to +70 °C
EP7309-IVZ -40 to +85 °C

Environmental, Manufacturing, & Handling Information

Model Number Peak Reflow Temp MSL Rating* Max Floor Life

EP7309-CBZ
EP7309-IBZ

260 °C 3 7 Days

EP7309-CVZ
EP7309-IVZ

EP7309

256-pin PBGA, 17mm X 17mm

208-pin LQFP.

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
All devices are now lead (Pb) free.

DS507F2 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) 41

EP7309

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE
Cirrus Logic, Inc. and it s su bsi d iari e s (“Ci r ru s”) be li eve t hat the inf or mati o n con tai n ed in th i s docu ment i s acc urate and reliable. Ho we ver , t h e inf o rmat io n i s su bj e ct

to change without noti ce and is provi ded “AS I S” with out warran ty of any kind ( express or implied ). Cust omers are a dvised to obtain the latest version of relevant
information to verify, before placing orders, tha t inform atio n bei ng relied on is curr ent and com plete. Al l prod ucts are sold s ubject to the ter ms and co nditio ns of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other righ ts of thir d
parties. This document is the property of Ci rrus and by furnishing this information, Cirrus gr an ts no li cense, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con­sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for ge neral distribution, advertising or promotional purpose s, or for crea ting any work for resale.

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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.

SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
LINUX is a registered trademark of Linus Torvalds.
Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation.

High-Performance, Low-Power System on Chip

Revision History

Revision Date Changes

PP1 NOV 2003 First preliminary release.

F1 AUG 2005 Updated ordering information. Added MSL data.
F2 MAR 2011 Removed lead-containing device ordering information. Removed 204-pin BGA

option.

42 Copyright Cirrus Logic, Inc. 2011

(All Rights Reserved) DS507F2