Cirrus Logic EDB9315A User Manual
Enhanced Universal Platform
System-on-Chip Processor
EDB9315A
EP9315
Engineering Development Board
Technical Reference Manual
http://www.cirrus.com
©Copyright 2006 Cirrus Logic, Inc. AUG ’06
DS638DB3
EDB9315A
Technical Reference Manual
CORPORATE HEADQUARTERS
Cirrus Logic, Inc.
2901 Via Fortuna
Austin, Texas 78746
United States
Phone: (512) 851-4000
Phone: (800) 888-5016
INTERNATIONAL OFFICES
ASIA PACIFIC
Cirrus Logic Intl. Ltd.
20F, Ocean Building
80 Shanghai Street
Kowloon, Hong Kong
China
Phone: (852) 2376-0801
Phone: (852) 2314-9920
Fax: (852) 2375-1202
JAPAN
Cirrus Logic K.K.
Aioi Sonpo, Building 6F
5-6 Niban-cho
Chiyoda-ku
Tokyo, 102-0084
Japan
Phone: +81 (3) 5226-7390
Fax: +81 (3) 5226-7677
EUROPE
Cirrus Logic (UK) Ltd.
Park House, Mere Park, Dedmere Road
Marlow, Bucks, SL7 1FJ, England
Phone ++49 89 818 974 65
Switchboard +44 1628 891300
Fax +44 1628 891988
2 ©Copyright 2006 Cirrus Logic, Inc. DS638DB3
EDB9315A
Technical Reference Manual
Table of Contents
CORPORATE HEADQUARTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
INTERNATIONAL OFFICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
ASIA PACIFIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
JAPAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
EUROPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1. EDB9315A Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Introducing the EDB9315A Engineering Development Board . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Identifying What's on the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1 Before you Begin... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Attaching Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Before Applying Power... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. EDB9315A Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1 Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Circuit Description, Schematic Page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Circuit Description, Schematic Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Circuit Description, Schematic Page 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Circuit Description, Schematic Page 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Circuit Description, Schematic Page 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Circuit Description, Schematic Page 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Circuit Description, Schematic Page 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Circuit Description, Schematic Page 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Circuit Description, Schematic Page 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Circuit Description, Schematic Page 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Circuit Description, Schematic Page 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Circuit Description, Schematic Page 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Circuit Description, Schematic Page 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Circuit Description, Schematic Page 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Download Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Developer’s User Forum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Other Useful Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Web Sites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Processor Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Code Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Appendix A. Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Appendix B. Programming Linux Images into Flash from a Windows® PC . . . . . . . . . . .33
Materials and Equipment Needed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Downloading Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Windows PC Ethernet Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TFTP Server Setup (Setup may vary depending on TFTP server used) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
HyperTerminal Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Board Programming Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Programming Software into the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
DS638DB3 ©Copyright 2006 Cirrus Logic, Inc. 3
EDB9315A
Technical Reference Manual
Figure 1. EDB9315A Board.......................................................................................................................5
Figure 2. EDB9315A Top View .................................................................................................................7
Figure 3. Block Diagram..........................................................................................................................10
Figure 4. Schematic Page 1 - Block Diagram .........................................................................................19
Figure 5. Schematic Page 2 - Processor & Memory ...............................................................................20
Figure 6. Schematic Page 3 - Peripherals ..............................................................................................21
Figure 7. Schematic Page 4 - UARTs & USB .........................................................................................22
Figure 8. Schematic Page 5 - mP Power................................................................................................23
Figure 9. Schematic Page 6 - SDRAM & Flash ......................................................................................24
Figure 10. Schematic Page 7 - JTAG & CFG .........................................................................................25
Figure 11. Schematic Page 8 - Ethernet.................................................................................................26
Figure 12. Schematic Page 9 - Expansion Connector ............................................................................27
Figure 13. Schematic Page 10 - IDE.......................................................................................................28
Figure 14. Schematic Page 11 - VGA & LCD .........................................................................................29
Figure 15. Schematic Page 12 - USB2.0 Slave ......................................................................................30
Figure 16. Schematic Page 13 - Audio ...................................................................................................31
Figure 17. Schematic Page 14 - Power Supply ......................................................................................32
List of Figures
4 ©Copyright 2006 Cirrus Logic, Inc. DS638DB3
1. EDB9315A Kit Contents
Each EDB9315A kit comes with the following:
• EDB9315A Development Board
• Null Modem Serial Cable
• Power Supply: +12V, 5A, 110V/220V with AC Power Cord
• Quick Start Guide
• Registration Card
• (2) IDC10-to-DB9 Cables
• IDE Ribbon Cable
• HDD Power Cable
• 3.5"-to-2.5" Notebook HDD Adapter
• 4x1 Header to HDD Power Connector Adapter
•IAR™ Evaluation CD
EDB9315A
Technical Reference Manual
• Quick Start Guide
• Board Registration Card
• Trial Software Download Information Card
All documentation, schematics, software, utilities, and related information is available from the download
section of the Cirrus Logic ARM Developer's web site, http://arm.cirrus.com
.
Figure 1. EDB9315A Board
DS638DB3 ©Copyright 2006 Cirrus Logic, Inc. 5
EDB9315A
Technical Reference Manual
2. Introducing the EDB9315A Engineering Development Board
This document will describe the features and basic operation of the EDB9315A board developed by
Cirrus Logic. Detailed information regarding the operation and programming of the EP9315 device are
covered by the EP9315 datasheet and User's Guide on the Cirrus Logic web site.
The EDB9315A is a convenient and easy-to-operate evaluation platform. It has been designed to provide
the majority of the EP9315 functions on a small 6" x 4" base board. These features include:
• EP9315 Processor Running at 200MHz
• 64MByte SDRAM
• 16MByte NOR Flash Memory
• Two USB 2.0 Full-speed Host Ports
• USB 2.0 High-speed Device Interface
• Audio Out
• Audio In
• Three UARTs
• 10/100 Ethernet Interface
•VGA
•IDE
•JTAG
• Consumer IR (CIR)
• Expansion Connectors
• LCD Interface with Touch Screen Support
Note: The EDB9315A kit does not include a LCD screen. The LCD interface is pin-compatible with
previous Cirrus Logic development boards.
Not all features of the EP9315 are on the base board. Two high-density connectors have been provided
to allow for daughter card expansion. The full memory bus is connected to one of the connectors and
any peripherals not on the development board are attached to the other connector. In addition, some
features such as Ethernet MII interface have been brought out to the peripheral connector as well.
2.1 Identifying What's on the Board
Figure 2 shows the top side of the EDB9315A. The accompanying legend identifies the main
components of the board.
6 ©Copyright 2006 Cirrus Logic, Inc. DS638DB3
EDB9315A
Technical Reference Manual
L
M N
K
AA
J
I
H
Z
E
D
C
FG
Y
O P
A
B
W
X
Q R
S
T
U
V
Figure 2. EDB9315A Top View
A. EP9315 processor
B. Processor Status LEDs - one Red and one
Green
C. USB 2.0 High-speed Device IC (ISP1581)
D. SDRAM - 2 16-bit devices
E. Memory Bus Expansion Connector
F. Main Power Switch, S1
G. 12V Power Connector
H. 3.3V Voltage Regulator - switching, 3A
I. Serial Boot Pushbutton - labeled "SERIAL
BOOT"
J. Reset Pushbutton - labeled "/POR"
K. UART2 Header - 5x2
L. UART1 Header - 5x2
N. USB Device Connector
O. Ethernet Connector
P. Dual, Stacked USB Host Connector
Q. Audio Out Connector
R. Audio In Connector
S. Peripheral Bus Expansion Connector
T. Touch Screen Connector
U. JTAG Connector
V. VGA Connector - DB15, female
W. LCD Connector
X. IDE Connector
Y. Commercial IR
Z. IDE Power Connector, +12V, +5V, GND
AA. RTC and Battery Backup
M. UART0, DB9 Male
One item not listed above is the Flash device. It is located on the bottom side of the board, under item C.
There are no jumpers on the board. The only "jumper" is the serial boot pushbutton. This button is used
when the developer wants to use the Cirrus Logic download utility to put new code into Flash memory.
DS638DB3 ©Copyright 2006 Cirrus Logic, Inc. 7
EDB9315A
Technical Reference Manual
3. Getting Started
3.1 Before you Begin...
The developer will find it useful to have some additional hardware not provided in the EDB9315A kit.
Items such as a USB mouse, USB keyboard, VGA monitor and cable, and a set of powered speakers
can make using the EDB9315A and the software installed on the board more enjoyable.
Caution: Make sure you are in a static-free environment and are following proper
procedures for handling ESD-sensitive electronic equipment.
3.2 Attaching Cables
Before attaching cables to the board make sure you know where pin 1 for each of the connectors is
located. Most connectors are keyed. However, some connectors use 2 x n headers, allowing the cable to
be plugged in backwards. Prime examples of this are the Touch Screen and JTAG connectors.
There is silkscreen on the PCB identifying each connector and its pin 1 location. Make sure to pay
attention to the markings on the PCB for the pin 1 location. The pin 1 identifier is marked by either a
number or a triangle.
3.3 Before Applying Power...
In order to use the EDB9315A the user must first connect the peripherals to the EDB9315A as described
in the following procedure.
1. Place the EDB9315A on a static free surface.
2. Make sure power switch S1 is in the OFF position.
3. Connect the 12V power supply provided to the board at J10.
4. Connect null modem serial cable provided in the kit from DB9 connector J2 to a serial port on a PC
or notebook (if so equipped).
5. Connect a VGA monitor to DB15 connector J6.
6. Launch a terminal program, such as minicom or HyperTerminal. Configure the PC com port for:
38400 baud, 8 data bits, no parity, 1 stop bit, no flow control for WinCE and 57600 baud for Linux.
7. Connect the board to a network that has internet access (optional)
8. Connect a USB mouse and keyboard.
9. Turn power switch S1 to the ON position and the board will boot and shortly display the WinCE 5.0 or
8 ©Copyright 2006 Cirrus Logic, Inc. DS638DB3
EDB9315A
Technical Reference Manual
the Qt/Opie desktop on the VGA monitor, depending which OS you have programmed into the board.
The EDB9315A comes with WinCE 5.0 installed.
NOTE: The WinCE 5.0 binary is not provided on the support web site. If you erase the image on the
board, you will have to download the BSP provided by Cirrus Logic and compile it using Platform
Builder.
Due to changes in distribution policy, the Microsoft trial CD/DVD that was formerly included in
the kit is no longer available. Please refer to the card in the kit that describes how to download
the Microsoft trial software from the Microsoft web site.
DS638DB3 ©Copyright 2006 Cirrus Logic, Inc. 9
EDB9315A
Technical Reference Manual
4. EDB9315A Circuit Description
This chapter makes reference to the schematics in Appendix A and discusses the main circuit
functionality of each schematic page. A detailed block diagram of the EDB9315A Engineering
Development Board is shown below.
JTAG
20 pin
Memory
Expansion
120 pin
Vout=1.8 , 3.3 , 5.0
POWER
Vin = +12V
Reset and
voltage
monitoring
SDRAM
64 MByte
32-bit
USB 2. 0
Device
( High Speed)
RTC
battery backed
CIR
UART2
UART3
10 pin
Ethernent
RJ45
Serial
EEPROM
Peripheral
Expansion
120 pin
Flash
16 MByte
16-bit
Audio In
Audio Out
IDE
40 pin
VGA
DB15
EP9315
LCD
40 pin
Touchscreen
10 pin
Dual USB 2. 0
Host
( Full Speed)
UART1
DB 9 w/ control
Figure 3. Block Diagram
Detailed information regarding the EP9315 processor and interfaces can be found at www.cirrus.com.
The details of this device will not be discussed in this document. Refer to the EP9315 datasheet, User's
Guide, and other information on the web site for more information.
10 ©Copyright 2006 Cirrus Logic, Inc. DS638DB3
EDB9315A
Technical Reference Manual
4.1 Circuit Operation
The major circuit operation for each page of the schematic will be discussed.
Note: Refer to http://arm.cirrus.com for the latest board schematics. Look under the download link at the top of the
page.
Page 1
Block diagram and revision history.
Page 2
There are two main clock inputs to the EP9315 device. One is the 14.7456 MHz crystal oscillator and the
other is the 32.768 kHz real time clock (RTC).
The 14.7456 MHz clock can be generated from a crystal circuit as shown in the schematics, or optionally
from a 14.7456 MHz oscillator. If a 14.7456 MHz oscillator is used, then only the XTALI pin is driven and
the drive level of the clock must be 3.3 V.
The RTC clock may be generated by the circuit shown in the schematics, or optionally an RTC oscillator.
Due to the cost of RTC oscillators, the circuit shown in the schematics is used. An external oscillator is
made by using an unbuffered '04 inverter. It is very important to use an unbuffered inverter in this
application. Using a buffered inverter may make the circuit oscillate in the ~MHz range or not start at all.
Refer to application note AN265.
The two LEDs connected to the EP9315 device are used to indicate processor health during boot and
general status of the board.
The reset output, RSTON (active-low signal) is buffered by U25. There is a resistor option for the RSTON
signal to be either driven by this buffer or bypassed. If the reset signal is not going to be buffered, U25
must be removed and R117 installed. By default, RSTON is buffered.
Page 3
This block shows the peripheral connections from the EP9315 processor.
Page 4
Main items on this page are the USB 2.0 Full-speed Host, USB power, UART, and Commercial IR (CIR)
circuits.
The USB Host circuits are connected directly from the EP9315 to U3 and U4 and then on to the stacked
USB connector, J1. U3 and U4 provide termination for the USB signals and ESD protection. Note that
only two of the three USB ports are routed to USB connectors, the remaining USB port is routed to the
Peripheral Expansion header. Power for the USB Host ports comes from the +5V switching regulator and
is protected with poly fuses rated for 0.5 A each.
The board has all three UARTs brought out. The main UART interface, UART0, is connected to a
standard male DB9 connector and provides for full modem control. The other two UART interfaces are
connected to 5x2 headers. There is an option for installing zero-ohm resistors if the developer needs to
provide +5V power to an external device. The pinout of the headers matches common IDC10-to-DB9
cables. Two such cables are included with the kit. All UART signals are level shifted from TTL to RS-232.
The CIR uses an enhanced GPIO (EGPIO) line to communicate to the EP9315 device.
DS638DB3 ©Copyright 2006 Cirrus Logic, Inc. 11
EDB9315A
Technical Reference Manual
Page 5
This is the power section for the EP9315 device. The ADC and PLL supplies are filtered. There is no
reason to filter the 3.3 and the 1.8V power rails.
Page 6
The SDRAM interface is comprised of two 16-bit SDRAM devices to form a 32-bit SDRAM bus. The
SDRAM is connected to /SDCS0 and is located at physical memory address 0xC000_0000. Single 32bit SDRAM devices may be used as well.
The Flash interface is made from a single 16-bit device. It uses a "multi-cell" Flash device. The Flash
device is connected to /CS6 and is located at physical memory address 0x6000_0000. The reference
design uses only one Flash device. However, the EP9315 can be designed with a 32-bit Flash interface
as well. The Flash device installed is a 128 Mbit, 16 Mbyte, device.
The serial EEPROM is a 4 Mbit device and may be used for serial "SPI Boot" or for storing the Ethernet
MAC address. SPI Boot is not used as the default boot method but may be used by the developer if it fits
his/her application. Details about SPI Boot are in the EP9315 User's Guide. The serial EEPROM is
accessed only if the EGPIO7 line is configured to the proper level. The SPI™ frame signal and the
EGPIO7 "enable" signal are OR'ed to create the enable for the serial EEPROM device. EGPIO7 must be
low in order to communicate to the serial EEPROM. Other devices on the SPI bus must be enabled in a
similar manner but not enabled simultaneously.
Note: EGPIO7 should be pulled low instead of pulled high. If SPI Boot is desired, remove R201 and pull down
EGPIO7.
Page 7
The JTAG interface is connected to a 2x10 header, JP3. This connector is wired for the Multi-ICE
debugger.
There are 10 signals that determine how the EP9315 will boot and operate. They are all shown on this
page except for BOOT1. BOOT1 is connected to GND. BOOT1 is used for factory testing only. The other
nine signals are either pulled up or down external to the EP9315 device. The boot configuration shown
sets the EP9315 device to perform an Internal Async boot from a 16-bit-wide memory.
The “Serial Boot” pushbutton, S2, is used to configure the board to perform a serial boot. A serial boot is
used to program the Flash device with the Cirrus Logic download utility. Instead of using jumpers, a
pushbutton is used. Simply hold the pushbutton down while pressing and releasing the reset pushbutton,
S3. Continue to hold S2 until the red LED turns off. Once the red LED is off, release S2.
The ISL1208 is connected to the EP9315 to provided an external, battery backed RTC clock. This device
has 2 bytes of battery backed SRAM. The battery is a common lithium coin cell and easily removable if
desired.
Page 8
The Micrel KS8721Bl PHY is used to provide the 10/100 Mbit Ethernet interface. The PHY is attached to
the EP9315 device MII interface. The PHY also connects to RJ45 connector, J3. The Ethernet connector
has integrated magnetics and status LEDs. The Micrel PHY requires external power filtering of the 2.5V
supply it produces.
12 ©Copyright 2006 Cirrus Logic, Inc. DS638DB3
EDB9315A
Technical Reference Manual
Page 9
The two connectors provide a daughter card interface for making custom circuits. J4 is the Memory
Expansion connector and J5 is the Peripheral Expansion connector.
The entire memory bus is connected to J5. It is recommended that the bus signals be buffered if adding
additional memory. However if a CPLD or FPGA is attached there is no reason to buffer. Use proper
engineering practices when using the high-speed memory bus with daughter cards.
The Peripheral Expansion bus has the signals for features not implemented on the EDB9315A board and
for commonly used signals.
Page 10
The IDE interface is connected from the EP9315 device to the IDE connector, JP5, through series
termination resistors. These pins are 5V tolerant.
A hard disk drive (HDD) and/or CD-ROM can be connected to the board with the IDE cable provided.
Simply plug the blue end of the IDE cable into the blue IDE connector, JP5. Power for the drive(s) is
provided by plugging the IDE power cable (included) into the IDE power connector, JP4.
If using a notebook HDD, please use the included 3.5”-to-2.5” IDE power adapter.
Page 11
Two video interfaces are provided. The main video interface is VGA. An LCD interface is also provided
however there is no LCD screen included with the development kit. The LCD interface is pin compatible
with previous Cirrus Logic ARM9 development boards. A 4-wire touch screen interface is also included
and is pin compatible with previous Cirrus Logic ARM9 development boards.
Page 12
An external USB 2.0 High-speed Peripheral device is provided. The USB device allows a Host to see the
board as a Mass Storage device. The USB interface chip is connected to the lower 16-bits of the
memory bus.
Page 13
Audio is supported by a Cirrus Logic CS4271 device. Two-channel audio out and line-level audio in is
supported. The audio device communicates to the EP9315 through the I
are generated by the EP9315. The audio in is line level, it is not a microphone-level input. Like the serial
EEPROM, the CS4271 is controlled by the SPI frame signal and EGPIO6. EGPIO6 must be low in order
to communicate to the CS4271 device. As mentioned before, only one SPI™ device can be enabled at a
time.
2
S interface and audio clocks
DS638DB3 ©Copyright 2006 Cirrus Logic, Inc. 13
EDB9315A
Technical Reference Manual
Page 14
Power and reset circuits are shown on this page. Most of the changes made to this revision of the
EDB9315A board were made in this section. The most important change made is that the board is now
powered from a +12V power supply instead of the former +5V supply.
The board has two connectors for input power. J10 is the standard power connector and is where the
power supply provided in the kit attaches. However, a 3x1 header, J11 is also available to supply power
to the board.
The 3.3V power rail is generated from a 3A, adjustable, switching regulator, U27. The 5V power rail is
generated from an identical 3A switching regulator, U28. The 5V supply requires a diode, D7. The 3.3V
supply does not require this diode.
The 1.8V power rail is generated from an 800mA linear regulator. Both the 3.3V and 1.8V power rails are
are monitored by U22 and it will issue a reset if either supply falls below the threshold voltage.
The reset pushbutton can connect directly to the voltage monitor reset input or to a supplementary resetdetect circuit. Refer to AN258 for more information. This circuit is implemented by U24 and some passive
devices. In general, this circuit is not required with EP9315 Rev E2 devices and may be removed if
desired. It is installed by default. If removed, R109 needs to be installed if the use of the reset pushbutton
is desired.
14 ©Copyright 2006 Cirrus Logic, Inc. DS638DB3
Loading...