Cirrus Logic CS8427 User Manual
CS8427
Serial
Audio
Input
Clock &
Data
Recovery
Misc.
Control
AES3
S/PDIF
Encoder
Serial
Audio
Output
Receiver
AES3
S/PDIF
Decoder
C&Ubit
Data
Buffer
Control
Port &
Registers
Output
Clock
Generator
RXN
RXP
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUT
TXP
TXN
RST OMCKEMPH U TCBL SDA/
CDOUT
SCL/
CCLK
AD1/
CDIN
AD0/CSINT
VA+ AGND FILT RERR
VL+ DGND
H/S
RMCK
Driver
96 kHz Digital Audio Interface Transceiver
Features
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-compatible Transceiver
+5.0 V Analog Supply (VA+)
+3.3 V or +5.0 V Digital Interface (VL+)
Flexible 3-wire Serial Digital I/O Ports
Adjustable Sample Rate up to 96 kHz
Low-jitter Clock Recovery
Pin and Microcontroller Read/Write Access to
Channel Status and User Data
Microcontroller and Standalone Modes
Differential Cable Driver and Receiver
On-chip Channel Status and User Data Buffer
Memories Permit Block Reads & Writes
OMCK System Clock Mode
Decodes Audio CD Q Sub-code
General Description
The CS8427 is a stereo digital audio transceiver with
AES3 and serial digital audio inputs, AES3 and serial
digital audio outputs, and includes comprehensive control ability through a 4-wire microcontroller port. Channel
status and user data are assembled in block-sized buffers, making read/modify/write cycles easy.
A low-jitter clock recovery mechanism yields a very clean
recovered clock from the incoming AES3 stream.
Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and automotive audio systems.
The CS8427 is available in 28-pin SOIC and TSSOP
packages in Commercial (-10°C to +70°C) and Automotive (-40°C to +85°C) grades. The CDB8427 Customer
Demonstration Board is also available for device evaluation and implementation suggestions. Please see
“Ordering Information” on page 49 for complete details.
I
www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY ‘10
DS477F5
1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 5
SPECIFIED OPERATING CONDITIONS ................................................................................. 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5
DC ELECTRICAL CHARACTERISTICS................................................................................... 6
DIGITAL INPUT CHARACTERISTICS ..................................................................................... 6
DIGITAL INTERFACE SPECIFICATIONS................................................................................ 6
TRANSMITTER CHARACTERISTICS ..................................................................................... 6
SWITCHING CHARACTERISTICS .......................................................................................... 7
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS................................................. 8
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE...................................... 9
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE ..................................... 10
2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 11
3. GENERAL DESCRIPTION ..................................................................................................... 12
3.1 Audio Input/Output Ports ................................................................................................. 12
3.2 Serial Control Port ............................................................................................................ 12
3.3 Channel Status and User bit Memory .............................................................................. 12
3.4 AES3 and S/PDIF Standards Documents ........................................................................ 13
4. DATA I/O FLOW AND CLOCKING OPTIONS ....................................................................... 13
5. THREE-WIRE SERIAL AUDIO PORTS ................................................................................. 15
6. AES3 RECEIVER .................................................................................................................... 16
6.1 OMCK System Clock Mode ............................................................................................. 16
6.2 PLL, Jitter Attenuation, and Varispeed ............................................................................ 16
6.3 Error Reporting and Hold Function .................................................................................. 16
6.4 Channel Status Data Handling ......................................................................................... 16
6.5 User Data Handling .......................................................................................................... 17
6.6 Non-Audio Auto Detection ............................................................................................... 17
7. AES3 TRANSMITTER ........................................................................................................... 18
7.1 Transmitted Frame and Channel Status Boundary Timing .............................................. 18
7.2 TXN and TXP Drivers ...................................................................................................... 18
8. MONO MODE OPERATION ................................................................................................... 19
8.1 Receiver Mono Mode ....................................................................................................... 19
8.2 Transmitter Mono Mode ................................................................................................... 19
9. CONTROL PORT DESCRIPTION AND TIMING .................................................................... 25
9.1 SPITM Mode .................................................................................................................... 25
9.2 I²C Mode .......................................................................................................................... 25
9.3 Interrupts .......................................................................................................................... 25
10. CONTROL PORT REGISTER SUMMARY ........................................................................... 27
10.1 Memory Address Pointer (MAP) ..................................................................................... 27
11. CONTROL PORT REGISTER BIT DEFINITIONS ................................................................ 28
11.1 Control 1 (01h) ................................................................................................................ 28
11.2 Control 2 (02h) ................................................................................................................ 28
11.3 Data Flow Control (03h).................................................................................................. 29
11.4 Clock Source Control (04h)............................................................................................. 30
11.5 Serial Audio Input Port Data Format (05h)...................................................................... 31
11.6 Serial Audio Output Port Data Format (06h)................................................................... 31
11.7 Interrupt 1 Status (07h) (Read Only)............................................................................... 32
11.8 Interrupt 2 Status (08h) (Read Only)............................................................................... 33
11.9 Interrupt 1 Mask (09h).....................................................................................................33
11.10 Interrupt 1 Mode MSB (0Ah) & Interrupt 1 Mode LSB (0Bh)......................................... 33
11.11 Interrupt 2 Mask (0Ch).................................................................................................. 34
11.12 Interrupt 2 Mode MSB (0Dh) & Interrupt 2 Mode LSB (0Eh) ........................................ 34
11.13 Receiver Channel Status (0Fh) (Read Only) ................................................................ 34
CS8427
2 DS477F5
CS8427
11.14 Receiver Error (10h) (Read Only)................................................................................. 35
11.15 Receiver Error Mask (11h) ........................................................................................... 36
11.16 Channel Status Data Buffer Control (12h).................................................................... 36
11.17 User Data Buffer Control (13h) ..................................................................................... 37
11.18 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only) ......................................... 37
11.19 OMCK/RMCK Ratio (1Eh) (Read Only)........................................................................ 38
11.20 C-bit or U-bit Data Buffer (20h - 37h) ........................................................................... 38
11.21 CS8427 I.D. and Version Register (7Fh) (Read Only) ................................................. 38
12. PIN DESCRIPTION - SOFTWARE MODE ........................................................................... 39
13. HARDWARE MODE DESCRIPTION ................................................................................... 42
13.1 Serial Audio Port Formats ............................................................................................. 42
14. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 44
15. APPLICATIONS ................................................................................................................... 46
15.1 Reset, Power Down and Start-up .................................................................................. 46
15.2 ID Code and Revision Code .......................................................................................... 46
15.3 Power Supply, Grounding, and PCB layout ................................................................... 46
15.4 Synchronization of Multiple CS8427s ............................................................................ 46
16. PACKAGE DIMENSIONS .................................................................................................... 47
17. ORDERING INFORMATION ............................................................................................... 49
18. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPO-
NENTS .................................................................................................................................. 50
18.1 AES3 Transmitter External Components ....................................................................... 50
18.2 Isolating Transformer Requirements ............................................................................. 50
18.3 AES3 Receiver External Components ........................................................................... 51
18.4 Isolating Transformer Requirements ............................................................................. 51
19. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 52
19.1 AES3 Channel Status(C) Bit Management .................................................................... 52
19.1.1 Manually accessing the E buffer ....................................................................... 52
19.1.2 Reserving the first 5 bytes in the E buffer ......................................................... 53
19.1.3 Serial Copy Management System (SCMS) ....................................................... 53
19.1.4 Channel Status Data E Buffer Access .............................................................. 53
19.2 AES3 User (U) Bit Management .................................................................................... 54
19.2.1 Mode 1: Transmit All Zeros ............................................................................... 54
19.2.2 Mode 2: Block Mode ......................................................................................... 54
20. APPENDIX C: PLL FILTER .................................................................................................. 55
20.1 General .......................................................................................................................... 55
20.2 External Filter Components ........................................................................................... 56
20.2.1 General ............................................................................................................. 56
20.2.2 Capacitor Selection ........................................................................................... 56
20.2.3 Circuit Board Layout ......................................................................................... 56
20.3 Component Value Selection .......................................................................................... 57
20.3.1 Identifying the Part Revision ............................................................................. 57
20.3.2 Locking to the RXP/RXN Receiver Inputs ......................................................... 57
20.3.3 Locking to the ILRCK Input ............................................................................... 58
20.3.4 Jitter Tolerance ................................................................................................. 58
20.3.5 Jitter Attenuation ............................................................................................... 59
21. REVISION HISTORY ............................................................................................................ 60
DS477F5 3
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing....................................................................................... 8
Figure 2. Audio Port Slave Mode and Data Input Timing ................................................................ 8
Figure 3. SPI Mode timing............................................................................................................... 9
Figure 4. I²C Mode timing.............................................................................................................. 10
Figure 5. Recommended Connection Diagram for Software Mode............................................... 11
Figure 6. CS8427 Internal Block Diagram..................................................................................... 13
Figure 7. Software Mode Audio Data Flow Switching Options ...................................................... 19
Figure 8. CS8427 Clock Routing................................................................................................... 20
Figure 9. AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out ............................. 21
Figure 11. Input Serial Port to AES3 Transmitter without PLL ...................................................... 21
Figure 10. AES3 Input to Serial Audio Output Only ...................................................................... 21
Figure 12. Input Serial Port to AES3 Transmitter with PLL ........................................................... 21
Figure 13. AES3 Receiver Timing for U pin output data ............................................................... 22
Figure 14. AES3 Transmitter Timing for C, U and V pin input data............................................... 22
Figure 15. Serial Audio Input Example Formats............................................................................ 23
Figure 16. Serial Audio Output Example Formats......................................................................... 24
Figure 17. Control Port Timing in SPI Mode.................................................................................. 26
Figure 18. Control Port Timing in I²C Mode................................................................................... 26
Figure 19. Hardware Mode............................................................................................................ 42
Figure 20. Professional Output Circuit ..........................................................................................50
Figure 21. Consumer Output Circuit..............................................................................................50
Figure 22. TTL/CMOS Output Circuit ............................................................................................ 50
Figure 23. Professional Input Circuit ............................................................................................. 51
Figure 24. Transformerless Professional Input Circuit .................................................................. 51
Figure 25. Consumer Input Circuit ................................................................................................ 51
Figure 26. TTL/CMOS Input Circuit...............................................................................................51
Figure 27. Channel Status Data Buffer Structure .......................................................................... 52
Figure 28. Flowchart for Reading the E Buffer .............................................................................. 53
Figure 29. Flowchart for Writing the E Buffer ................................................................................ 53
Figure 30. PLL Block Diagram ...................................................................................................... 55
Figure 31. Recommended Layout Example .................................................................................. 56
Figure 32. Jitter Tolerance Template ............................................................................................58
Figure 33. Revision A .................................................................................................................... 59
Figure 34. Revision A1 .................................................................................................................. 59
Figure 35. Revision A2 using A1 values........................................................................................ 59
Figure 36. Revision A2 using A2* values ...................................................................................... 59
CS8427
LIST OF TABLES
Table 1. Control Register Map Summary ...................................................................................... 27
Table 2. Hardware Mode Start-up Options.................................................................................... 43
Table 3. Serial Audio Output Formats Available in Hardware Mode ............................................. 43
Table 4. Serial Audio Input Formats Available in Hardware Mode ................................................ 43
Table 5. Second Line Part Marking ...............................................................................................57
Table 6. Locking to RXP/RXN - Fs = 8 to 96 kHz ......................................................................... 57
Table 7. Locking to RXP/RXN - Fs = 32 to 96 kHz ....................................................................... 57
Table 8. Locking to the ILRCK Input .............................................................................................58
Table 9. Revision History .............................................................................................................. 60
4 DS477F5
CS8427
1. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T
= 25°C.
A
SPECIFIED OPERATING CONDITIONS
AGND, DGND = 0 V, all voltages with respect to 0 V.
Parameter Symbol Min Typ Max Units
Power Supply Voltage
(Note 1)
VA+
VL+
4.5
2.85
5.0
3.3 or 5.0
5.5
5.5
V
V
Ambient Operating Temperature: ‘-CS’, ‘CSZ’ & ‘-CZ’
‘-DS’ & ‘-DZ’
Notes: 1. I²C protocol is supported only in VL+ = 5.0 V mode.
T
A
-10
-40
-
-
+70
+85
°C
ABSOLUTE MAXIMUM RATINGS
AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Parameter Symbol Min Max Units
Power Supply Voltage VL+,VA+ - 6.0 V
Input Current, Any Pin Except Supplies (Note 2) I
Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
Notes: 2. Transient currents of up to 100 mA will not cause SCR latch-up.
in
in
A
stg
-±10mA
-0.3 (VL+) + 0.3 V
-55 125 °C
-65 150 °C
DS477F5 5
DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameters Symbol Min Typ Max Units
Power-down Mode
Supply Current in power down VA+
Normal Operation
Supply Current at 48 kHz frame rate VA+
Supply Current at 96 kHz frame rate VA+
(Note 3)
VL+ = 3.3 V
VL+ = 5.0 V
(Note 4)
VL+ = 3.3 V
VL+ = 5.0 V
VL+ = 3.3 V
VL+ = 5.0 V
CS8427
-
-
-
-
-
-
-
-
-
20
60
60
6.3
30.1
46.5
6.6
44.8
76.6
-
-
-
-
-
-
-
-
-
μA
μA
μA
mA
mA
mA
mA
mA
mA
Notes: 3. Power Down Mode is defined as RST
4. Normal operation is defined as RST
= LO with all clocks and data lines held static.
= HI.
DIGITAL INPUT CHARACTERISTICS
Parameters Symbol Min Typ Max Units
Input Leakage Current I
Differential Input Voltage, RXP0 to RXN V
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameters Symbol Min Max Units
High-Level Output Voltage (I
Low-Level Output Voltage (I
High-Level Output Voltage, TXP, TXN (23 mA at VL+ = 5.0 V)
Low-Level Output Voltage, TXP, TXN (23 mA at VL+ = 5.0 V)
High-Level Input Voltage, except RXP, RXN V
Low-Level Input Voltage, except RXP, RXN (Note 5) V
Notes: 5. At 5.0 V mode, V
= -3.2 mA), except TXP/TXN V
OH
= 3.2 mA), except TXP/TXN V
OH
(15.2 mA at VL+ = 3.3 V)
(15.2 mA at VL+ = 3.3 V)
= 0.8 V (Max), at 3.3 V mode, VIL =0.4 V (Max).
IL
in
TH
OH
OL
IH
IL
-±1±10μA
-200- mV
(VL+) - 1.0 - V
-0.4V
(VL+) - 0.7
(VL+) - 0.7
-
-
-
-
0.7
0.7
V
V
V
V
2.0 (VL+) + 0.3 V
-0.3 0.4/0.8 V
TRANSMITTER CHARACTERISTICS
Parameters Symbol Min Typ Max Units
TXP Output Resistance VL+ = 5.0 V
VL+ = 3.3 V
TXN Output Resistance VL+ = 5.0 V
VL+ = 3.3 V
6 DS477F5
R
R
TXP
TXN
-
-
-
-
26
40
26
40
-
-
-
-
Ω
Ω
Ω
Ω
CS8427
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
RST
pin Low Pulse Width 200 - - μs
OMCK Frequency for OMCK = 512 * Fso 4.1 - 55.3 MHz
OMCK Low and High Width for OMCK = 512 * Fso 7.2 - - ns
OMCK Frequency for OMCK = 384 * Fso 3.1 - 41.5 MHz
OMCK Low and High Width for OMCK = 384 * Fso 10.8 - - ns
OMCK Frequency for OMCK = 256 * Fso 2.0 - 27.7 MHz
OMCK Low and High Width for OMCK = 256 * Fso 14.4 - - ns
PLL Clock Recovery Sample Rate Range 8.0 - 108.0 kHz
RMCK output jitter (Note 6) - 200 - ps RMS
RMCK output duty cycle 40 50 60 %
RMCK Input Frequency (Note 7) 1.8 - 27.7 MHz
RMCK Input Low and High Width (Note 7) 14.4 - - ns
AES3 Transmitter Output Jitter - - 1 ns
Notes: 6. Cycle-to-cycle locking to RXP/RXN using 32 to 96 kHz external PLL filter components.
7. PLL is bypassed (RXD1:0 bits in the Clock Source Control register set to 10b), clock is input to the
RMCK pin.
DS477F5 7
CS8427
sckh
sckl
sckw
t
t
t
t
dpd
SDOUT
(input)
(input)
SDIN
dh
t
ds
t
lrcks
t
lrckd
t
ISCLK
OSCL K
ILRCK
OLRCK
t
smd
t
lm d
Hardware Mode
Software Mode
ISC LK
OSCLK
(output)
ILRCK
OLRCK
(output)
RMCK
(output)
RMCK
(output)
OMCK
(input)
Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
OSCLK Active Edge to SDOUT Output Valid (Note 8) t
SDIN Setup Time Before ISCLK Active Edge (Note 8) t
SDIN Hold Time After ISCLK Active Edge (Note 8) t
dpd
ds
dh
Master Mode
O/RMCK to I/OSCLK active edge delay (Note 8, 9) t
O/RMCK to I/OLRCK delay (Note 10) t
smd
lmd
I/OSCLK and I/OLRCK Duty Cycle - 50 - %
Slave Mode
I/OSCLK Period (Note 11) t
I/OSCLK Input Low Width t
I/OSCLK Input High Width t
I/OSCLK Active Edge to I/OLRCK Edge
sckw
sckl
sckh
t
lrckd
(Note 8, 10, 12)
I/OLRCK Edge Setup Before I/OSCLK Active Edge
t
lrcks
(Note 8, 10, 13)
- - 20 ns
20 - - ns
20 - - ns
0 - 10 ns
0 - 10 ns
36 - - ns
14 - - ns
14 - - ns
20 - - ns
20 - - ns
Notes: 8. The active edges of ISCLK and OSCLK are programmable.
9. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising
edge. When these signals are derived from RMCK, they are clocked from its falling edge.
10. The polarity of ILRCK and OLRCK is programmable.
11. No more than 128 SCLK per frame.
12. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
13. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has
changed.
8 DS477F5
CS8427
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
pd
CDOUT
t
csh
Figure 3. SPI Mode timing
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency (Note 14) f
CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 15) t
CCLK Falling to CDOUT Stable t
Rise Time of CDOUT t
Fall Time of CDOUT t
Rise Time of CCLK and CDIN (Note 16) t
Fall Time of CCLK and CDIN (Note 16) t
sck
csh
css
scl
sch
dsu
dh
pd
r1
f1
r2
f2
Notes: 14. If Fso or Fsi is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fso and
less than 128 Fsi. This is dictated by the timing requirements necessary to access the Channel Status
and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate.
The minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to
1.024 MHz should be safe for all possible conditions.
15. Data must be held for sufficient time to bridge the transition time of CCLK.
16. For f
< 1 MHz.
sck
0-6.0MHz
1.0 - - μs
20 - - ns
66 - - ns
66 - - ns
40 - - ns
15 - - ns
- - 50 ns
- - 25 ns
- - 25 ns
- - 100 ns
- - 100 ns
DS477F5 9
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE
t
buf
t
hdst
t
hdst
t
low
t
r
t
f
t
hdd
t
high
t
sud
t
sust
t
susp
Stop Start
Start
Stop
Repeated
SDA
SCL
Figure 4. I²C Mode timing
Note 17, Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
SCL Clock Frequency f
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 18) t
SDA Setup Time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
Notes: 17. I²C protocol is supported only in VL+ = 5.0 V mode.
18. Data must be held for sufficient time to bridge the 25 ns transition time of SCL.
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
- - 100 kHz
4.7 - - μs
4.0 - - μs
4.7 - - μs
4.0 - - μs
4.7 - - μs
0--μs
250 - - ns
- - 25 ns
- - 25 ns
4.7 - - μs
CS8427
10 DS477F5
* A separate analog supply is only necessary in applications where RMCK is used
for a jitter sensitive task. For applications where RMCK is not used for a jitter
sensitive task, connect VA+ to VD+ via a ferrite bead. Keep the decoupling
capacitor between VA+ and AGND.
CS8427
Cable
Termination
RXP
RXN
AES3/
SPDIF
Source
3-wire Serial
Audio Source
ILRCK
ISCLK
SDIN
Clock Source
and Control
RMCK
OMCK
Hardware
Control
RST
RERR
EMPH
TCBL
To other
CS8427's
Cable
Interface
AES3/
SPDIF
Equipment
TXP
TXN
3-wire Serial
Audio Input
Device
OLRCK
OSCLK
SDOUT
Microcontroller
SDA/CDOUT
AD0/CS
SCL/CCLK
AD1/CDIN
U
INT
VA+ V L+
Ferrite *
Bead
+5.0 V
Analog
Supply*
0.1 Fμ
0.1 Fμ
DGNDFILTAGND
RFILT
CFILT CRIP
H/S
+3.3 V or +5.0 V
Digital Supply
DA2/
Figure 5. Recommended Connection Diagram for Software Mode
2. TYPICAL CONNECTION DIAGRAM
CS8427
DS477F5 11
CS8427
3. GENERAL DESCRIPTION
The CS8427 is an AES3 transceiver intended to be
used in digital audio systems. Such systems include digital mixing consoles, effects processors,
digital recorders, and computer multimedia systems.
3.1 Audio Input/Output Ports
The CS8427 has the following Audio ports:
• Serial Audio Input Port
• Serial Audio Output Port
• AES3 or S/PDIF Receiver
• AES3 or S/PDIF Transmitter
The Serial Audio ports use a three-wire format.
This consists of a serial audio data stream, a leftright clock defining the boundaries of the audio
sample frames, and a serial clock signal clocking
the data bits.
A Serial Audio port may operate in either Master or
Slave mode. When a port is a Master, it supplies
the left-right clock and the serial clock to the
nal device that is sending or receiving the serial data
A port in slave mode must have its left-right clock
and its serial clock supplied by an external device
so that it may send or receive serial audio data.
The input sample rate is determined by the stream
applied to the Serial Audio Input or to the AES3 Receiver. A phase-locked loop recovers RMCK, the
input master clock signal, from the chosen input
stream.
The output from the device may be through the Serial Audio Output, the AES3 Transmitter, or from
both simultaneously. In some configurations, all
audio ports of the device may be in use at the same
time.
exter-
3.2 Serial Control Port
Besides the functional blocks already described,
the device also has a control port that allows the
user to read and write the control registers that
configure the part. The control port is capable of
operating in either SPI or I²C serial mode. This port
also has access to buffer memory that allows the
user to control what is transmitted in the Channel
Status and User bits of the outgoing AES3 stream.
The control port is clocked by the serial clock signal that the user's microcontroller sends it. The
MCU can read and write the registers even when
the RMCK and OMCK clocks are not running. The
Channel Status and User bit buffer memories depend on clocking from RMCK and OMCK. They will
not function unless the clocks are running, and the
RUN bit in the Clock Source Control register is set.
There is also an interrupt signal associated with
the Serial Control Port and the internal registers.
The format of the interrupt may be chosen by a register setting. There are two interrupt status registers and their associated interrupt mask registers.
3.3 Channel Status and User bit Memory
The memory architecture consists of three buffers
to handle the Channel Status information, and another three buffers to handle the User bits. The
data recovery logic extracts the Channel Status
and User bits from the AES3 stream and places
them in their respective D buffers. Each buffer contains 384 bits.
This is enough memory to hold a complete block of
.
Channel Status bits from both A and B channels
and a complete block of User bits.
When the D buffers are full, the chip transfers their
contents into the E buffers. While in the E buffers
the Channel Status and User bits may be read or
written through the control port. This allows the
user to alter them to suit the needs of the application. The control bit BSEL, in the Channel Status
Data Buffer Control register, determines whether
the control port has access to the Channel Status
bits or the User bits. The AES3 encoder reads the
Channel Status and User bits from the F buffers
and inserts them into the outgoing AES3 stream.
After the F buffers bits are transmitted, the device
transfers the current contents of the E buffers into
the F buffers.
In applications using AES3 in and AES3 out, the
CS8427 can automatically transceive user data
that conforms to the IEC60958 format. The
CS8427 also gives the user access to the bits necessary to comply with the serial copy management
system (SCMS).
In applications where the user want to read/modify/write the Channel Status information that requires a microcontroller to actively manage the
12 DS477F5
CS8427
Figure 6. CS8427 Internal Block Diagram
Serial
Audio
Input
AES3
Encoder
Serial
Audio
Output
Receiver
RXP
RXN
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUT
TXP
TXN
AES3
TXOFFAESBP
SPD1-0
TXD1-0
Channel
Status
and
User Data
Recovery
Control
Port
Control
Registers
Channel
Status Bits
D
User Bits
D
EF
E
F
SDA/CDOUT
SCL/CCLK
AD1/CDIN
AD0/CS
INT
Output
Clock
Generator
OMCK
AD2/EMPH
Channel Status bits. The part also has a feature
that allows the first five bytes of Channel Status
memory to be configured and transmitted in each
channel status block without change. See “Appen-
dix A: External AES3/SPDIF/IEC60958 Transmitter and Receiver Components” on page 50 for a
tutorial in Channel Status and User bit management.
3.4 AES3 and S/PDIF Standards
This data sheet assumes that the user is familiar
with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3 and
IEC60958 specifications on hand for easy reference.
The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org or
www.ansi.org. Obtain the latest IEC60958 stan-
dard from ANSI or from the International Electrotechnical Commission at www.iec.ch. The latest
Documents
EIAJ CP-1201 standard is available from the Japanese Electronics Bureau.
Crystal Application Note AN22: Overview of Digital
Audio Interface Data Structures contains a useful
tutorial on digital audio specifications, but it should
not be considered a substitute for the standards.
The paper, An Understanding and Implementation
of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is
an excellent tutorial on SCMS. It is available from
the AES as preprint 3518.
4. DATA I/O FLOW AND CLOCKING OPTIONS
The CS8427 can be configured for several connectivity alternatives, called data flows. Figure 7. “Soft-
ware Mode Audio Data Flow Switching Options” on
page 19 shows the data flow switching, along with
the control register bits which control the switches;
this drawing only shows the audio data paths for
simplicity. This drawing only shows the audio data
paths for simplicity. Figure 8 shows the internal
DS477F5 13
CS8427
clock routing and the associated control register
bits. The clock routing constraints determine which
data routing options are actually usable. Users
should note that not all the possible data flow
switch setting combinations are valid, because of
the clock distribution architecture.
The AESBP switch, shown in Figure 7, allows a
TTL level bi-phase, mark-encoded data stream
connected to RXP to be routed to the TXP and
TXN pin drivers. The TXOFF switch causes the
TXP and TXN outputs to be driven to ground.
There are two possible clock sources. The first,
designated the recovered clock, is the output of the
PLL, and is output through the RMCK pin. The input to the PLL can be either the incoming AES3
data stream or the ILRCK word rate clock from the
serial audio input port. The second clock is input
through the OMCK pin and would normally be a
crystal derived stable clock. The Clock Source
Control Register bits determine which clock is used
to operate the CS8427.
The CS8427 has another constraint related to the
state machine that governs the startup of the part.
The startup state machine doesn’t complete its
process until the PLL has locked unless one is in
the transmitter dataflow (See Figure 10). The consequence of this is that the transmitter will not
transmit until the PLL has locked. If you wish to use
the part in transceiver mode and this constraint is
a problem, there is a work around. Start the part up
in its default configuration and allow the PLL to lock
to a signal on the ILRCK pin, then without stopping
the part, reconfigure it to the transceiver mode.
By studying the following drawings and appropriately setting the Data Flow Control and Clock
Source Control register bits, the CS8427 can be
configured to fit a variety of customer requirements. Please note that applications implementing
both the Serial Audio Output Port and the AES3
Transmitter must operate at the same sample rate
because they are both controlled by the same
clock source.
Figure 9 shows the entire data path clocked by the
PLL generated recovered clock. Figure 10 illustrates a standard AES3 receiver function. Figure
11 shows a standard AES3 transmitter function
without PLL. Figure 12 shows a standard AES3
transmitter function with PLL.
14 DS477F5
CS8427
5. THREE-WIRE SERIAL AUDIO PORTS
A 3-wire serial audio input port and a 3-wire serial
audio output port is provided. Each port can be adjusted to suit the attached device by setting the
control registers. The following parameters are adjustable: master or slave, serial clock frequency,
audio data resolution, left or right justification of the
data relative to left/right clock, optional 1-bit cell
delay of the 1st data bit, the polarity of the bit clock,
and the polarity of the left/right clock. By setting the
appropriate control bits, many formats are possible.
Figure 15 shows a selection of common input for-
mats, along with the control bit settings. It should
be noted that in right justified mode, the serial audio output data is “MSB extended”. This means
that in a sub-frame where the MSB of the data is
'1', all bits preceding the MSB in the sub-frame will
also be '1'. Conversely, in a sub-frame where the
MSB of the data is '0', all bits preceding the MSB in
the sub-frame will also be '0'.
The clocking of the input section of the CS8427
may be derived from the incoming ILRCK word
rate clock, using the on-chip PLL. The PLL operation is described in “AES3 Receiver” on page 16. In
the case of use with the serial audio input port, the
PLL locks onto the leading edges of the ILRCK
clock.
Figure 16 shows a selection of common output for-
mats, along with the control bit settings. A special
AES3 direct output format is included, which allows
serial output port access to the V, U, and C bits embedded in the serial audio data stream. The P bit is
replaced by a Z bit that marks the subframe just prior to the start of each block. This format is only
available when the serial audio output port is being
clocked by the AES3 receiver recovered clock.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the appropriate
clock domain master clock.
In slave mode, the left/right clock and the serial bit
clock are inputs. The left/right clock must be synchronous to the appropriate master clock, but the
serial bit clock can function in asynchronous burst
mode if desired. By appropriate phasing of the
left/right clock and control of the serial clocks,
CS8427’s can be multiplexed to share one serial
port. The left/right clock should be continuous, but
the duty cycle does not have to be 50%, provided
that enough serial clocks are present in each
phase to clock all the data bits. When in slave
mode, the serial audio output port must not be set
to right justified data.
When using the serial audio output port in slave
mode with an OLRCK input which is asynchronous
to the port’s data source, an interrupt bit (OSLIP) is
provided to indicate when repeated or dropped
samples occur.
DS477F5 15
CS8427
6. AES3 RECEIVER
The CS8427 includes an AES3 digital audio receiver and an AES3 digital audio transmitter. A
comprehensive buffering scheme provides
read/write access to the channel status and user
data. This buffering scheme is described in “Ap-
pendix B: Channel Status and User Data Buffer
Management”.
The AES3 receiver accepts and decodes audio
and digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards.
The receiver consists of a differential input stage,
accessed through pins RXP and RXN, a PLL
based clock recovery circuit, and a decoder which
separates the audio data from the channel status
and user data.
External components are used to terminate and
isolate the incoming data cables from the CS8427.
These components are detailed in “Appendix A:
External AES3/SPDIF/IEC60958 Transmitter and
Receiver Components” on page 50.
6.1 OMCK System Clock Mode
A special mode is available that allows the clock
that is being input through the OMCK pin to be output through the RMCK pin. This feature is controlled by the SWCLK bit in control register 1.
When the PLL loses lock, the frequency of the
VCO drops to 300 kHz. The SWCLK function allows the clock from RMCK to be used as a clock in
the system without any disruption when input is removed from the Receiver. This clock switching is
performed glitch free. None of the internal circuitry
that is clocked from the PLL is driven by the OMCK
being output from RMCK. This function is available
only in software mode.
6.2 PLL, Jitter Attenuation, and Varispeed
Please see Appendix C for general description of
the PLL, selection of recommended PLL filter components, and layout considerations. Figure 5
shows the recommended configuration of the two
capacitors and one resistor that comprise the PLL
filter.
6.3 Error Reporting and Hold Function
While decoding the incoming AES3 data stream,
the CS8427 can identify several kinds of error, indicated in the Receiver Error register. The UNLOCK bit indicates whether the PLL is locked to
the incoming AES3 data. The V bit reflects the current validity bit status. The BIP (bi-phase) error bit
indicates an error in incoming bi-phase coding.
The PAR (parity) bit indicates a received parity error.
The error bits are “sticky”: they are set on the first
occurrence of the associated error and will remain
set until the user reads the register through the
control port. This enables the register to log all unmasked errors that occurred since the last time the
register was read.
The Receiver Error Mask register allows masking
of individual errors. The bits in this register serve
as masks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error
is unmasked, which implies the following: its occurrence will be reported in the receiver error register,
induce a pulse on RERR, invoke the occurrence of
a RERR interrupt, and affect the current audio
sample according to the status of the HOLD bits.
The HOLD bits allow a choice of holding the previous sample, replacing the current sample with zero
(mute), or not changing the current audio sample.
If a mask bit is set to 0, the error is masked, which
implies the following: its occurrence will not be reported in the receiver error register, will not induce
a pulse on RERR or generate a RERR interrupt,
and will not affect the current audio sample. The
QCRC and CCRC errors do not affect the current
audio sample, even if unmasked
6.4 Channel Status Data Handling
The first two bytes of the Channel Status block are
decoded into the Receiver Channel Status register. The setting of the CHS bit in the Channel Status Data Buffer Control register determines
whether the channel status decodes are from the A
channel (CHS = 0) or B channel (CHS = 1).
The PRO (professional) bit is extracted directly.
For consumer data, the COPY (copyright) bit is extracted, and the category code and L bits are decoded to determine SCMS status, indicated by the
ORIG (original) bit. If the category code is set to
16 DS477F5
CS8427
General on the incoming AES3 stream, copyright
will always be indicated even when the stream indicates no copyright. Finally, the AUDIO
tracted and used to set an AUDIO
described in the Non-Audio Auto-Detection section
below.
If 50/15 µs pre-emphasis is detected, the state of
the EMPH
The encoded channel status bits which indicate
sample word length are decoded according to
AES3-1992 or IEC 60958. Audio data routed to the
serial audio output port is unaffected by the word
length settings - all 24 bits are passed on as received.
“Appendix B: Channel Status and User Data Buffer
Management” on page 52 describes the overall
handling of Channel Status and User bit data.
pin is adjusted accordingly.
bit is ex-
indicator, as
6.5 User Data Handling
The incoming user data is buffered in a user accessible buffer. Various automatic modes of re-transmitting received User data are provided. The
Appendix: Channel Status and User Data Buffer
Management describes the overall handling of CS
and U data.
Received User data may also be output to the U
pin, under the control of a control register bit. Depending on the data flow and clocking options selected, there may not be a clock available to qualify
the U data output. Figure 13 illustrates the timing.
If the incoming user data bits have been encoded
as Q-channel subcode, the data is decoded and
presented in ten consecutive register locations. An
interrupt may be enabled to indicate the decoding
of a new Q-channel block, which may be read
through the control port.
6.6 Non-Audio Auto Detection
An AES3 data stream may be used to convey nonaudio data, thus it is important to know whether the
incoming AES3 data stream is digital audio or not.
This information is typically conveyed in channel
status bit 1 (AUDIO
cally by the CS8427. However, certain non-audio
sources, such as AC3
not adhere to this convention, and the bit may not
be properly set. The CS8427 AES3 receiver can
detect such non-audio data. This is accomplished
by looking for a 96-bit sync code, consisting of
0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and
0x4E1F. When the sync code is detected, an internal AUTODETECT signal will be asserted. If no additional sync codes are detected within the next
4096 frames, AUTODETECT will be de-asserted
until another sync code is detected. The AUDIO
in the Receiver Channel Status register is the logical OR of AUTODETECT and the received channel status bit 1. If non-audio data is detected, the
data is still processed exactly as if it were normal
audio. It is up to the user to mute the outputs as required.
), which is extracted automati-
or MPEG encoders, may
bit
DS477F5 17
CS8427
7. AES3 TRANSMITTER
The AES3 transmitter encodes and transmits audio and digital data according to the AES3,
IEC60958 (S/PDIF), and EIAJ CP-1201 interface
standards. Audio and control data are multiplexed
together and bi-phase, mark encoded. The resulting bit stream is driven to an output connector either directly or through a transformer.
The transmitter clock may be derived from the
clock input pin OMCK, or from the incoming data.
If OMCK is asynchronous to the data source, an interrupt bit (TSLIP) is provided that will go high every time a data sample is dropped or repeated. Be
aware that the pattern of slips does not have hysteresis and so the occurrence of the interrupt condition is not deterministic.
The channel status (C) and user channel (U) bits in
the transmitted data stream are taken from storage
areas within the CS8427. The user can manually
access the internal storage or configure the
CS8427 to run in one of several automatic modes.
The Appendix: Channel Status and User Data
Buffer Management provides detailed descriptions
of each automatic mode and describes methods of
manually accessing the storage areas. The transmitted user data can optionally be input through
the U pin, under the control of a control port register bit. Figure 13 shows the timing requirements for
clocking U data through the U pin.
7.1 Transmitted Frame and Channel Status Boundary Timing
The TCBL pin is used to control or indicate the start
of transmitted channel status block boundaries and
may be used as an input or output.
In some applications, it may be necessary to control the precise timing of the transmitted AES3
frame boundaries. This may be achieved in three
ways:
1) With TCBL set to input, driving TCBL high for
>3 OMCK clocks will cause a frame start, as well as
a new channel status block start.
2) If the AES3 output comes from the AES3 input, setting TCBL as output will cause AES3 output frame
boundaries to align with AES3 input frame boundaries.
3) If the AES3 output comes from the serial audio input port while the port is in slave mode and TCBL
is set to output, the start of the A channel sub-frame
will be aligned with the leading edge of IL-CK.
7.2 TXN and TXP Drivers
The line drivers are low skew, low impedance, differential outputs capable of driving cables directly.
Both drivers are set to ground during reset
(RST
= low), when no AES3 transmit clock is provided, and optionally under the control of a register
bit. The CS8427 also allows immediate mute of the
AES3 transmitter audio data through a control register bit.
External components are used to terminate and
isolate the external cable from the CS8427. These
components are detailed in Appendix A: External
AES3/SPDIF/IEC60958 Transmitter and Receiver
Components.
18 DS477F5
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