Cirrus Logic CS8421 User Manual
Serial
Audio
Input
Time
Varying
Digital
Filters
BYPASS
Digital
PLL
Clock
Generator
ILRCK
ISCLK
SDIN
Sync Info
Data
Serial
Audio
Output
OLRCK
OSCLK
SDOUT
XTI XTO
SRC_UNLOCK
2.5 V (VD) GND
RST
Sync Info
Data
Data
Level Translators
TDM_IN
MS_SEL
SAIF
SAOF
Serial
Port
Mode
Decoder
Level Translators
Level Translators
MCLK_OUT
3.3 V or 5.0 V (VL)
CS8421
32-bit, 192-kHz Asynchronous Sample Rate Converter
Features
175 dB Dynamic Range
–140 dB THD+N
No Programming Required
No External Master Clock Required
Supports Sample Rates up to 211 kHz
Input/Output Sample Rate Ratios of 7.5:1 to 1:8
Master Clock Support for 128 x Fs, 256 x Fs,
384 x Fs, and 512 x Fs (Master Mode)
16-, 20-, 24-, or 32-bit Data I/O
32-bit Internal Signal Processing
Dither Automatically Applied and Scaled to
Output Resolution
Flexible 3-wire Serial Digital Audio Input and
Output Ports
Master and Slave Modes for Both Input and
Output
Bypass Mode
Time Division Multiplexing (TDM) Mode
Attenuates Clock Jitter
Multiple Device Outputs are Phase Matched
Linear Phase FIR Filter
Automatic Soft Mute/Unmute
+2.5 V Digital Supply (VD)
+3.3 V or 5.0 V Digital Interface (VL)
Space-saving 20-pin TSSOP and QFN
Packages
The CS8421 supports sample rates up to 211 kHz and
is available in 20-pin TSSOP and QFN packages in both
Commercial (-10° to +70°C) and Automotive (-40° to
+85°C and -40° to +105°C) grades. The CDB8421 Customer Demonstration board is also available for device
evaluation and implementation suggestions. See “Or-
dering Information” on page 35 for complete details.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
JULY ‘12
DS641F6
CS8421
General Description
The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter.
Digital audio inputs and outputs can be 32, 24, 20, or 16 bits. Input and output data can be completely asynchronous,
synchronous to an external dat a clock, or the part can operate without any external clock by using an integrated
oscillator.
Audio data is input and output through configur able 3-wire input/output ports. The CS8421 does no t require any software control via a control port.
Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mixing consoles, high-quality D/A, effects processors, computer audio systems, and automotive audio systems.
The CS8421 is also suitable for use as an asynchronous decimation or interpolation filter. See Cirrus Logic Application Note AN270, “Audio A/D Conversion with an Asynchronous Decimation Filter”, available at www.cirrus.com
for more details.
2 DS641F6
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................ 5
1.1 TSSOP Pin Descriptions ........... ... ... ... ... .... ... ... ... .... ... .......................................... ... ........................ 5
1.2 QFN Pin Descriptions .......................................................................... ... ... ... .... ... ... ... ... .................. 7
2. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 9
SPECIFIED OPERATING CONDITIONS.............................................................................................. 9
ABSOLUTE MAXIMUM RATINGS........................................................................................................9
PERFORMANCE SPECIFICATIONS......................................... ......................................................... 10
DIGITAL FILTER CHARACTERISTICS .............................................................................................. 11
DC ELECTRICAL CHARACTERISTICS ....................... ... ... ... .... ... ... ... ... .......................................... ... 11
DIGITAL INPUT CHARACTERISTICS................................................................................................ 12
DIGITAL INTERFACE SPECIFICATIONS .......................................................................................... 12
SWITCHING SPECIFICATIONS ......................................................................................................... 12
3. TYPICAL CONNECTION DIAGRAMS ................................................................................................14
4. APPLICATIONS .................................................................................................................................. 16
4.1 Three-wire Serial Input/Output Audio Port .................................................................................... 16
4.2 Mode Selection .......................................................... ... .......................................... ... ................... 17
4.3 Sample Rate Converter (SRC) ..................................................................................................... 19
4.3.1 Data Resolution and Dither .............................. ... .... ... ... ... ... .... ... ... ... ................................ 19
4.3.2 SRC Locking and Varispeed .. ... .... ... .......................................... ... ... .... ... ... ... ... .... ... ... ... ... 19
4.3.3 Bypass Mode ......... ... .... ... ... ... ... .... ... ... ... .......................................... .... ............................ 19
4.3.4 Muting ....... ... .... ... ... ... .... ...................................... .... ... ... ... ... .... ......................................... 20
4.3.5 Group Delay and Phase Matching Between Multiple CS8421 Parts ............................... 20
4.3.6 Master Clock ....................................... ............................................................................. 20
4.3.7 Clocking .... ... .... ... ... ....................................... ... ... .... ... ... ... ................................................ 21
4.4 Time Division Multiplexing (TDM) Mode ....................................................................................... 21
4.5 Reset, Power-Down, and Start-Up ............................................................................................... 22
4.6 Power Supply, Grounding, and PCB Layout ................................................................................ 23
5. PERFORMANCE PLOTS ................................................................................................................ 24
6. PACKAGE DIMENSIONS ................................................................................................................... 33
TSSOP THERMAL CHARACTERISTICS ........................................... ... .... ... ... ... .... ............................ 33
QFN THERMAL CHARACTERISTICS.......................................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 34
7. ORDERING INFORMATION ............................................................................................................... 35
8. REVISION HISTORY .......................................................................................................................... 35
CS8421CS8421
LIST OF FIGURES
Figure 1. Non-TDM Slave Mode Timing..................................................................................................... 13
Figure 2. TDM Slave Mode Timing ............................................................................................................ 13
Figure 3. Non-TDM Master Mode Timing................................................................................................... 13
Figure 4. TDM Master Mode Timing .......................................................................................................... 13
Figure 5. Typical Connection Diagram, No External Master Clock............................ .... ............................ 14
Figure 6. Typical Connection Diagram, Master and Slave Modes............................................................. 15
Figure 7. Serial Audio Interface Format - I²S ............................................................................................. 17
Figure 8. Serial Audio Interface Format - Left-Justified.............................................................................. 17
Figure 9. Serial Audio Interface Format - Right-Justified ........................................................................... 17
Figure 10. Typical Connection Diagram for Crystal Circuit ........................................................................ 21
Figure 11. TDM Slave Mode Timing Diagram............................................................................................ 21
Figure 12. TDM Master Mode Timing Diagram.......................................................................................... 22
Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)....................................................... 22
Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave).................... 22
Figure 15. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz..................................... 24
Figure 16. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz................................ 24
Figure 17. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz.................................. 24
DS641F6 3
CS8421
Figure 18. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz.................. .... ... ... ... ... 24
Figure 19. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:96 kHz.................. ... .... ... ... ... ... 24
Figure 20. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 96 kHz:48 kHz.................. ... .... ... ... ... ... 24
Figure 21. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 192 kHz:48 kHz................... .... ... ... ... ... 25
Figure 22. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz: 96 kHz......... ... ... ... .... ... ... ... ... 25
Figure 23. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz: 48 kHz......... ... ... ... .... ... ... ... ... 25
Figure 24. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz. ... ... ... ... .... ... ... ... ... 25
Figure 25. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz............................... 25
Figure 26. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz: 44.1 kHz......... ... ... .... ... ... ... ... 25
Figure 27. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 96 kHz: 48 kHz......... ... ... ... .... ... ... ... ... 26
Figure 28. IMD, 10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz ................................................................... 26
Figure 29. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 192 k Hz:48 kHz....... ... ... ... .... ... ... ... ... 26
Figure 30. IMD, 10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz ................................................................ 26
Figure 31. IMD, 10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz ................................................................ 26
Figure 32. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz................................ 26
Figure 33. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Tone, 192 kHz:192 kHz............................... 27
Figure 34. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:96 kHz................ ... .... ... ... ... ... 27
Figure 35. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:48 kHz................ ... .... ... ... ... ... 27
Figure 36. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 96 kHz:48 kHz................ ... .... ... ... ... ... 27
Figure 37. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz................ .... ... ... ... ... 27
Figure 38. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 192 kHz ..................................... 27
Figure 39. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 48 kHz ....................................... 28
Figure 40. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 96 kHz ....................................... 28
Figure 41. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 44.1 kHz .................................... 28
Figure 42. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 192 kHz . ... .... ...... ... ... 28
Figure 43. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 32 kHz ....................................... 28
Figure 44. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 32 kHz ... ....... ... ... ... ... 28
Figure 45. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 96 kHz ... ....... ... ... ... ... 29
Figure 46. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz ................... 29
Figure 47. Frequency Response with 0 dBFS Input ..................................................................................29
Figure 48. Passband Ripple, 192 kHz:48 kHz ..................... ... ... ... .... ... ... ... ... .... ... ... ................................... 29
Figure 49. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 48 kHz ... ....... ... ... ... ... 29
Figure 50. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz........................................ 29
Figure 51. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz..................................... 30
Figure 52. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz........................................ 30
Figure 53. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz........................................ 30
Figure 54. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz................................... 30
Figure 55. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz ..................................... 30
Figure 56. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz................................... 30
Figure 57. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:44.1 kHz ..................................................... 31
Figure 58. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:96 kHz ........................................................ 31
Figure 59. THD+N vs. Input Amplitude, 1 kHz Tone, 96 kHz:48 kHz ........................................................ 31
Figure 60. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:192 kHz ................................................... 31
Figure 61. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:48 kHz ..................................................... 31
Figure 62. THD+N vs. Input Amplitude, 1 kHz Tone, 192 kHz:48 kHz ...................................................... 31
Figure 63. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:44.1 kHz........................................................... 32
Figure 64. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:96 kHz.............................................................. 32
Figure 65. THD+N vs. Frequency Input, 0 dBFS, 44.1 kHz:48 kHz........................................................... 32
Figure 66. THD+N vs. Frequency Input, 0 dBFS, 96 kHz:48 kHz.............................................................. 32
LIST OF TABLES
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL) ................. 18
Table 2. Serial Audio Input Port Start-Up Options (SAIF).......................................................................... 18
Table 3. Serial Audio Output Port Start-Up Options (SAOF) ..................................................................... 18
4 DS641F6
1. PIN DESCRIPTIONS
1
2
3
4
5
16
6
7
8
15
14
13
12
11
9
10
17
18
19
20
SRC_UNLOCK
XTO
SAIF
XTI
SAOF
VD
VL
GND
GND
RST
MS_SEL
BYPASS
OLRCK
ILRCK
OSCLK
ISCLK
SDOUT
SDIN
TDM_IN
MCLK_OUT
1.1 TSSOP PIN DESCRIPTIONS
CS8421CS8421
DS641F6 5
Pin Name # Pin Description
XTO 1 Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 20.
XTI 2
VD 3 Digital Power (Input) - Digital core power supply. Typically +2.5 V.
GND 4 Ground (Input) - Ground for I/O and core logic.
RST
BYPASS 6
ILRCK 7
ISCLK 8 Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDIN pin.
SDIN 9 Serial Audio Input Data Port (Input) - Audio data serial input pin.
MCLK_OUT 10
TDM_IN 11
SDOUT 12
OSCLK 13 Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDOUT pin.
OLRCK 14
MS_SEL 15
GND 16 Ground (Input) - Ground for I/O and core logic.
VL 17 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
SAOF 18
SAIF 19
SRC_UNLOCK 20
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock”
on page 20.
Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are
5
reset. On initial power-up, RST must be held low until the power supply is stable and all input
clocks are stable in frequency and phase.
Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample rate converter will
be bypassed, and any data input through the serial audio input port will be directly output on the
serial audio output port. When BYPASS is low, the sample rate converter will operate normally.
Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDIN pin.
Master Clock Output (Output) - Buffered and level-shifted output for Master clock. If MCLK_OUT
is not required, this pin should be pulled high through a 47 k resistor to turn the output off. See
“Master Clock” on page 20.
Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded
when not used. See “Time Division Multiplexing (TDM) Mode” on page 21.
Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally , this pin may be
pulled low through a 47-k resistor, but must not be pulled high.
Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDOUT pin.
Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio
ports at startup and reset. See Table 1 on page 18 for settings.
Serial Audio Output Format Select (Input) - Used to select the serial audio output format at
startup and reset. See Table 3 on page 18 for format settings.
Serial Audio Input Format Select (
and reset. See Table 2 on page 18 for format settings.
SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and
Varispeed” on page 19.
Input) - Used to select the serial audio input format at startup
CS8421
6 DS641F6
1.2 QFN PIN DESCRIPTIONS
76
5
4
3
2
1
8
9
10
11
12
13
14
15
16
17
181920
Top-Down View
20-pin QFN Package
Thermal Pad
XTI
XTO
SRC_UNLOC
SAIF
SAOF
ISCLK
SDIN
MCLK_OUT
TDM_IN
SDOUT
VD
GND
RST
BYPASS
ILRCK
VL
GND
MS_SEL
OLRCK
OSCLK
CS8421CS8421
DS641F6 7
Pin Name # Pin Description
VD 1 Digital Power (Input) - Digital core power supply. Typically +2.5 V.
GND 2 Ground (Input) - Ground for I/O and core logic.
Reset (Input) - When RST
RST
BYPASS 4
ILRCK 5
ISCLK 6 Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDIN pin.
SDIN 7 Se ria l Audi o In put Data Port (Input) - Audio data serial input pin.
MCLK_OUT 8
TDM_IN 9
SDOUT 10
OSCLK 11 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin.
OLRCK 12
MS_SEL 13
GND 14 Ground (Input) - Ground for I/O and core logic.
VL 15 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
SAOF 16
SAIF 17
SRC_UNLOCK 18
XTO 19 Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 20.
XTI 20
Thermal Pad -
3
reset. On initial power-up, RST
are stable in frequency and phase.
Sample Rate Converter Bypass (Input) - When BYP ASS is high, the sample-rate converter will be
bypassed, and any data input through the serial audio input port will be directly output on the serial
audio output port. When BYPASS is low, the sample rate converter will operate normally.
Serial Audio Input Left/Right Cl oc k (Input/Output) - Word-rate clock for the audio data on the
SDIN pin.
Master Clock Output (Output) - Buffered and level-shifted output for Master clock. If MCLK_OUT
is not required, this pin should be pulled high through a 47 k resistor to turn the output off. See
“Master Clock” on page 20.
Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded
when not used. See “Time Division Multiplexing (TDM) Mode” on page 21.
Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally , this pin may be
pulled low through a 47-k resistor, but must not be pulled high.
Serial Audio Input Left/Right Cl oc k (Input/Output) - Word rate clock for the audio data on the
SDOUT pin.
Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio
ports at startup and reset. See Table 1 on page 18 for settings.
Serial Audio Output Format Select (Input) - Used to select the serial audio output format at
startup and reset. See Table 3 on page 18 for format settings.
Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup
and reset. See Table 2 on page 18 for format settings.
SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and
Varispeed” on page 19.
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock” on
page 20.
Thermal Pad - Thermal relief pad for optimized heat dissipation. This pad must be electrically
connected to GND. See “Power Supply, Grounding, and PCB Layout” on page 23 for more
information.
is low, the CS8421 enters a low-power mode and all internal states are
must be held low until the power supply is stable and all input clocks
CS8421
8 DS641F6
CS8421CS8421
2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T
= 25°C.)
A
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V)
Parameter Symbol Min Nominal Max Units
Power Supply Voltage VD
VL
Ambient Operating Temperature: ‘-CZ’
‘-CNZ’
‘-DZ’
‘-EZ’
‘-ENZ’
T
A
2.38
3.14
-10
-10
-40
-40
-40
2.5
3.3 or 5.0
-
-
-
-
-
2.62
5.25
+70
+70
+85
+105
+105
V
V
°C
°C
°C
°C
°C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.)
Parameter Symbol Min Max Units
Power Supply Voltage VD
VL
Input Current, Any Pin Except Supplies (Note 1) I
Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
stg
in
in
A
-0.3
-0.3
-±10mA
-0.3 VL+0.4 V
-55 +125 °C
-65 +150 °C
3.5
6.0
V
V
Notes:
1. Transient currents of up to 100 mA will not cause SCR latch-up.
2. Numbers separated by a colon indicate input and output sample rates. For example, 48 kHz:96 kHz indicates that
Fsi = 48 khz and Fso = 96 kHz.
DS641F6 9
CS8421
PERFORMANCE SPECIFICATIONS
(XTI/XTO = 27 MHz; Input signal = 1.000 kHz, 0 dBFS, Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 32-Bits,
unless otherwise stated.)
Parameter Min Typ Max Units
Resolution 16 - 32 bits
Sample Rate with XTI = 27.000 MHz Slave
Master
Sample Rate with other XTI clocks Slave
Master
Sample Rate with ring oscillator (XTI to GND or VL, XTO floating) 12 - 96 kHz
Sample Rate Ratio - Upsampling - - 1:8
Sample Rate Ratio - Downsampling - - 7.5:1
Gain Error -0.2 - -0.02 dB
Interchannel Gain Mismatch - 0.0 - dB
Interchannel Phase Deviation - 0.0 - Degrees
Peak Idle Channel Noise Component (32-bit operation) - - -192 d B FS
Dynamic Range (20 Hz to Fso/2, 1 kHz, -60 dBFS Input)
44.1 kHz:48 kHz A-Weighted
Unweighted
44.1 kHz:192 kHz A-Weighted
Unweighted
48 kHz:44.1 kHz A-Weighted
Unweighted
48 kHz:96 kHz A-Weighted
Unweighted
96 kHz:48 kHz A-Weighted
Unweighted
192 kHz:32 kHz A-Weighted
Unweighted
Total Harmonic Distortion + Noise (20 Hz to Fso/2, 1 kHz, 0 dBFS Input)
32 kHz:48 kHz - -161 - dB
44.1 kHz:48 kHz - -171 - dB
44.1 kHz:192 kHz - -130 - dB
48 kHz:44.1 kHz - -160 - dB
48 kHz:96 kHz - -148 - dB
96 kHz:48 kHz - -168 - dB
192 kHz:32 kHz - -173 - dB
7.2
53
XTI/3750
XTI/512
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
180
177
175
172
180
177
179
176
176
173
175
172
207
211
XTI/130
XTI/128
-
-
-
-
-
-
-
-
-
-
-
-
kHz
kHz
kHz
kHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
10 DS641F6
CS8421CS8421
DIGITAL FILTER CHARACTERISTICS
Parameter Min Typ Max Units
Passband (Upsampling or Downsampling) - - 0.4535*Fso Hz
Passband Ripple - - ±0.007 dB
Stopband 0.5465*Fso - - Hz
Stopband Attenuation 125 - - dB
Group Delay SRC Mode
Bypass Mode
3. The equation for the group delay through the sample-rate converter is (56.581 / Fsi) + (55.658 / Fso). For example,
if the input sample rate is 192 kHz and the output sample rate is 96 kHz, the group delay through the sample-rate
converter is (56.581/192,000) + (55.658/96,000) =.875 milliseconds.
-
-
(Note 3)
-
-
3/Fsi
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
Parameter Symbol Min Typ Max Units
Power-Down Mode (Note 4)
Supply Current in power-down VD
(Oscillator attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
Supply Current in power-down VD
(Crystal attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
Normal Operation (Note 5)
Supply Current at 48 kHz Fsi and Fso VD
(Oscillator attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
Supply Current at 192 kHz Fsi and Fso VD
(Oscillator attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
Supply Current at 48 kHz Fsi and Fso VD
(Crystal attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
Supply Current at 192 kHz Fsi and Fso VD
(Crystal attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
50
100
200
100
1.5
4
24
2.5
4
80
8
13
24
3
7
80
4
6.5
A
A
A
A
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
s
s
4. Power Down Mode is defined as RST
attached across XTI-XTO, in which case the crystal will begin oscillating.
5. Normal operation is defined as RST
= LOW with all clocks and data lines held static, except when a crystal is
= HI.
DS641F6 11
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