Cirrus Logic CS8416 User Manual

CS8416

192 kHz Digital Audio Interface Receiver

Features

 Complete EIAJ CP1201, IEC-60958, AES3,

S/PDIF-Compatible Receiver

 +3.3 V Analog Supply (VA)

 +3.3 V Digital Supply (VD)

 +3.3 V or +5.0 V Digital Interface Supply (VL)

 8:2 S/PDIF Input MUX

 AES/SPDIF Input Pins Selectable in Hardware

Mode

 Three General Purpose Outputs (GPO) Allow

Signal Routing

 Selectable Signal Routing to GPO Pins

 S/PDIF-to-TX Inputs Selectable in Hardware

Mode

 Flexible 3-wire Serial Digital Output Port

 32 kHz to 192 kHz Sample Frequency Range

 Low-Jitter Clock Recovery

 Pin and Microcontroller Read Access to

Channel Status and User Data

 SPI™ or I²C

Control Port Software Mode and

Stand-Alone Hardware Mode

 Differential Cable Receiver

 On-Chip Channel Status Data Buffer Memories

 Auto-Detection of Compressed Audio Input

Streams

 Decodes CD Q Sub-Code

 OMCK System Clock Mode

See the General Description and Ordering Information on page 2.

RXN

RXP0 RXP1 RXP2 RXP3 RXP4 RXP5 RXP6 RXP7

http://www.cirrus.com

Receiver

8:2

MUX

AGND FILT

Clock & Data Recovery

TX Passthrough

Misc. Control

RST

RMCK

VDVA

De-emphasis

AES3 S/PDIF Decoder

Format

Detect

SDA/ CDOUT

C & U bit

Data Buffer

SCL/ CCLK

Filter

Control Port & Registers

DGND

AD1/ CDIN

AD0/ CS

OMCK

Serial Audio Output

n:3

MUX

OLRCK OSCLK SDOUT

GPO0 GPO1

AD2/GPO2

AUGUST '07

DS578F3

CS8416

General Description

The CS8416 is a monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. The CS8416 has a serial digital audio output port and comprehensive control ability through a selectable control port in Software Mode or through selectable pins in Hardware Mode. Channel status data are assembled in buffers, making read access easy. GPO pins may be assigned to route a variety of signals to output pins.

A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream.

Stand-alone operation allows systems with no microcontroller to operate the CS8416 with dedicated output pins for channel status data.

The CS8416 is available in 28-pin TSSOP, SOIC, and QFN packages in Commercial grade (-10° to +70° C) and Automotive grade (-40° to +85° C). The CDB8416 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 59 for complete ordering information.

Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems.

2 DS578F3

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6

SPECIFIED OPERATING CONDITIONS ............................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6

DC ELECTRICAL CHARACTERISTICS................................................................................................. 7

DIGITAL INPUT CHARACTERISTICS ...................................................................................................7

DIGITAL INTERFACE SPECIFICATIONS.............................................................................................. 7

SWITCHING CHARACTERISTICS ........................................................................................................ 8

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS............................................................... 9

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE .................................................. 10

SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT ............................................... 11

2. PIN DESCRIPTION - SOFTWARE MODE .......................................................................................... 12

2.1 TSSOP Pin Description ................................................................................................................. 12

2.2 QFN Pin Description ...................................................................................................................... 14

3. PIN DESCRIPTION - HARDWARE MODE ......................................................................................... 16

3.1 TSSOP Pin Description ................................................................................................................. 16

3.2 QFN Pin Description ...................................................................................................................... 18

4. TYPICAL CONNECTION DIAGRAMS ................................................................................................20

5. APPLICATIONS .................................................................................................................................. 22

5.1 Reset, Power-Down and Start-Up ................................................................................................. 22

5.2 ID Code and Revision Code .......................................................................................................... 22

5.3 Power Supply, Grounding, and PCB Layout ................................................................................. 22

6. GENERAL DESCRIPTION .................................................................................................................. 23

6.1 AES3 and S/PDIF Standards Documents ..................................................................................... 23

7. SERIAL AUDIO OUTPUT PORT ......................................................................................................... 23

7.1 Slip/Repeat Behavior ..................................................................................................................... 25

7.2 AES11 Behavior ............................................................................................................................ 26

8. S/PDIF RECEIVER .............................................................................................................................. 27

8.1 8:2 S/PDIF Input Multiplexer ......................................................................................................... 27

8.1.1 General ............................................................................................................................... 27

8.1.2 Software Mode ................................................................................................................... 27

8.1.3 Hardware Mode .................................................................................................................. 28

8.2 OMCK System Clock Mode ........................................................................................................... 28

8.3 Clock Recovery and PLL Filter ...................................................................................................... 28

9. GENERAL PURPOSE OUTPUTS ....................................................................................................... 29

10. ERROR AND STATUS REPORTING ................................................................................................30

10.1 General ........................................................................................................................................ 30

10.1.1 Software Mode ................................................................................................................. 30

10.1.2 Hardware Mode ................................................................................................................ 30

10.2 Non-Audio Detection ................................................................................................................... 31

10.2.1 Format Detection .............................................................................................................. 31

10.3 Interrupts ..................................................................................................................................... 31

11. CHANNEL STATUS AND USER-DATA HANDLING ....................................................................... 32

11.1 Software Mode ............................................................................................................................ 32

11.2 Hardware Mode ........................................................................................................................... 32

12. CONTROL PORT DESCRIPTION ..................................................................................................... 33

12.1 SPI Mode ..................................................................................................................................... 33

12.2 I²C Mode ...................................................................................................................................... 34

13. CONTROL PORT REGISTER QUICK REFERENCE ....................................................................... 35

14. CONTROL PORT REGISTER DESCRIPTIONS .............................................................................. 36

14.1 Memory Address Pointer (MAP) .................................................................................................. 36

14.2 Control0 (00h) ............................................................................................................................. 36

14.3 Control1 (01h) ............................................................................................................................. 37

CS8416

DS578F3 3

CS8416

14.4 Control2 (02h) ............................................................................................................................. 38

14.5 Control3 (03h) ............................................................................................................................. 39

14.6 Control4 (04h) ............................................................................................................................. 39

14.7 Serial Audio Data Format (05h) ................................................................................................... 40

14.8 Receiver Error Mask (06h) ......................................................................................................... 41

14.9 Interrupt Mask (07h) .................................................................................................................... 41

14.10 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h) ......................................................... 41

14.11 Receiver Channel Status (0Ah) ................................................................................................ 42

14.12 Format Detect Status (0Bh) ....................................................................................................... 42

14.13 Receiver Error (0Ch) ................................................................................................................ 43

14.14 Interrupt 1 Status (0Dh) ............................................................................................................ 44

14.15 Q-Channel Subcode (0Eh - 17h) ............................................................................................... 44

14.16 OMCK/RMCK Ratio (18h) ....................................................................................................... 45

14.17 Channel Status Registers (19h - 22h) ....................................................................................... 45

14.18 IEC61937 PC/PD Burst Preamble (23h - 26h) .......................................................................... 45

14.19 CS8416 I.D. and Version Register (7Fh) ...................................................................................45

15. HARDWARE MODE .......................................................................................................................... 46

15.1 Serial Audio Port Formats ........................................................................................................... 46

15.2 Hardware Mode Function Selection ............................................................................................ 46

15.3 Hardware Mode Equivalent Register Settings ............................................................................. 47

16. EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ................................................... 49

16.1 AES3 Receiver External Components ........................................................................................ 49

16.2 Isolating Transformer Requirements ........................................................................................... 49

17. CHANNEL STATUS BUFFER MANAGEMENT ............................................................................... 51

17.1 AES3 Channel Status (C) Bit Management ................................................................................ 51

17.2 Accessing the E Buffer ................................................................................................................ 51

17.2.1 Serial Copy Management System (SCMS) ...................................................................... 51

18. PLL FILTER ....................................................................................................................................... 53

18.1 General ........................................................................................................................................ 53

18.2 External Filter Components ......................................................................................................... 53

18.2.1 General ............................................................................................................................. 53

18.2.2 Capacitor Selection .......................................................................................................... 54

18.2.3 Circuit Board Layout ......................................................................................................... 54

18.2.4 Component Value Selection ............................................................................................. 54

18.2.5 Jitter Attenuation ............................................................................................................... 55

19. PACKAGE DIMENSIONS ................................................................................................................. 56

TSSOP THERMAL CHARACTERISTICS............................................................................................. 57

QFN THERMAL CHARACTERISTICS ................................................................................................. 58

20. ORDERING INFORMATION ............................................................................................................. 59

21. REVISION HISTORY ......................................................................................................................... 60

4 DS578F3

LIST OF FIGURES

Figure 1. Audio Port Master Mode Timing ................................................................................................... 9

Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 9

Figure 3. SPI Mode Timing ........................................................................................................................ 10

Figure 4. I²C Mode Timing ......................................................................................................................... 11

Figure 5. Typical Connection Diagram - Software Mode ........................................................................... 20

Figure 6. Typical Connection Diagram - Hardware Mode .......................................................................... 21

Figure 7. Serial Audio Output Example Formats........................................................................................ 24

Figure 8. AES3 Data Format...................................................................................................................... 25

Figure 9. Receiver Input Structure ............................................................................................................. 27

Figure 10. C/U Data Outputs...................................................................................................................... 32

Figure 11. Control Port Timing in SPI Mode .............................................................................................. 33

Figure 12. Control Port Timing, I²C Slave Mode Write ............................................................................... 34

Figure 13. Control Port Timing, I²C Slave Mode Read............................................................................... 34

Figure 14. De-Emphasis Filter Response .................................................................................................. 39

Figure 15. Hardware Mode Data Flow ....................................................................................................... 46

Figure 16. Professional Input Circuit .......................................................................................................... 49

Figure 17. Transformerless Professional Input Circuit ............................................................................... 49

Figure 18. Consumer Input Circuit ............................................................................................................. 50

Figure 19. S/PDIF MUX Input Circuit ......................................................................................................... 50

Figure 20. TTL/CMOS Input Circuit............................................................................................................ 50

Figure 21. Channel Status Data Buffer Structure....................................................................................... 52

Figure 22. Flowchart for Reading the E Buffer........................................................................................... 52

Figure 23. PLL Block Diagram ................................................................................................................... 53

Figure 24. Recommended Layout Example............................................................................................... 54

Figure 25. Jitter Attenuation Characteristics of PLL................................................................................... 55

CS8416

LIST OF TABLES

Table 1. Typical Delays by Frequency Values ........................................................................................... 26

Table 2. Clock Switching Output Clock Rates............................................................................................ 28

Table 3. GPO Pin Configurations............................................................................................................... 29

Table 4. Hardware Mode Start-Up Pin Conditions ..................................................................................... 47

Table 5. Hardware Mode Serial Audio Format Select................................................................................ 48

Table 6. External PLL Component Values ................................................................................................. 54

DS578F3 5

CS8416

1. CHARACTERISTICS AND SPECIFICATIONS

All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T

= 25°C.

SPECIFIED OPERATING CONDITIONS

(AGND, DGND = 0 V, all voltages with respect to 0 V)

Parameter Symbol Min Typ Max Units

V V V

°C

Power Supply Voltage

Ambient Operating Temperature: Commercial Grade

Automotive Grade

VA VD VL

3.13

-10

-40

3.3

3.3 or 5.0

3.46

5.25

+70 +85

ABSOLUTE MAXIMUM RATINGS

(AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.)

Parameter Symbol Min Max Units

Power Supply Voltage VA, VD,VL - 6.0 V

Input Current, Any Pin Except Supplies (Note 1) I

Input Voltage V

Ambient Operating Temperature (power applied) T

Storage Temperature T

Notes:

1. Transient currents of up to 100 mA will not cause SCR latch-up.

stg

-±10mA

-0.3 (VL) + 0.3 V

-55 125 °C

-65 150 °C

6 DS578F3

DC ELECTRICAL CHARACTERISTICS

(AGND = DGND = 0 V; all voltages with respect to 0 V.)

Parameters Symbol Min Typ Max Units

Power-Down Mode

Supply Current in power-down VA

Normal Operation (Notes 3, 4)

Supply Current at 48 kHz frame rate VA

Supply Current at 192 kHz frame rate VA

Notes:

2. Power-Down Mode is defined as RST = LO with all clocks and data lines held static.

3. Normal operation is defined as RST

4. Assumes that no inputs are floating. It is recommended that all inputs be driven high or low at all times.

(Notes 2, 4)

VD VL = 3.3 V VL = 5.0 V

= HI.

IL IL

IA ID

IL IL

IA ID

IL IL

CS8416

10 70 10 12

5.7

5.9

2.8

4.2

9.4 23

7.8

11.8

μA μA μA μA

mA mA mA mA

DIGITAL INPUT CHARACTERISTICS

(AGND = DGND = 0 V; all voltages with respect to 0 V.)

Parameters Symbol Min Typ Max Units

Input Leakage Current I

Differential Input Sensitivity, RXP[7:0] to RXN V

Input Hysteresis V

DIGITAL INTERFACE SPECIFICATIONS

(AGND = DGND = 0 V; all voltages with respect to 0 V.)

Parameters Symbol Min Max Units

High-Level Output Voltage (IOH = -3.2 mA) V

Low-Level Output Voltage (I

High-Level Input Voltage, except RXP[7:0], RXN V

Low-Level Input Voltage, except RXP[7:0], RXN V

= 3.2 mA) V

--±0.5μA

- 150 200 mVpp

0.15 - 1.0 V

(VL) - 1.0 - V

-0.5V

2.0 (VL) + 0.3 V

-0.3 0.8 V

DS578F3 7

CS8416

SWITCHING CHARACTERISTICS

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)

Parameter Symbol Min Typ Max Units

RST Pin Low Pulse Width 200 - - μS

PLL Clock Recovery Sample Rate Range 30 - 200 kHz

RMCK Output Jitter (Note 5) -200-ps RMS

RMCK Output Duty-Cycle (Note 6)

(Note 7)

RMCK/OMCK Maximum Frequency - - 50 MHz

Notes:

5. Typical RMS cycle-to-cycle jitter.

6. Duty cycle when clock is recovered from biphase encoded input.

7. Duty cycle when OMCK is switched over for output on RMCK.

45 50

50 55

55 65

% %

8 DS578F3

CS8416

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)

Parameter Symbol Min Typ Max Units

OSCLK/OLRCK Active Edge to SDOUT Output Valid (Note 8) t

dpd

Master Mode

RMCK to OSCLK active edge delay (Note 8) t

RMCK to OLRCK delay (Note 9) t

smd

lmd

OSCLK and OLRCK Duty Cycle - 50 - %

Slave Mode

OSCLK Period t

OSCLK Input Low Width t

OSCLK Input High Width t

OSCLK Active Edge to OLRCK Edge (Notes 8,9,10) t

OSCLK Edge Setup Before OSCLK Active-Edge (Notes 8,9,11) t

sckw

sckl

sckh

lrckd

lrcks

Notes:

8. In Software Mode the active edges of OSCLK are programmable.

9. In Software Mode the polarity of OLRCK is programmable.

10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK has changed.

11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.

--23ns

0-12ns

36 - - ns

14 - - ns

10 - - ns

OSCLK (output)

OLRCK (output)

RMCK

(output)

smd

lmd

OLRCK

(input)

OSCLK

(input)

SDOUT

lrckd

lrcks

sckh

sckw

sckl

dpd

Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input

DS578F3 9

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)

Parameter Symbol Min Max Unit

CCLK Clock Frequency (Note 12) f

High Time Between Transmissions t

Falling to CCLK Edge t

CCLK Low Time t

CCLK High Time t

CDIN to CCLK Rising Setup Time t

CCLK Rising to DATA Hold Time (Note 13) t

CCLK Falling to CDOUT Stable t

Rise Time of CDOUT t

Fall Time of CDOUT t

Rise Time of CCLK and CDIN (Note 14) t

Fall Time of CCLK and CDIN (Note 14) t

Notes:

12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dictated by the timing requirements necessary to access the Channel Status memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is 32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions.

13. Data must be held for sufficient time to bridge the transition time of CCLK.

14. For f

<1 MHz.

sck

csh

css

scl

sch

dsu

06.0MHz

1.0 - µs

20 - ns

66 - ns

40 - ns

15 - ns

-50ns

-25ns

-100ns

CS8416

CCLK

CDIN

CDOUT

css

dsu

scl

sch

Figure 3. SPI Mode Timing

csh

10 DS578F3

SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)

Parameter Symbol Min Max Unit

SCL Clock Frequency f

Bus Free Time Between Transmissions t

Start Condition Hold Time (prior to first clock pulse) t

Clock Low time t

Clock High Time t

Setup Time for Repeated Start Condition t

SDA Hold Time from SCL Falling (Note 15) t

SDA Setup time to SCL Rising t

Rise Time of SCL and SDA t

Fall Time SCL and SDA t

Setup Time for Stop Condition t

Notes:

15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

scl

buf

hdst

low

high

sust

hdd

sud

susp

-100kHz

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs

10 - ns

250 - ns

- 1000 ns

-300ns

4.7 - µs

CS8416

SDA

SCL

Stop Start

buf

hdst

low

high

hdd

Figure 4. I²C Mode Timing

sud

Repeated

Start

sust

hdst

Stop

susp

DS578F3 11

2. PIN DESCRIPTION - SOFTWARE MODE

2.1 TSSOP Pin Description

CS8416

RXP3 OLRCK

RXP2 OSCLK

RXP1 SDOUT

RXP0 OMCK

RXN RMCK

VA VD

AGND DGND

FILT VL

RST

RXP4 GPO1

RXP5 AD2 / GPO2

RXP6 SDA / CDOUT

RXP7 SCL / CCLK

AD0 / CS

Pin # Pin Description

821

12 17

Top-Down View

28-pin SOIC/TSSOP

Package

14 15

GPO0

AD1 / CDIN

Name

VA 6

VD 23 Digital Power (Input) – Digital core power supply. Nominally +3.3 V

VL 21 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

AGND 7

DGND 22

RST

FILT 8

RXP0 RXP1 RXP2 RXP3 RXP4 RXP5 RXP6 RXP7

Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise as possible since noise on this pin will directly affect the jitter performance of the recovered clock

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con- nected to a common ground area under the chip.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected to a common ground area under the chip.

Reset (Input) - When RST On initial power up, RST

in frequency and phase.

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground. For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on

page 53 for more information on the PLL and the external components.

4 3

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or

S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select

line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-

ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for rec-

ommended input circuits.

12 13

is low, the CS8416 enters a low power mode and all internal states are reset.

must be held low until the power supply is stable, and all input clocks are stable

12 DS578F3

CS8416

Pin # Pin Description

Name

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or

RXN 5

OMCK 25

RMCK 24

OSCLK 27 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin

OLRCK 28

SDOUT 26

SDA /

CDOUT

SCL / CCLK

AD0 / CS

AD1 /

CDIN

AD2 /

GPO2

GPO1 19 General Purpose Output 1 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.

GPO0 20 General Purpose Output 0 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.

S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In singleended operation this should be AC coupled to ground through a capacitor. See “External

AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.

System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock. OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h. “OMCK System

Clock Mode” section on page 28

Input Section Recovered Master Clock (Output) - Input section recovered master clock output from the PLL. Frequency defaults to 256x the sample rate (F

in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4 register (04h).

Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs)

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL through a 47 kΩ resistor to place the part in Software Mode.

Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out-

put data from the control port interface on the CS8416. See the “Control Port Description” section on

page 33.

Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and

out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the

“Control Port Description” section on page 33.

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416 into SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is

a chip address pin. In SPI Mode, CS

“Control Port Description” section on page 33.

Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In

SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description”

section on page 33.

General Purpose Output 2 (Output) - If using the I²C control port, this pin must be pulled high or low

through a 47 kΩ resistor. See the “Control Port Description” section on page 33 and “General Purpose

Outputs” on page 29 for GPO functions.

is used to enable the control port interface on the CS8416. See the

) and may be set to 128x through the RMCKF bit

DS578F3 13

2.2 QFN Pin Description

CS8416

RXP1

RXP2

RXP3

OLRCK

OSCLK

SDOUT

OMCK

262728

222324

RXP0

RXN

AGND

FILT

RST

RXP4

RXP5

Thermal Pad

Top-Down View

28-pin QFN Package

RXP6

RXP7

12 13 14

RMCK

DGND

GPO0

GPO1

AD2 / GPO2

AD0 / CS

AD1 / CDIN

SCL / CCLK

SDA / CDOUT

Pin # Pin Description

Name

VA 3

VD 20 Digital Power (Input) – Digital core power supply. Nominally +3.3 V

VL 18 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

AGND 4

DGND 19

RST

FILT 5

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con- nected to a common ground area under the chip.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected to a common ground area under the chip.

Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset.

On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase.

page 53 for more information on the PLL and the external components.

14 DS578F3

CS8416

Pin # Pin Description

Name

RXP0 RXP1 RXP2 RXP3 RXP4 RXP5 RXP6 RXP7

RXN 2

OMCK 22

RMCK 21

OSCLK 24 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin

OLRCK 25

SDOUT 23

SDA /

CDOUT

SCL /

CCLK

AD0 / CS

AD1 /

CDIN

AD2 /

GPO2

GPO1 16 General Purpose Output 1 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.

GPO0 17 General Purpose Output 0 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.

THERMAL

PAD

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or

S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select

line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-

ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for rec-

ommended input circuits.

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In singleended operation this should be AC coupled to ground through a capacitor. See “External

AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.

Clock Mode” section on page 28

Input Section Recovered Master Clock (Output) - Input section recovered master clock output from the PLL. Frequency defaults to 256x the sample rate (F

in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4 register (04h).

Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs)

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL through a 47 kΩ resistor to place the part in Software Mode.

put data from the control port interface on the CS8416. See the “Control Port Description” section on

page 33.

Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and

out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the

“Control Port Description” section on page 33.

a chip address pin. In SPI Mode, CS

“Control Port Description” section on page 33.

Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In

SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description”

section on page 33.

General Purpose Output 2 (Output) - If using the I²C control port, this pin must be pulled high or low

through a 47 kΩ resistor. See the “Control Port Description” section on page 33 and “General Purpose

Outputs” on page 29 for GPO functions.

- Thermal Pad - Thermal relief pad for optimized heat dissipation.

is used to enable the control port interface on the CS8416. See the

) and may be set to 128x through the RMCKF bit

DS578F3 15

3. PIN DESCRIPTION - HARDWARE MODE

3.1 TSSOP Pin Description

CS8416

RXP3 OLRCK

RXP2 OSCLK

RXP1 SDOUT

RXP0 OMCK

RXN RMCK

VA VD

AGND DGND

FILT VL

RST

RXSEL1 C

RXSEL0 U

TXSEL1 RCBL

TXSEL0 96KHZ

NV / RERR AUDIO

821

12 17

Top-Down View

28-pin SOIC/TSSOP

Package

14 15

Pin Name Pin # Pin Description

Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little

VA 6

VD 23 Digital Power (Input) – Digital core power supply. Nominally +3.3 V

VL 21 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

AGND 7

DGND 22

RST

FILT 8

RXP0 RXP1 RXP2 RXP3

RXN 5

4 3 2 1

noise as possible since noise on this pin will directly affect the jitter performance of the recovered clock

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con- nected to a common ground area under the chip.

Reset (Input) - When RST reset. On initial power up, RST are stable in frequency and phase.

on page 53 for more information on the PLL and the external components.

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left floating or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In singleended operation this should be AC coupled to ground through a capacitor. See “External

AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.

is low, the CS8416 enters a low power mode and all internal states are

must be held low until the power supply is stable, and all input clocks

16 DS578F3

CS8416

Pin Name Pin # Pin Description

System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on

OMCK 25

RMCK 24

OSCLK 27 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin

OLRCK 28

SDOUT 26

RXSEL1 RXSEL0

TXSEL1 TXSEL0

TX 20

NV/RERR 14

AUDIO 15

96KHZ 16

RCBL 17

C19

U18

10 11

12 13

OMCK after reset. When enabled, the clock signal input on this pin is automatically output through RMCK on PLL unlock. See “OMCK System Clock Mode” on page 28.

Input Section Recovered Master Clock (Output) - Input section recovered master clock output from the PLL. Frequency is 256x the sample rate (F

resistor to DGND. Frequency is 128x the sample rate (F resistor to VL.

Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs)

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to DGND through a 47 kΩ resistor to place the part in Hardware Mode.

Receiver MUX Selector (Input) - Used to select which pin, RXP[3:0], is used for the receiver input.

TX Pin MUX SELECTION (Input) - Used to select which pin, RXP[3:0], is passed to the TX pin out-

put. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs.

S/PDIF MUX Passthrough (Output) - Single-ended signal is resolved to full-rail, but is not de-jittered before it is output. Output is set by TXSEL[1:0]. This pin is also used to select the type of phase detector (PDUR) at reset. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs.

Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected by a 47 kΩ resistor to DGND. RERR is selected by a 47 kΩ resistor to VL.

Audio Channel Status Bit (Output) – When low, a valid linear PCM audio stream is indicated. See

“Non-Audio Detection” on page 31. This pin is also used to select the serial port format (SFSEL1) at

reset.

96 kHz Sample Rate Detect (Output) - If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥ 88.1 kHz. Otherwise the output is indeterminate. Also used to set the Emphasis Audio Match feature at reset.

Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block. RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames and then returns low for the remainder of the block. RCBL changes on rising edges of RMCK. Also used to set the serial audio port to master or slave at reset.

Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. Also used to select the serial port format (SFSEL0) at reset.

User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. Also used to select the frequency of RMCK to either 256*Fs or 128*Fs at reset.

) when the U pin is pulled down by a 47 kΩ

) when the U pin is pulled up by a 47 kΩ

DS578F3 17

3.2 QFN Pin Description

CS8416

RXP1

RXP2

RXP3

OLRCK

OSCLK

SDOUT

OMCK

262728

222324

RXP0

RXN

AGND

FILT

RST

RXSEL1

RXSEL0

Thermal Pad

Top-Down View

28-pin QFN Package

TXSEL1

TXSEL0

12 13 14

96KHZ

AUDIO

RCBL

RMCK

DGND

NV / RERR

Pin Name Pin # Pin Description

Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little

VA 3

VD 20 Digital Power (Input) – Digital core power supply. Nominally +3.3 V

VL 18 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

AGND 4

DGND 19

RST

FILT 5

RXP0 RXP1 RXP2 RXP3

1 28 27 26

noise as possible since noise on this pin will directly affect the jitter performance of the recovered clock

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con- nected to a common ground area under the chip.

Reset (Input) - When RST reset. On initial power up, RST

is low, the CS8416 enters a low power mode and all internal states are

must be held low until the power supply is stable, and all input clocks

are stable in frequency and phase.

on page 53 for more information on the PLL and the external components.

18 DS578F3

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