The CS8416 is a monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio data
according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. The CS8416 has a serial digital
audio output port and comprehensive control ability through a selectable control port in Software Mode or through
selectable pins in Hardware Mode. Channel status data are assembled in buffers, making read access easy. GPO
pins may be assigned to route a variety of signals to output pins.
A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream.
Stand-alone operation allows systems with no microcontroller to operate the CS8416 with dedicated output pins for
channel status data.
The CS8416 is available in 28-pin TSSOP, SOIC, and QFN packages in Commercial grade (-10° to +70° C) and
Automotive grade (-40° to +85° C). The CDB8416 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 59 for complete ordering
information.
Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems.
2DS578F3
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6
8.2 OMCK System Clock Mode ........................................................................................................... 28
8.3 Clock Recovery and PLL Filter ...................................................................................................... 28
9. GENERAL PURPOSE OUTPUTS ....................................................................................................... 29
10. ERROR AND STATUS REPORTING ................................................................................................30
10.1 General ........................................................................................................................................ 30
18.1 General ........................................................................................................................................ 53
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and T
= 25°C.
A
SPECIFIED OPERATING CONDITIONS
(AGND, DGND = 0 V, all voltages with respect to 0 V)
ParameterSymbol Min TypMax Units
V
V
V
°C
Power Supply Voltage
Ambient Operating Temperature:Commercial Grade
Automotive Grade
VA
VD
VL
T
3.13
3.13
3.13
A
-10
-40
3.3
3.3
3.3 or 5.0
-
-
3.46
3.46
5.25
+70
+85
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.)
ParameterSymbolMinMaxUnits
Power Supply VoltageVA, VD,VL-6.0V
Input Current, Any Pin Except Supplies(Note 1)I
Input VoltageV
Ambient Operating Temperature (power applied)T
Storage TemperatureT
Notes:
1. Transient currents of up to 100 mA will not cause SCR latch-up.
in
in
A
stg
-±10mA
-0.3(VL) + 0.3V
-55125°C
-65150°C
6DS578F3
DC ELECTRICAL CHARACTERISTICS
(AGND = DGND = 0 V; all voltages with respect to 0 V.)
ParametersSymbolMinTypMaxUnits
Power-Down Mode
Supply Current in power-downVA
Normal Operation (Notes 3, 4)
Supply Current at 48 kHz frame rateVA
Supply Current at 192 kHz frame rateVA
Notes:
2. Power-Down Mode is defined as RST = LO with all clocks and data lines held static.
3. Normal operation is defined as RST
4. Assumes that no inputs are floating. It is recommended that all inputs be driven high or low at all times.
(Notes 2, 4)
VD
VL = 3.3 V
VL = 5.0 V
VD
VL = 3.3 V
VL = 5.0 V
VD
VL = 3.3 V
VL = 5.0 V
= HI.
IA
ID
IL
IL
IA
ID
IL
IL
IA
ID
IL
IL
CS8416
-
-
-
-
-
-
-
-
-
-
-
-
10
70
10
12
5.7
5.9
2.8
4.2
9.4
23
7.8
11.8
-
-
-
-
-
-
-
-
-
-
-
-
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
DIGITAL INPUT CHARACTERISTICS
(AGND = DGND = 0 V; all voltages with respect to 0 V.)
ParametersSymbol Min TypMaxUnits
Input Leakage CurrentI
Differential Input Sensitivity, RXP[7:0] to RXNV
IN
TH
Input HysteresisV
DIGITAL INTERFACE SPECIFICATIONS
(AGND = DGND = 0 V; all voltages with respect to 0 V.)
ParametersSymbol Min MaxUnits
High-Level Output Voltage (IOH = -3.2 mA)V
Low-Level Output Voltage (I
High-Level Input Voltage, except RXP[7:0], RXNV
Low-Level Input Voltage, except RXP[7:0], RXNV
= 3.2 mA)V
OL
--±0.5μA
-150200mVpp
H
OH
0.15-1.0V
(VL) - 1.0-V
OL
IH
IL
-0.5V
2.0(VL) + 0.3V
-0.30.8V
DS578F37
CS8416
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
ParameterSymbolMinTypMaxUnits
RST Pin Low Pulse Width200--μS
PLL Clock Recovery Sample Rate Range30-200kHz
RMCK Output Jitter(Note 5)-200-ps RMS
RMCK Output Duty-Cycle(Note 6)
(Note 7)
RMCK/OMCK Maximum Frequency--50MHz
Notes:
5. Typical RMS cycle-to-cycle jitter.
6. Duty cycle when clock is recovered from biphase encoded input.
7. Duty cycle when OMCK is switched over for output on RMCK.
45
50
50
55
55
65
%
%
8DS578F3
CS8416
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
ParameterSymbolMinTypMaxUnits
OSCLK/OLRCK Active Edge to SDOUT Output Valid(Note 8)t
dpd
Master Mode
RMCK to OSCLK active edge delay(Note 8)t
RMCK to OLRCK delay(Note 9)t
smd
lmd
OSCLK and OLRCK Duty Cycle-50-%
Slave Mode
OSCLK Periodt
OSCLK Input Low Widtht
OSCLK Input High Widtht
OSCLK Active Edge to OLRCK Edge(Notes 8,9,10)t
OSCLK Edge Setup Before OSCLK Active-Edge (Notes 8,9,11)t
sckw
sckl
sckh
lrckd
lrcks
Notes:
8. In Software Mode the active edges of OSCLK are programmable.
9. In Software Mode the polarity of OLRCK is programmable.
10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
--23ns
0-12ns
0-12ns
36--ns
14--ns
14--ns
10--ns
10--ns
OSCLK
(output)
OLRCK
(output)
RMCK
(output)
t
smd
t
lmd
OLRCK
(input)
OSCLK
(input)
SDOUT
t
lrckd
t
lrcks
t
sckh
t
sckw
t
sckl
t
dpd
Figure 1. Audio Port Master Mode TimingFigure 2. Audio Port Slave Mode and Data Input
DS578F39
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
ParameterSymbolMinMaxUnit
CCLK Clock Frequency(Note 12)f
High Time Between Transmissionst
CS
Falling to CCLK Edget
CS
CCLK Low Timet
CCLK High Timet
CDIN to CCLK Rising Setup Timet
CCLK Rising to DATA Hold Time(Note 13)t
CCLK Falling to CDOUT Stablet
Rise Time of CDOUTt
Fall Time of CDOUTt
Rise Time of CCLK and CDIN(Note 14)t
Fall Time of CCLK and CDIN(Note 14)t
Notes:
12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dictated by the timing requirements necessary to access the Channel Status memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is
32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For f
<1 MHz.
sck
sck
csh
css
scl
sch
dsu
dh
pd
r1
f1
r2
r2
06.0MHz
1.0-µs
20-ns
66-ns
66-ns
40-ns
15-ns
-50ns
-25ns
-25ns
-100ns
-100ns
CS8416
CS
CCLK
CDIN
CDOUT
t
css
t
t
t
r2
t
dsu
scl
t
sch
f2
t
dh
Figure 3. SPI Mode Timing
t
csh
t
pd
10DS578F3
SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
ParameterSymbolMinMaxUnit
SCL Clock Frequencyf
Bus Free Time Between Transmissionst
Start Condition Hold Time (prior to first clock pulse)t
Clock Low timet
Clock High Timet
Setup Time for Repeated Start Conditiont
SDA Hold Time from SCL Falling(Note 15)t
SDA Setup time to SCL Risingt
Rise Time of SCL and SDAt
Fall Time SCL and SDAt
Setup Time for Stop Conditiont
Notes:
15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
-100kHz
4.7-µs
4.0-µs
4.7-µs
4.0-µs
4.7-µs
10-ns
250-ns
-1000ns
-300ns
4.7-µs
CS8416
SDA
SCL
StopStart
t
buf
t
hdst
t
low
t
high
t
hdd
Figure 4. I²C Mode Timing
t
sud
Repeated
Start
t
t
sust
hdst
Stop
t
f
t
r
t
susp
DS578F311
2. PIN DESCRIPTION - SOFTWARE MODE
2.1TSSOP Pin Description
CS8416
Pin
RXP3OLRCK
RXP2OSCLK
RXP1SDOUT
RXP0OMCK
RXNRMCK
VAVD
AGNDDGND
FILTVL
RST
RXP4GPO1
RXP5AD2 / GPO2
RXP6SDA / CDOUT
RXP7SCL / CCLK
AD0 / CS
Pin #Pin Description
1
2
3
4
5
6
7
28
27
26
25
24
23
22
821
9
10
11
1217
13
Top-Down View
28-pin SOIC/TSSOP
Package
20
19
18
16
1415
GPO0
AD1 / CDIN
Name
VA6
VD23Digital Power (Input) – Digital core power supply. Nominally +3.3 V
VL21Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V
AGND7
DGND22
RST
FILT8
RXP0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise
as possible since noise on this pin will directly affect the jitter performance of the recovered clock
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-
nected to a common ground area under the chip.
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected
to a common ground area under the chip.
Reset (Input) - When RST
On initial power up, RST
9
in frequency and phase.
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.
For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on
page 53 for more information on the PLL and the external components.
4
3
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
2
S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select
1
line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-
10
ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for rec-
11
ommended input circuits.
12
13
is low, the CS8416 enters a low power mode and all internal states are reset.
must be held low until the power supply is stable, and all input clocks are stable
12DS578F3
CS8416
Pin
Pin #Pin Description
Name
Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or
RXN5
OMCK25
RMCK24
OSCLK27Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin
OLRCK28
SDOUT26
SDA /
CDOUT
SCL /
CCLK
AD0 / CS
AD1 /
CDIN
AD2 /
GPO2
GPO119General Purpose Output 1 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.
GPO020General Purpose Output 0 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.
S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In singleended operation this should be AC coupled to ground through a capacitor. See “External
AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.
SystemClock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the
Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock.
OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h. “OMCK System
Clock Mode” section on page 28
InputSectionRecoveredMasterClock (Output) - Input section recovered master clock output from
the PLL. Frequency defaults to 256x the sample rate (F
in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4
register (04h).
Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT pin. Frequency will be the output sample rate (Fs)
Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL
through a 47 kΩ resistor to place the part in Software Mode.
Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data
line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out-
17
put data from the control port interface on the CS8416. See the “Control Port Description” section on
page 33.
Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and
16
out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the
“Control Port Description” section on page 33.
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416
into SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is
14
a chip address pin. In SPI Mode, CS
“Control Port Description” section on page 33.
Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In
15
SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description”
section on page 33.
General Purpose Output 2 (Output) - If using the I²C control port, this pin must be pulled high or low
18
through a 47 kΩ resistor. See the “Control Port Description” section on page 33 and “General Purpose
Outputs” on page 29 for GPO functions.
is used to enable the control port interface on the CS8416. See the
) and may be set to 128x through the RMCKF bit
s
DS578F313
2.2QFN Pin Description
CS8416
RXP1
RXP2
RXP3
OLRCK
OSCLK
SDOUT
OMCK
262728
25
222324
RXP0
RXN
VA
AGND
FILT
RST
RXP4
1
2
3
4
5
6
7
RXP5
Thermal Pad
Top-Down View
28-pin QFN Package
98
10
11
RXP6
RXP7
121314
RMCK
21
VD
20
DGND
19
VL
18
GPO0
17
GPO1
16
AD2 / GPO2
15
AD0 / CS
AD1 / CDIN
SCL / CCLK
SDA / CDOUT
Pin
Pin #Pin Description
Name
VA3
VD20Digital Power (Input) – Digital core power supply. Nominally +3.3 V
VL18Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V
AGND4
DGND19
RST
FILT5
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise
as possible since noise on this pin will directly affect the jitter performance of the recovered clock
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-
nected to a common ground area under the chip.
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected
to a common ground area under the chip.
Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset.
6
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase.
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.
For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on
page 53 for more information on the PLL and the external components.
14DS578F3
CS8416
Pin
Pin #Pin Description
Name
RXP0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
RXN2
OMCK22
RMCK21
OSCLK24Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin
OLRCK25
SDOUT23
SDA /
CDOUT
SCL /
CCLK
AD0 / CS
AD1 /
CDIN
AD2 /
GPO2
GPO116General Purpose Output 1 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.
GPO017General Purpose Output 0 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.
THERMAL
PAD
1
28
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
27
S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select
26
line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-
7
ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for rec-
8
ommended input circuits.
9
10
Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or
S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In singleended operation this should be AC coupled to ground through a capacitor. See “External
AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.
SystemClock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the
Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock.
OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h. “OMCK System
Clock Mode” section on page 28
InputSectionRecoveredMasterClock (Output) - Input section recovered master clock output from
the PLL. Frequency defaults to 256x the sample rate (F
in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4
register (04h).
Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT pin. Frequency will be the output sample rate (Fs)
Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL
through a 47 kΩ resistor to place the part in Software Mode.
Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data
line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out-
14
put data from the control port interface on the CS8416. See the “Control Port Description” section on
page 33.
Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and
13
out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the
“Control Port Description” section on page 33.
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416
into SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is
11
a chip address pin. In SPI Mode, CS
“Control Port Description” section on page 33.
Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In
12
SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description”
section on page 33.
General Purpose Output 2 (Output) - If using the I²C control port, this pin must be pulled high or low
15
through a 47 kΩ resistor. See the “Control Port Description” section on page 33 and “General Purpose
Outputs” on page 29 for GPO functions.
-Thermal Pad - Thermal relief pad for optimized heat dissipation.
is used to enable the control port interface on the CS8416. See the
) and may be set to 128x through the RMCKF bit
s
DS578F315
3. PIN DESCRIPTION - HARDWARE MODE
3.1TSSOP Pin Description
CS8416
RXP3OLRCK
RXP2OSCLK
RXP1SDOUT
RXP0OMCK
RXNRMCK
VAVD
AGNDDGND
FILTVL
RST
RXSEL1C
RXSEL0U
TXSEL1RCBL
TXSEL096KHZ
NV / RERRAUDIO
1
2
3
4
5
6
7
28
27
26
25
24
23
22
821
9
10
11
1217
13
Top-Down View
28-pin SOIC/TSSOP
Package
20
19
18
16
TX
1415
Pin NamePin #Pin Description
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little
VA6
VD23Digital Power (Input) – Digital core power supply. Nominally +3.3 V
VL21Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V
AGND7
DGND22
RST
FILT8
RXP0
RXP1
RXP2
RXP3
RXN5
9
4
3
2
1
noise as possible since noise on this pin will directly affect the jitter performance of the recovered
clock
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-
nected to a common ground area under the chip.
Reset (Input) - When RST
reset. On initial power up, RST
are stable in frequency and phase.
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog
ground.
For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter”
on page 53 for more information on the PLL and the external components.
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The
select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left
floating or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49
for recommended input circuits.
Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or
S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In singleended operation this should be AC coupled to ground through a capacitor. See “External
AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.
is low, the CS8416 enters a low power mode and all internal states are
must be held low until the power supply is stable, and all input clocks
16DS578F3
CS8416
Pin NamePin #Pin Description
System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on
OMCK25
RMCK24
OSCLK27Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin
OLRCK28
SDOUT26
RXSEL1
RXSEL0
TXSEL1
TXSEL0
TX20
NV/RERR14
AUDIO15
96KHZ16
RCBL17
C19
U18
10
11
12
13
OMCK after reset. When enabled, the clock signal input on this pin is automatically output through
RMCK on PLL unlock. See “OMCK System Clock Mode” on page 28.
InputSectionRecoveredMasterClock (Output) - Input section recovered master clock output
from the PLL. Frequency is 256x the sample rate (F
resistor to DGND. Frequency is 128x the sample rate (F
resistor to VL.
Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT pin. Frequency will be the output sample rate (Fs)
Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to
DGND through a 47 kΩ resistor to place the part in Hardware Mode.
Receiver MUX Selector (Input) - Used to select which pin, RXP[3:0], is used for the receiver input.
TX Pin MUX SELECTION (Input) - Used to select which pin, RXP[3:0], is passed to the TX pin out-
put. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs.
S/PDIF MUX Passthrough (Output) - Single-ended signal is resolved to full-rail, but is not de-jittered
before it is output. Output is set by TXSEL[1:0]. This pin is also used to select the type of phase
detector (PDUR) at reset. If TX passthrough is not used, the user should set it to output one of the
unused receiver inputs.
Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected
by a 47 kΩ resistor to DGND. RERR is selected by a 47 kΩ resistor to VL.
Audio Channel Status Bit (Output) – When low, a valid linear PCM audio stream is indicated. See
“Non-Audio Detection” on page 31. This pin is also used to select the serial port format (SFSEL1) at
reset.
96 kHz Sample Rate Detect (Output) - If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a
“1” if the sample rate is ≥ 88.1 kHz. Otherwise the output is indeterminate. Also used to set the
Emphasis Audio Match feature at reset.
Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block.
RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames and then
returns low for the remainder of the block. RCBL changes on rising edges of RMCK. Also used to set
the serial audio port to master or slave at reset.
Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the
rising and falling edges of OLRCK. Also used to select the serial port format (SFSEL0) at reset.
User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling
edges of OLRCK. Also used to select the frequency of RMCK to either 256*Fs or 128*Fs at reset.
) when the U pin is pulled down by a 47 kΩ
s
) when the U pin is pulled up by a 47 kΩ
s
DS578F317
3.2QFN Pin Description
CS8416
RXP1
RXP2
RXP3
OLRCK
OSCLK
SDOUT
OMCK
262728
25
222324
RXP0
RXN
VA
AGND
FILT
RST
RXSEL1
1
2
3
4
5
6
7
RXSEL0
Thermal Pad
Top-Down View
28-pin QFN Package
98
10
11
TXSEL1
TXSEL0
121314
96KHZ
AUDIO
RCBL
21
20
19
18
17
16
15
RMCK
VD
DGND
VL
TX
C
U
NV / RERR
Pin NamePin #Pin Description
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little
VA3
VD20Digital Power (Input) – Digital core power supply. Nominally +3.3 V
VL18Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V
AGND4
DGND19
RST
6
FILT5
RXP0
RXP1
RXP2
RXP3
1
28
27
26
noise as possible since noise on this pin will directly affect the jitter performance of the recovered
clock
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-
nected to a common ground area under the chip.
Reset (Input) - When RST
reset. On initial power up, RST
is low, the CS8416 enters a low power mode and all internal states are
must be held low until the power supply is stable, and all input clocks
are stable in frequency and phase.
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog
ground.
For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter”
on page 53 for more information on the PLL and the external components.
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The
select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left
floating or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49
for recommended input circuits.
18DS578F3
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