Cirrus Logic CS8130 User Manual

CS8130

http://www.cirrus.com

MAR ‘06

DS134F1-B1

http://www.cirrus.com

MAR ‘06

DS134F1-B1

http://www.cirrus.com

MAR ‘06

DS134F1-B1

11/6/97

CS8130 Revision G Addendum

Multi-Standard Infrared Transceiver (DS134F1, SEP ‘05)

The following items represent perman ent changes to the sp ecificatio n of the CS8130 IR tra ns ceiver.

1) The Silicon Rev ision Register (Register 28) rea ds 0010, indicating rev G silicon.

2) The default rec eive sensitivity sett ing is changed to 00011 (Register 6 resets to 0011).

3) Oscillator low power m ode is now the default condition aft er reset (Register 21 resets to 010 0).

4) The BLKR bit (Register 4, bit D2) blocks the RXD output data during those periods when the transmit LEDs are on. This pr event s the UAR T/system readi ng the transmi tted da ta. The re-ena ble sign al for

the receiver is delayed by 8 µs from when the LEDs are turned off. Se t to 1 to block RXD dat a, set to 0 to allow RXD data throu gh during transmission. Th is bit goes to 0 upon RESET.

5) An additional control bit was added which causes the CS8130 receiver to ignore the falling edge of the IR pulse. This bit is called ENPOS, and it is bit D2 of Register #7. ENPOS is normally 1, which causes the falling edge to be ignore d. This results in grea ter range in IrDA and high-frequenc y ASK (Sharp 500 kHz) modes. ENPOS should be set to 0 for low -fre que ncy amplitude modulated m ode s.

6) For IrDA/HP-SIR pulse widt h mo des, two additional con tr ol bi ts have been added: a. The THIN bit (Register 7, bit D1) allows the minimum acceptable pulse width to be reduced from

1 µs to 0.5 µs when se t t o 1. T his bit has effect only when the receiver is p rogrammed to mode 1a (fixed 1.6 µs pulses onl y) or 1c (receive 1.6 µs to 3/16 of a bi t cell pulses). This bit re sets to 0.

b. The WIDE bit (Reg ister 1, Bit D2) e xpands the maximum allow able pul se width t o 9/16 of a bit

cell when set to 1. This bit has effect only when the receiver is set to mode 1a (fixed 1.6 µs pulses only).

For normal IrDA operation, it is recommended that THIN be set to 0 and WIDE be set to 1. Under these conditions, the qualification boundaries for receiver mode 1c (receive 1.6 µs to 3/16 of a bit cell pulses) are ident ical t o the qu alif icatio n boun darie s for re ceiv er mode 1a ( fixed 1.6 µs pulse s only) . Th is bit resets to 1.

7) A TV remote receive mode hesitate bi t has been adde d (Register 1, Bi t D3). When th is bit is set to 0, the RXD pin will remain high until the first valid IR signal is detected. At that time, the RXD pin will output serial data at the specified baud rate until the receiver is disabled (Register 0, bit D1). If this bit is set to 1, the RXD pin will im mediately and continuously output data. This bit rese ts to 0.

8) The ASK transmit carrier freque nc y form ul a ha s ch ang ed : MD=(3.6864E6/FR)-2 , where MD is the Modulator Div ide r Value and FR is the desired modulation frequency (Registe rs 10 & 11) . The RESET de fau lt value for MD is now 5, yiel ding a de faul t carr ier

Cirrus Logic, Inc.

P.O. Box 17847, Austin, Texas 78760

http://www.cirrus.com

(512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

(All Rights Reserv ed)

SEP ‘05

DS134PP2-B

DS134F1-B

NOV ‘97

CS8130

frequency of 527 kHz .

9) ASK Receive Choices - valid incoming frequency range (with RATS = 0 and MD = 5) is 431 kHz to 609 kHz.

10) RATS register control of receive data frequency window period is now: T(min) ~= [(2*M D)+ 3+RATS]*135ns T(max) ~= [(2*MD)+3+(6*(RATS+1))]*135ns

11)Clarification: the IrDA/HP-SIR baud rate can be a s low as 12 00 bps.

12)Specifications in the following tables replace those found in the SEP ’05 CS8130 data sheet

(DS134F1).

POWER SUPPLY SPECIFICATIONS (T

Logic 1 = V+, Note 1)

Parameter Symbol Min Typ Max Unit

Power Supply Voltage 2.7 3.0 5.5 V Power Supply Current - All func tions enabled (Note 2) - 2.7 3.3 mA Power Supply Current - All functions disabled (Note 3) - 0.3 1 µA Power Supply Current - Receiver only enabl ed (Note 2) - 2.0 2.8 mA Power Supply Current - Transmit only enabled (Note 4) - 0.7 1.5 mA Oscillator Power Supply Current low power mode:

normal power mode:

Data & State Retention Supply Voltage 2 - - V

Notes: 1. Power supply current specifications are with the supply at 3.0 V. For ap proximate consumption at

+5.0 V, multiply the above currents by 1.667.

2. Oscillator in l ow power mode; does not include LED current. Subtract oscillator current i f using an external clock to run the CS8130.

3. Floating digital inputs will not cause the power supply to increase beyond the specification.

4. Does not include LED current, does incl ude oscillator current in low power mode.

= 25 °C; V+ = 3.0 V, Digital Input Leve ls: Logic 0 = 0 V,

0.45

1.3

2.2

mA mA

2 DS134F1-B

2 DS134F1-B1

2 DS134PP2-B

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