Cirrus Logic CS5581 User Manual

3/25/08

15:11

±2.5 V / 5 V, 200 kSps, 16-bit, High-throughput

Features & Description

 Single-ended Analog Input
 On-chip Buffers for High Input Impedance
 Conversion Time = 5 µS
 Settles in One Conversion
 Linearity Error = 0.0008%
 Signal-to-Noise = 80 dB
 S/(N + D) = 80 dB
 DNL = ±0.1 LSB Max.
 Simple three/four-wire serial interface
 Power Supply Configurations:

- Analog: +5V/GND; IO: +1.8V to +3.3V

- Analog: ±2.5V; IO: +1.8V to +3.3V

 Power Consumption:

- ADC Input Buffers On: 85 mW

- ADC Input Buffers Off: 60 mW

General Description

The CS5581 is a single-channel, 16-bit analog-to-digital
converter capable of 200 kSps conversion rate. The input
accepts a single-ended analog input signal. On -chip buff­ers provide high input impedance for both the AIN input
and the VREF+ input. This significantly reduces the drive
requirements of signal sources and reduces errors due to
source impedances. The CS5581 is a delta-sigma convert­er capable of switching multiple input channels at a high
rate with no loss in throughput. The ADC uses a low-laten­cy digital filter architecture. The filter is designed for fast
settling and settles to full accuracy in one conversion. The
converter's 16-bit data output is in serial format, with the
serial port acting as either a master or a slave. The convert­er is designed to support bipolar, ground-referenced
signals when operated from ±2.5V analog supplies.

The converter can operate from an analog supply of 0-5V
or from ±2.5V. The digital interface supports standard logic
operating from 1.8, 2.5, or 3.3 V.

ORDERING INFORMATION:

See Ordering Information on page 32.

CS5581

∆Σ

ADC

V1+

VREF+

VREF-

AIN

ACOM

BUFEN

V1-

V2+

ADC

V2-

Preliminary Product Information

http://www.cirrus.com

VL

CS5581

SMODE
CS

DIGITAL

FILTER

LOGIC

OSC/CLOCK

GENERATOR

TST

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright © Cirrus Logic, Inc. 2008

(All Rights Reserved)

DIGITAL CONTROL

DCR

VLR

SERIAL

INTERFACE

VLR2

VLR3

SCLK

SDO
RDY

RST
CONV

BP/UP
MCLK

MAR ‘08

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TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DIGITAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

GUARANTEED LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.1 Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.3 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.4 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.5 Output Coding Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.6 Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7 AIN & VREF Sampling Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8 Converter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.9 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.10 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.10.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.10.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.11 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.12 Using the CS5581 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.13 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4. PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . .32

8. REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

CS5581

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LIST OF FIGURES

Figure 1. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. SSC Mode - Read Timing, CS falling after RDY falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. SEC Mode - Continuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. SEC Mode - Discontinuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 6. CS5581 Configured Using ±2.5V Analog Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. CS5581 Configured for Unipolar Measurement Using a Single 5V Analog Supply. . . . 18

Figure 8. CS5581 Configured for Bipolar Measurement Using a Single 5V Analog Supply. . . . . 19

Figure 9. CS5581 DNL Plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. CS5581 DNL Error Plot with DNL Histogram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Spectral Performance, 0 dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Spectral Performance, -6 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13. Spectral Performance, -12 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14. Spectral Performance, -80 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15. Spectral Performance, -100 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 16. Spectral Plot of Noise with Shorted Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 17. Noise Histogram (4096 Conversions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 18. CS5581 Spectral Response (DC to fs/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 19. CS5581 Spectral Response (DC to 20 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 20. CS5581 Spectral Response (DC to 8fs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 21. Simple Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 22. More Complex Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CS5581

LIST OF TABLES

Table 1. Output Coding, Two’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2. Output Coding, Offset Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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1. CHARACTERISTICS AND SPECIFICATIONS

• Min / Max characteristics and specifications are guaranteed over the specified operating conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and T

• VLR = 0 V. All voltages measured with respect to 0 V.

A

CS5581

= 25°C.

ANALOG CHARACTERISTICS T

±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL, unless other­wise stated; BUFEN = V1+ unless otherwise stated. Connected per Figure 6. Bipolar mode unless otherwise
stated.

Parameter Min Typ Max Unit

Accuracy

Linearity Error - 0.0008 - ±%FS
Differential Linearity Error (Note 1) - - ±0.1 LSB

Positive Full-scale Error - 1.0 - %FS
Negative Full-scale Error - 1.0 - %FS
Full-scale Drift (Note 2, 3) - ±1 - LSB
Bipolar Offset (Note 3) - ±15 - LSB
Bipolar Offset Drift (Note 2, 3) - ±1 - LSB
Noise - 140 - µVrms

Dynamic Performance

Peak Harmonic or Spurious Noise 1 kHz, -0.5 dB Input

Total Harmonic Distortion 1 kHz, -0.5 dB Input - -95 -82 dB
Signal-to-Noise 77 80 - dB

= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V,

A

12 kHz, -0.5 dB Input--

-96

-96

-

-

dB
dB

16

16
16
16

S/(N + D) Ratio -0.5 dB Input, 1 kHz

-60 dB Input, 1 kHz--

-3 dB Input Bandwidth (Note 4) - 168 - kHz

1. No missing codes is guaranteed at 16 bits resolution over the specified temperature range.

2. Total drift over specified temperature range after reset at power-up, at 25º C.

3. One LSB is equivalent to VREF ÷ 2

4. Scales with MCLK.

4 DS796PP1

16

or 4.096 ÷ 65536 = 62.5 µV.

80
21

-

-

dB
dB

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CS5581

ANALOG CHARACTERISTICS (CONTINUED) T

V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL,
unless otherwise stated; BUFEN = V1+ unless otherwise stated. Connected per Figure 6.

Parameter Min Typ Max Unit

Analog Input

Analog Input Range Unipolar

Input Capacitance - 10 - pF
CVF Current (Note 5) AIN Buffer On (BUFEN = V+)

AIN Buffer Off (BUFEN = V-)

Voltage Reference Input

Voltage Reference Input Range
(VREF+) – (VREF-) (Note 6) 2.4 4.096

Input Capacitance - 10 - pF
CVF Current VREF+ Buffer On (BUFEN = V+)

VREF+ Buffer Off (BUFEN = V-)

Power Supplies

DC Power Supply Currents I

Power Consumption Normal Operation Buffers On

Power Supply Rejection (Note 7) V1+ , V2+ Supplies

V1-, V2- Supplies

= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- =

A

0 to +VREF / 2

Bipolar

ACOM

VREF-

V1

I

V2

I

VL

Buffers Off

-

-

-

-

-

-

-

-

-

-

-

-

-

±VREF / 2

600
130
130

3
1
1

-

-

-

85
60

80
80

101

-

-

-

4.2

-

-

-

18

1.8

0.6

80

-

-

V
V

nA

µA
µA

V

µA
mA
mA

mA
mA
mA

mW
mW

dB

dB

5. Measured using an input signal of 1 V DC.

6. For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer.

7. Tested with 100 mVP-P on any supply up to 1 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at
the same voltage potential.

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SWITCHING CHARACTERISTICS

TA= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter Symbol Min Typ Max Unit

CS5581

Master Clock Frequency Internal Oscillator

External Clock

Master Clock Duty Cycle 40 - 60 %

Reset

RST

Low Time (Note 8) t
rising to RDY falling Internal Oscillator

RST

External Clock

Conversion

CONV

Pulse Width t

setup to CONV falling (Note 9) t

BP/UP

low to start of conversion t

CONV
Perform Single Conversion (CONV
Conversion Time (Note 10)

Start of Conversion to RDY

8. Reset must not be released until the power supplies and the voltage reference are within specification.

9. BP/UP

10. If CONV is held low continuously, conversions occur every 80 MCLK cycles.

can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.

is tied to CONV, conversions will occur every 82 MCLKs.

If RDY
If CONV is operated asynchronously to MCLK, a conversion may take up to 84 MCLKs.
RDY falls at the end of conversion.

high before RDY falling) t

falling t

XIN

f

clk

res

t

wup

cpw

scn
scn
bus

buh

12

0.5

1--µs

-

-

4--MCLKs
0--ns

--2MCLKs

20 - - MCLKs

- - 84 MCLKs

14
16

120

1536

16

16.2

-

-

MHz
MHz

µs

MCLKs

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SWITCHING CHARACTERISTICS (CONTINUED)

TA= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter Symbol Min Typ Max Unit

Serial Port Timing in SSC Mode (SMODE = VL)

RDY

falling to MSB stable t
Data hold time after SCLK rising t
Serial Clock (Out) Pulse Width (low)

(Note 11, 12) Pulse Width (high)

rising after last SCLK rising t

RDY

11 . SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down

resistors.

12. SCLK = MCLK/2.

1
2

t

3

t

4
5

CS5581

--2-MCLKs

-10-ns

50
50

-8-MCLKs

-

-

-

-

ns
ns

MCLK

RDY

SCLK(o)

SDO

CS

t

1

t

2

MSB MSB–1

t

3

t

4

LSB

LSB+1

Figure 1. SSC Mode - Read Timing, CS remaining low (Not to Scale)

t

5

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SWITCHING CHARACTERISTICS (CONTINUED)

TA= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter Symbol Min Typ Max Unit

Serial Port Timing in SSC Mode (SMODE = VL)

Data hold time after SCLK rising t
Serial Clock (Out) Pulse Width (low)

(Note 13, 14) Pulse Width (high)
RDY

rising after last SCLK rising t

falling to MSB stable t

CS
First SCLK rising after CS

hold time (low) after SCLK rising t

CS
SCLK, SDO tristate after CS

13. SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down
resistors.

14. SCLK = MCLK/2.

falling t

rising t

t
t

10
11
12
13
14

7
8

9

CS5581

-10-ns

50
50

-8-MCLKs

-10-ns

-8-MCLKs

10 - - ns

-5-ns

-

-

-

-

ns
ns

MCLK

RDY

SCLK(o)

SDO

CS

t

13

t

12

t

11

MSB MSB–1

t

7

t

8

t

9

LSB+1

LSB

t

14

Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale)

t

10

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SWITCHING CHARACTERISTICS (CONTINUED)

TA= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter Symbol Min Typ Max Unit

Serial Port Timing in SEC Mode (SMODE = VLR)

SCLK(in) Pulse Width (High)
SCLK(in) Pulse Width (Low)
CS

hold time (high) after RDY falling t
hold time (high) after SCLK rising t

CS
CS

low to SDO out of Hi-Z (Note 15) t
Data hold time after SCLK rising t
Data setup time before SCLK rising t

CS

hold time (low) after SCLK rising

-

-

15
16
17
18
19

t

20

CS5581

30 - - ns
30 - - ns
10 - - ns

10 - - ns

-10-ns

-10-ns

10 - - ns

1

10 - ns

SCLK

10

RDY

rising after SCLK falling t

15. SDO will be high impedance when CS is high. In some systems SDO may require a pull-down resistor.

MCLK

RDY

t

15

CS

t

16

SCLK(i)

t

17

t

t

19

18

SDO

21

-10-ns

t

21

t

20

LSBMSB

Figure 3. SEC Mode - Continuous SCLK Read Timing (Not to Scale)

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MCLK

SCLK(i)

RDY

CS

SDO

3/25/08

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t

21

t

15

t

17

t

t

19

18

t

20

LSBMSB

CS5581

Figure 4. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale)

DIGITAL CHARACTERISTICS

= TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V

T

A

Parameter Symbol Min Typ Max Unit

Input Leakage Current I
Digital Input Pin Capacitance C
Digital Output Pin Capacitance C

in

in

out

--2µA

-3-pF

-3-pF

10 DS796PP1