Cirrus Logic CS5566 User Manual

5/4/09

AIN+
AIN-

CS

SCLK

SMODE

VREF+

VREF-

RDY

OSC/CLOCK

GENERATOR

CONV
BP/UP

DIGITAL CONTROL

SERIAL

INTERFACE

ADC

DIGITAL

FILTER

LOGIC

VL

MCLK

SDO

RST

SLEEP

TST

DCR

V1-

V2-

BUFEN

V2+

V1+

CS5566

VLR

VLR2

CS5566

±2.5 V / 5 V, 5 kSps, 24-bit

Features & Description

 Differential Analog Input
 On-chip Buffers for High Input Impedance
 Conversion Time = 200 μS
 Settles in One Conversion
 Linearity Error = 0.0005%
 Signal-to-Noise = 110 dB
 24 Bits, No Missing Codes
 Simple three/four-wire serial interface
 Power Supply Configurations:

- Analog: +5V/GND; IO: +1.8V to +3.3V

- Analog: ±2.5V; IO: +1.8V to +3.3V

 Power Consumption: 20 mW @ 5 kSps

ΔΣ

ADC

General Description

The CS5566 is a single-channel, 24-bit analog-to-digital
converter capable of 5 kSps conversion rate. The input
accepts a fully differential analog input signal. On-chip
buffers provide high input impedance for both the AIN in­puts and the VREF+ input. This significantly reduces the
drive requirements of signal sources and reduces errors
due to source impedances. The CS5566 is a delta-sigma
converter capable of switching multiple input channels at
a high rate with no loss in throughput. The ADC uses a
low-latency digital filter architecture. The filter is designed
for fast settling and settles to full accuracy in one conv er­sion. The converter's 24-bit data output is in serial form,
with the serial port acting as either a master or a slave. The
converter is designed to support bipolar, ground-refer­enced signals when operated from ±2.5V analog supplies.

The converter can operate from an analog supply of 0-5V
or from ±2.5V. The digital interface supports standard log­ic operating from 1.8, 2.5, or 3.3 V.

Preliminary Product Information

http://www.cirrus.com

ORDERING INFORMATION:

See Ordering Information on page 30.

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2009

(All Rights Reserved)

MAY ‘09

DS806PP2

5/4/09

CS5566

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

DIGITAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

DIGITAL FILTER CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

GUARANTEED LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.1 Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.5 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 Output Coding Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7 Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.8 AIN & VREF Sampling Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9 Converter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.10 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.11 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.11.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.11.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.12 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.13 Using the CS5566 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.14 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4. PIN DESCRIPTIONS 26

5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . .30

8. REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2 DS806PP2

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CS5566

LIST OF FIGURES

Figure 1. Converter Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. SSC Mode - Read Timing, CS falling after RDY falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. SEC Mode - Continuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. SEC Mode - Discontinuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. Power Consumption vs. Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 8. CS5566 Configured Using ±2.5V Analog Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. CS5566 Configured Using a Single 5V Analog Supply . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. CS5566 DNL Plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Spectral Performance, 0 dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Spectral Performance, -6 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13. Spectral Performance, -12 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14. Spectral Performance, -20 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15. Spectral Performance, -80 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 16. Spectral Performance, -120 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 17. Spectral Performance, -130 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19. Noise Histogram (4096 Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 18. Spectral Plot of Noise with Shorted Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 20. Digital Filter Response (DC to 2.5 kHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LIST OF TABLES

Table 1. Output Coding, Two’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 2. Output Coding, Offset Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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CS5566

1. CHARACTERISTICS AND SPECIFICATIONS

• Min / Max characteristics and specifications are guaranteed over the specified operating conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and T

• VLR = 0 V. All voltages with respect to 0 V.

= 25°C.

A

ANALOG CHARACTERISTICS T

±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL. BUFEN = V1+
unless otherwise stated. Connected per Figure 8. Bipolar mode unless otherwise stated.

Parameter Min Typ Max Unit

Accuracy

Linearity Error - 0.0005 - ±%FS
Differential Linearity Error (Note 1) - ±0.1 - LSB

Positive Full-scale Error - 1.0 - %FS
Negative Full-scale Error - 1.0 - %FS

Full-scale Drift (Note 2) - 1 - PPM / °C
Bipolar Offset (Note 2) - ±500 - LSB

Bipolar Offset Drift (Note 2) - 1 - LSB / °C
Noise - 9.5 - μVrms

Dynamic Performance

Peak Harmonic or Spurious Noise 200 Hz, -0.5 dB Input - -115 - dB
Total Harmonic Distortion 200 Hz, -0.5 dB Input - -110 -100 dB
Signal-to-Noise 108 110 - dB
S/(N + D) Ratio -0.5 dB Input, 200 Hz

-3 dB Input Bandwidth (Note 3) - 21 - kHz

Analog Input

Analog Input Range (Differential) Unipolar

Input Capacitance - 10 - pF
CVF Current (Note 4) AIN Buffer On (BUFEN = V+)

Common Mode Rejection Ratio (DC to 2 kHz) -100 -110 - dB

= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V,

A

-60 dB Input, 200 Hz--

Bipolar

AIN Buffer Off (BUFEN = V-)--

109

50

0 to +VREF

±VREF

600
130

-

-

-

-

24

24

dB
dB

V
V

nA
μA

1. No missing codes is guaranteed at 24 bits resolution over the specified temperature range.

2. One LSB is equivalent to (2 x VREF) ÷ 2

3. Scales with MCLK.

4. Measured using an input signal of 1 V DC.

4 DS806PP2

24

or (2 x 4.096) ÷ 16, 777,216 = 488 n V.

5/4/09

CS5566

ANALOG CHARACTERISTICS (CONTINUED) T

= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- =

A

V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL.;
BUFEN = V1+ unless otherwise stated. Connected per Figure 8.

Parameter Min Typ Max Unit

Voltage Reference Input

Voltage Reference Input Range
(VREF+) – (VREF-) (Note 5) 2.4 4.096

4.2

V
Input Capacitance - 10 - pF
CVF Current VREF+ Buffer On (BUFEN = V+)

VREF+ Buffer Off (BUFEN = V-)

VREF-

-

-

-

3
1
1

-

-

-

μA
mA
mA

Power Supplies

Average DC Power Supply Currents (Note 6) I

Peak DC Power Supply Currents (Note 6) I

V1

I

V2

I

VL
V1

I

V2

I

VL

Average Power Consumption Normal Operation Buffers On

(Note 6) Buffers Off

Sleep (SLEEP = 0)

Power Supply Rejection (Note 7) V1+ , V2+ Supplies

V1-, V2- Supplies

75
75

-

-

-

-

-

-

-

-

-

20
15

6

85
85

-

-

-

-

-

-

5

0.6

0.4
9

1.2

280

-

-

-

-

-

mA
mA
mA

mA
mA

μA

mW
mW
mW

dB
dB

5. For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer.

6. Specification is for MCLK = 8MHz and 5 kSps conversion rate. MCLK frequency and conversion rate affect power consumption.
See Section 3.2 Power Consumption for more details.

7. Tested with 100 mVP-P on any supply up to 2 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at
the same voltage potential.

DS806PP2 5

5/4/09

1182 - 1186 MCLKs

Converter

Status

CONVERT

RDY

IDLEIDLE CONVERT

SDO

ACTIVE

t

bus

354 + 64 MCLKs

1600 - 1604 MCLKs

SWITCHING CHARACTERISTICS

TA= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter Symbol Min Typ Max Unit

CS5566

Master Clock Frequency Internal Oscillator

External Clock

XIN

f

clk

6

0.5

7
8

8

8.1

MHz
MHz

Master Clock Duty Cycle 40 - 60 %

Reset

RST

Low Time t
rising to RDY falling Internal Oscillator

RST

External Clock

t

wup

res

1--µs

-

-

240

3084

-

-

µs

MCLKs

Conversion

CONV

Pulse Width t

setup to CONV falling (Note 8) t

BP/UP

low to start of conversion t

CONV
Perform Single Conversion (CONV

high before RDY falling) t

cpw

scn
scn
bus

4--MCLKs
0--ns

- 1182 1186 MCLKs

20 - - MCLKs

Conversion Time (Note 9)

Start of Conversion to RDY

falling t

buh

- - 1604 MCLKs

Sleep Mode

SLEEP
SLEEP

8. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.

9. If CONV
If RDY is tied to CONV, conversions will occur every 1602 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 1604 MCLKs.
RDY falls at the end of conversion.

10. RDY

is held low continuously, conversions occur every 1600 MCLK cycles.

will fall when the device is fully operational when coming out of sleep mode.

low to low-power state
high to device active (Note 10)

t
t

con
con

-

-

50

3083

-

-

µs

MCLKs

Figure 1. Converter Status (Not to scale)

6 DS806PP2

5/4/09

MCLK

RDY

SCLK(o)

SDO

MSB MSB–1

LSB

LSB+1

CS

t

1

t

2

t

3

t

4

t

5

Figure 2. SSC Mode - Read Timing, CS remaining low (Not to Scale)

SWITCHING CHARACTERISTICS (CONTINUED)

TA=-40to+85°C;V1+=V2+=+2.5V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter Symbol Min Typ Max Unit

Serial Port Timing in SSC Mode (SMODE = VL)

RDY falling to MSB stable t
Data hold time after SCLK rising t
Serial Clock (Out) Pulse Width (low)

(Note 11, 12) Pulse Width (high)

rising after last SCLK rising t

RDY

11. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resistor.

12. SCLK = MCLK/2.

1
2

t

3

t

4
5

CS5566

--2-MCLKs

-10-ns

100
100

-8-MCLKs

-

-

-

-

ns
ns

DS806PP2 7

5/4/09

MCLK

RDY

SCLK(o)

SDO

CS

t

12

t

8

t

13

t

9

t

7

t

11

MSB MSB–1

LSB

LSB+1

t

14

t

10

Figure 3. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale)

SWITCHING CHARACTERISTICS (CONTINUED)

TA=-40to+85°C;V1+=V2+=+2.5V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter Symbol Min Typ Max Unit

Serial Port Timing in SSC Mode (SMODE = VL)

Data hold time after SCLK rising t
Serial Clock (Out) Pulse Width (low)

(Note 13, 14) Pulse Width (high)

rising after last SCLK rising t

RDY

falling to MSB stable t

CS
First SCLK rising after CS falling t

hold time (low) after SCLK rising t

CS
SCLK, SDO tri-state after CS

13. SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down
resistors.

14. SCLK = MCLK/2.

rising t

t
t

10
11
12
13
14

7
8

9

CS5566

-10-ns

100
100

-8-MCLKs

-10-ns

-8-MCLKs

10 - - ns

-5-ns

-

-

-

-

ns
ns

8 DS806PP2

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1

SCLK

10

MCLK

SCLK(i)

SDO

CS

RDY

LSBMSB

t

19

t

18

t

20

t

17

t

16

t

15

t

21

Figure 4. SEC Mode - Continuous SCLK Read Timing (Not to Scale)

SWITCHING CHARACTERISTICS (CONTINUED)

TA=-40to+85°C;V1+=V2+=+2.5V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter Symbol Min Typ Max Unit

Serial Port Timing in SEC Mode (SMODE = VLR)

SCLK(in) Pulse Width (High)
SCLK(in) Pulse Width (Low)

-

-

CS5566

30 - - ns
30 - - ns

hold time (high) after RDY falling t

CS

hold time (high) after SCLK rising t

CS

low to SDO out of Hi-Z (Note 15) t

CS
Data hold time after SCLK rising t
Data setup time before SCLK rising t

CS

hold time (low) after SCLK rising

RDY

rising after SCLK falling t

15. SDO will be high impedance when CS is high. In some systems SDO may require a pull-down resistor.

15
16
17
18
19

t

20

21

10 - - ns
10 - - ns

-10-ns

-10-ns

10 - - ns
10 - ns

-10-ns

DS806PP2 9