Cirrus Logic CS5530 User Manual

CS5530

VA+ C1 C2 VREF+ VREF- VD+

DIFFERENTIAL

4

TH

ORDER

ΔΣ

MODULATOR

PROGRAMMABLE

SINC FIR FILTER

AIN1+

AIN1-

SERIAL

INTERFACE

LATCH

CLOCK

GENERATOR

CALIBRATION

SRAM/CONTROL

LOGIC

DGND

CS

SDI
SDO

SCLK

OSC2OSC1A1A0VA-

64X

24-bit ADC with Ultra-low-noise Amplifier

Features & Description

 Chopper-stabilized Instrumentation

Amplifier, 64X

• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)

• 1200 pA Input Current

Digital Gain Scaling up to 40x



 Delta-sigma Analog-to-digital Converter

• Linearity Error: 0.0015% FS

• Noise Free Resolution: Up to 19 bits

Scalable V



 Simple Three-wire Serial Interface

• SPI™ and Microwire™ Compatible

• Schmitt-trigger on Serial Clock (SCLK)

Onboard Offset and Gain Calibration



Registers

 Selectable Word Rates: 6.25 to 3,840 Sps
 Selectable 50 or 60 Hz Rejection
 Power Supply Configurations

• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V

• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V

• VA+ = +3 V; VA- = -3 V; VD+ = +3 V

Input: Up to Analog Supply

REF

General Description

The CS5530 is a highly integrat ed ΔΣ Analog-to-Digital
Converter (ADC) which uses charge-balance techniques
to achieve 24-bit performance. The ADC is optimized for
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.

To accommodate these applications, the ADC
a very-low-noise, chopper-stabilized instrumentation
amplifier (12 nV/√Hz

@ 0.1 Hz) with a gain of 64X. This
device also includes a fourth-order ΔΣ modulator fol­lowed by a digital filter

which provides twenty selectable
output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,
120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and
3840 Sps (MCLK = 4.9152 MHz).

To ease communication between the ADC and a micro­controller, the converter includes a simple three-wire se­rial interface which is SPI and Microwire compatible with
a Schmitt-trigger input on the serial clock (SCLK).

High dynamic range, programmable output rates, and
flexible power supply options make this device an ideal
solution for weigh scale and process control
applications.

ORDERING INFORMATION

See page 35.

includes

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2009

(All Rights Reserved)

NOV ‘09

DS742F3

CS5530

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ................................................................. 4

ANALOG CHARACTERISTICS................................................................................ 4

TYPICAL NOISE-FREE RESOLUTION (BITS)........................................................6

5 V DIGITAL CHARACTERISTICS .......................................................................... 7

3 V DIGITAL CHARACTERISTICS .......................................................................... 7

DYNAMIC CHARACTERISTICS..............................................................................8

ABSOLUTE MAXIMUM RATINGS...........................................................................8

SWITCHING CHARACTERISTICS..........................................................................9

2. GENERAL DESCRIPTION .............................................................................................. 11

2.1. Analog Input ........................................................................................................... 11

2.1.1. Analog Input Span .......................................................................................... 12

2.1.2. Voltage Noise Density Performance ...........................................................12

2.1.3. No Offset DAC ............................................................................................ 12

2.2. Overview of ADC Register Structure and Operating Modes .................................. 12

2.2.1. System Initialization .................................................................................... 12

2.2.2. Command Register Descriptions ................................................................14

2.2.3. Serial Port Interface .................................................................................... 16

2.2.4. Reading/Writing On-Chip Registers ............................................................ 17

2.3. Configuration Register ...........................................................................................17

2.3.1. Power Consumption ................................................................................... 17

2.3.2. System Reset Sequence ............................................................................17

2.3.3. Input Short ..................................................................................................17

2.3.4. Voltage Reference Select .......................................................................... 17

2.3.5. Output Latch Pins .......................................................................................18

2.3.6. Filter Rate Select ........................................................................................18

2.3.7. Word Rate Select ........................................................................................ 18

2.3.8. Unipolar/Bipolar Select ...............................................................................18

2.3.9. Open Circuit Detect .................................................................................... 18

2.3.10. Configuration Register Description ...........................................................19

2.4. Calibration .............................................................................................................. 21

2.4.1. Calibration Registers .................................................................................. 21

2.4.2. Gain Register .............................................................................................21

2.4.3. Offset Register ...........................................................................................21

2.4.4. Performing Calibrations ..............................................................................22

2.4.5. System Calibration ...................................................................................... 22

2.4.6. Calibration Tips ...........................................................................................22

2.4.7. Limitations in Calibration Range ................................................................. 23

2.5. Performing Conversions ........................................................................................ 23

2.5.1. Single Conversion Mode ............................................................................. 23

2.5.2. Continuous Conversion Mode .................................................................... 24

2.6. Using Multiple ADCs Synchronously ..................................................................... 25

2.7. Conversion Output Coding ....................................................................................25

2.7.1. Conversion Data Output Descriptions ........................................................ 26

2.8. Digital Filter ............................................................................................................ 27

2.9. Clock Generator .....................................................................................................28

2.10. Power Supply Arrangements ................................................................................. 28

2.11. Getting Started ....................................................................................................... 31

2.12. PCB Layout ............................................................................................................ 31

3. PIN DESCRIPTIONS ......................................................................................................32

Clock Generator ......................................................................................................32

Control Pins and Serial Data I/O .............................................................................32

Measurement and Reference Inputs ......................................................................33

Power Supply Connections .....................................................................................33

4. SPECIFICATION DEFINITIONS ..................................................................................... 33

5. PACKAGE DRAWINGS ..................................................................................................34

6. ORDERING INFORMATION .......................................................................................... 35

7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .................... 35

2 DS742F3

LIST OF FIGURES

Figure 1. SDI Write Timing (Not to Scale)...............................................................................10

Figure 2. SDO Read Timing (Not to Scale).............................................................................10

Figure 3. Front End Configuration...........................................................................................11

Figure 4. Input Model for AIN+ and AIN- Pins.........................................................................11

Figure 5. Measured Voltage Noise Density................ .............................................................12

Figure 5. Measured Voltage Noise Density................ .............................................................12

Figure 6. CS5530 Register Diagram.......................................................................................13

Figure 7. Command and Data Word Timing ...........................................................................16

Figure 8. Input Reference Model when VRS = 1 ....................................................................18

Figure 9. Input Reference Model when VRS = 0 ....................................................................18

Figure 10. System Calibration of Offset..................................................................................22

Figure 11. System Calibration of Gain ....................................................................................22

Figure 12. Synchronizing Multiple ADCs.................................................................................25

Figure 13. Digital Filter Response (Word Rate = 60 Sps).......................................................27

Figure 14. 120 Sps Filter Magnitude Plot to 120 Hz ...............................................................27

Figure 15. 120 Sps Filter Phase Plot to 120 Hz......................................................................27

Figure 16. Z-Transforms of Digital Filters................................................................................27

Figure 17. On-chip Oscillator Model........................................................................................28

Figure 18. CS5530 Configured with a Single +5 V Supply ............................................... ... ...29

Figure 19. CS5530 Configured with ±2.5 V Analog Supplies..................................................29

Figure 20. CS5530 Configured with ±3 V Analog Supplies.....................................................30

CS5530

LIST OF TABLES

Table 1. Conversion Timing for Single Mode..........................................................................24

Table 2. Conversion Timing for Continuous Mode..................................................................24

Table 3. Output Coding...........................................................................................................25

DS742F3 3

CS5530

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARCTERISTICS

(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz;
OWR (Output Word Rate) = 60 Sps; Bipolar Mode)
(See Notes 1 and 2.)

CS5530-CS

Parameter

Accuracy

Linearity Error - ±0.0015 ±0.003 %FS
No Missing Codes 24 - - Bits
Bipolar Offset - ±16 ±32 LSB

Unipolar Offset - ±32 ±64 LSB
Offset Drift (Notes 3 and 4) - 10 - nV/°C

Bipolar full-scale Error - ±8 ±31 ppm
Unipolar full-scale Error - ±16 ±62 ppm
full-scale Drift (Note 4) - 2 - ppm/°C

UnitMin Typ Max

24
24

Notes: 1. Applies after system calibration at any temperature within -40 °C to +85 °C.

2. Specifications guaranteed by design, characterization, and/or test. LSB is 24 bits.

3. This specification applies to the device only and does not include any effects by external parasitic
thermocouples.

4. Drift over specified temperature range after calibration at power-up at 25 °C.

4 DS742F3

CS5530

ANALOG CHARACTERISTICS (Continued)

(See Notes 1 and 2.)

Parameter Min Typ Max Unit

Analog Input

Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode (VA-) + 1.6 - (VA+) - 1.6 V
CVF Current on AIN+ or AIN- - 1200 - pA
Input Current Noise - 1 - pA/√Hz
Open Circuit Detect Current 100 300 - nA
Common Mode Rejection DC

50, 60 Hz

Input Capacitance - 10 - pF

Voltage Reference Input

Range (VREF+) - (VREF-) 1 2.5 (VA+)-(VA-) V
CVF Current (Note 5, 6) - 50 - nA
Common Mode Rejection DC

50, 60 Hz

Input Capacitance 11 - 22 pF

System Calibration Specifications

Full-scale Calibration Range Bipolar/Unipolar Mode 3 - 110 %FS
Offset Calibration Range Bipolar Mode -100 - 100 %FS
Offset Calibration Range Unipolar Mode -90 - 90 %FS

-

-

-

-

130
120

120
120

-

-

-

-

dB
dB

dB
dB

Notes: 5. See the section of the data sheet which discusses input models.

6. Input current on VREF+ or VREF- may increase to 250 nA if operated within 50 mV of VA+ or VA-. This
is due to the rough charge buffer being saturated under these conditions.

DS742F3 5

ANALOG CHARACTERISTICS (Continued)

(See Notes 1 and 2.)

Parameter

Power Supplies

DC Power Supply Currents (Normal Mode) I

Power Consumption Normal Mode (Note 7)

Power Supply Rejection (Note 8)

7. All outputs unloaded. All input CMOS levels.

8. Tested with 100 mV change on VA+ or VA-.

A+, IA-

I

D+

Standby
Sleep

DC Positive Supplies
DC Negative Supply

CS5530-CS

Min Typ

-

-

-

-

-

-

-

6

0.6
35

5

500

115
115

CS5530

Max

1.0
45

Unit

8

mA
mA

mW

-

mW

-

µW

-

-

dB
dB

TYPICAL NOISE-FREE RESOLUTION (BITS) (See Notes 9 and 10)

Output Word Rate (Sps) -3 dB Filter Frequency (Hz) Noise-free Bits

7.5 1.94 19 17
15 3.88 19 24
30 7.75 18 34
60 15.5 18 48

120 31 17 68
240 62 16 115
480 122 16 163

960 230 15 229
1,920 390 15 344
3,840 780 13 1390

9. Noise Free Resolution listed is for Bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMS
Noise))/LOG(2) rounded to the nearest bit. For Unipolar operatio n, the input span is 1/2 as large, so one
bit is lost. The input span is calculated in the analog input span section of the data sheet. The Noise
Free Resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will
scale the noise, and change the Noise Free Resolution accordingly.

10. “Noise Free Resolution” is not the same as “Effective Resolution”. Effective Resolution is based on the
RMS noise value, while Noise Free Resolution is based on a peak-to-peak noise value specified a s 6.6
times the RMS noise value. Effective Resolution is calculated as LOG((Input Span)/(RMS
Noise))/LOG(2).

Noise (nV

rms

)

Specifications are subject to change without notice.

6 DS742F3

5 V DIGITAL CHARACTERISTICS

(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 11.)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage All Pins Except SCLK

SCLK

Low-Level Input Voltage All Pins Except SCLK

SCLK

High-Level Output Voltage A0 and A1, I

SDO, I

Low-Level Output Voltage A0 and A1, I

SDO, I

= -1.0 mA

out

= -5.0 mA

out

= 1.0 mA

out

= 5.0 mA

out

Input Leakage Current I
SDO 3-State Leakage Current I
Digital Output Pin Capacitance C

V

IH

0.6 VD+

(VD+) - 0.45--

V

IL

0.0

0.0

V

OH

(VA+) - 1.0

(VD+) - 1.0

V

OL

in

OZ

out

- - (VA-) + 0.4

-±1±10µA

--±10µA

-9-pF

3 V DIGITAL CHARACTERISTICS

(TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V; See Notes 2 and 11.)

CS5530

VD+
VD+

-0.8

0.6

--V

0.4

V

V

V

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage All Pins Except SCLK

SCLK

Low-Level Input Voltage All Pins Except SCLK

SCLK

High-Level Output Voltage A0 and A1, I

SDO, I

Low-Level Output Voltage A0 and A1, I

SDO, I

= -1.0 mA

out

= -5.0 mA

out

= 1.0 mA

out

= 5.0 mA

out

Input Leakage Current I
SDO 3-State Leakage Current I
Digital Output Pin Capacitance C

11. All measurements performed under static conditions.

V

IH

V

IL

V

OH

0.6 VD+

(VD+) - 0.45

0.0

0.0

(VA+) - 1.0

-VD+

V

VD+

-0.8

V

0.6

--V

(VD+) - 1.0

V

OL

- - (VA-) + 0.4

V

0.4

in

OZ

out

-±1±10µA

--±10µA

-9-pF

DS742F3 7

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Unit

Modulator Sampling Rate f
Filter Settling Time to 1/2 LSB (full-scale Step Input)

Single Conversion mode (Notes 12, 13, and 14)
Continuous Conversion mode, OWR < 3200 Sps
Continuous Conversion mode, OWR ≥ 3200 Sps

CS5530

s

t

s

t

s

t

s

MCLK/16 Sps

1/OWR

5/OWR

sinc5

SC

+ 3/OWR

5/OWR

s
s
s

12. The ADCs use a Sinc5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc5 filter
followed by a Sinc
(FRS = 0) word rate associated with the Sinc

3

filter for the other OWRs. OWR

5

filter.

refers to the 3200 Sps (FRS = 1) or 3840 Sps

sinc5

13. The single conversion mode only outputs fully settled conversions. See Table 1 for more details about
single conversion mode timing. OWR

is used here to designate the different conversion time

SC

associated with single conversions.

14. The continuous conversion mode outputs every conversion. This means that the filter’s settling time
with a full-scale step input in the continuous conversion mode is dictated by the OWR.

ABSOLUTE MAXIMUM RATINGS

(DGND = 0 V; See Note 15.)

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Notes 16 and 17)

Positive Digital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies (Notes 18 and 19) I
Output Current I
Power Dissipation (Note 20) PDN - - 500 mW

Analog Input Voltage VREF pins

AIN Pins

Digital Input Voltage V
Ambient Operating Temperature T
Storage Temperature T

VD+
VA+

VA-

IN

OUT

V

INR

V

INA
IND

A

stg

-0.3

-0.3

+0.3

-

-

-

+6.0
+6.0

-3.75

V
V
V

--±10mA

--±25mA

(VA-) -0.3
(VA-) -0.3--

(VA+) + 0.3
(VA+) + 0.3VV

-0.3 - (VD+) + 0.3 V

-40 - 85 °C

-65 - 150 °C

Notes: 15. All voltages with respect to ground.

16. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.

17. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.

18. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.

19. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.

20. Total power dissipation, including all input currents and output currents.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

8 DS742F3

CS5530

SWITCHING CHARACTERISTICS

(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0
V, Logic 1 = VD+; C

Master Clock Frequency (Note 21)

Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 22)

Fall Times (Note 22)

Start-up

Oscillator Start-up Time XTAL = 4.9152 MHz (Note 23) t

Serial Port Timing

Serial Clock Frequency SCLK 0 - 2 MHz
Serial Clock Pulse Width High

SDI Write Timing

CS

Enable to Valid Latch Clock t
Data Set-up Time prior to SCLK rising t
Data Hold Time After SCLK Rising t
SCLK Falling Prior to CS

SDO Read Timing

to Data Valid t

CS
SCLK Falling to New Data Bit t

Rising to SDO Hi-Z t

CS

= 50 pF; See Figures 1 and 2.)

L

Parameter Symbol Min Typ Max Unit

MCLK

External Clock or Crystal Oscillator

Any Digital Input Except SCLK

SCLK

Any Digital Output

Any Digital Input Except SCLK

SCLK

Any Digital Output

Pulse Width Low

Disable t

t

t

rise

fall

ost

t

1

t

2

3
4
5
6

7
8
9

1 4.9152 5 MHz

-

-

-

-

-

-

50

50

-

-

1.0

100

-

-

-

1.0

100

-

-20-ms

250
250

-

-

-

-

50 - - ns

50 - - ns
100 - - ns
100 - - ns

--150ns

--150ns

--150ns

µs
µs
ns

µs
µs
ns

ns
ns

Notes: 21. Device parameters are specified with a 4.9152 MHz clock.

22. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

23. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.

DS742F3 9

CS5530

CS

SCLK

MSB

MSB-1

LSB

SDI

t3

t6t4 t5 t1

t2

Figure 1. SDI Write Timing (Not to Scale)

CS

SCLK

MSB MSB-1

LSB

SDO

t7

t9

t8

t1

t2

Figure 2. SDO Read Timing (Not to Scale)

10 DS742F3

2. GENERAL DESCRIPTION

VREF+

Sinc

Digital

Filter

64x

AIN+

AIN-

X1

VREF-

X1

Differe n tia l

4 Order

ΔΣ

Modulator

th

5

Programmable

Sinc

Digital Filter

3 Serial

Port

1000

Ω

1000 Ω

22 nF

C1 PIN
C2 PIN

Figure 3. Front End Configuration

AIN

C

= 3.9 pF

f =

V ≤ 8 mV
i = fV C

os

os

n

MCLK

128

Figure 4. Input Model for AIN+ and AIN- Pins

CS5530

The CS5530 is a ΔΣ Analog-to-Digital Converter
(ADC) which uses charge-balance techniques to
achieve 24-bit performance. The ADC is optimized
for measuring low-level unipolar or bipolar signals
in weigh scale, process control, scientific, and med­ical applications.

To accommodate these applications, the ADC in­cludes a very-low-noise, chopper-stabilized instru­mentation amplifier (12 nV/√Hz @ 0.1 Hz) with a
gain of 64X. This ADC also includes a fourth-order
ΔΣ modulator followed by a digital filter

which pro-

vides twenty selectable output word rates of 6.25,

7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400,
480, 800, 960, 1600, 1920, 3200, and 3840 samples
per second (MCLK = 4.9152 MHz).

To ease communication between the ADCs and a
micro-controller, the converters include a simple
three-wire serial interface which is SPI and Mi­crowire compatible with a Schmitt-trigger input on
the serial clock (SCLK).

2.1 Analog Input

Figure 3 illustrates a block diagram of the CS5530.
The front end includes a chopper-stabilized instru­mentation amplifier with a gain of 64X.

The amplifier is chopper-stabilized and operates with
a chop clock frequency of MCLK/128. The CVF
(sampling) current into the instrumentation amplifier
is typically 1200 pA over -40°C to +85°C
(MCLK=4.9152 MHz). The common-mode plus sig­nal range of the instrumentation amplifier is (VA-) +

1.6 V to (VA+) - 1.6 V.
Figure 4 illustrates the input model for the 64X am-

plifier.

Note: The C = 3.9 pF capacitor is for input current

modeling only. For physical input capacitance
see ‘Input Capacitance’ specification under
Analog Characteristics.

DS742F3 11