Cirrus Logic CS5529 User Manual

CS5529

16-bit, Programmable ∆Σ ADC with 6-bit Latch

Features

z Delta-sigma Analog-to-digital Converter

- Linearity Error: 0.0015%FS

- Noise-free Resolution: 16-Bits

z 2.5 V Bipolar/Unipolar Buffered Input Range
z 6-bit Output Latch
z Eight Digital Filters

- Selectable Output Word Rates

- Output Settles in One Conversion Cycle

- 50/60 Hz ±3 Hz Simultaneous Rejection

z Simple Three-wire Serial Interface

- SPI™ and Microwire™ Compatible

- Schmitt Trigger on Serial Clock (SCLK)

z System/Self-calibration with R/W Registers
z Power Supply Configurations

- VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V

- VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V

- VA+ = +3.0 V; VA- = -3.0 V; VD+ = +3.0 V

z Low Power Consumption: 2.6 mW

General Description

The 16-bit CS5529 is a low-power, programmable ∆Σ
ADC (Analog-to-Digital Converter), which includes
coarse/fine charge buffers, a fourth-order ∆Σ modulator,
a calibration microcontroller, a digital filter with program­mable decimation rates, a 6-bit output latch, and a three­wire serial interface. The ADC is designed to operate
from single or dual analog supplies and a single digital
supply.

The digital filter is programmable with output update
rates between 1.88 Hz to 101 Sps. These output rates
are specified for XIN = 32.768 kHz. Output word rates
can be increased by approximately 3X by using XIN =
100 kHz. The filter is designed to settle to full accuracy
for the selected output word rate in one conversion.
When operated at word rates of 15 Sps or less, the filter
rejects both 50 Hz and 60 Hz simultaneously.

Low power, single conversion settling time, programma­ble output rates, and the ability to handle negative input
signals make this single- or dual-supply product an ideal
solution for isolated and non-isolated applications.

ORDERING INFORMATION

See page 29.

AIN+

AIN-

VREF+

VREF-

A0 A1 D0 D1 D2 D3

http://www.cirrus.com

1X

1X

Latch

VA+

VA- DGND

Differential

4th Order

Delta-Sigma

Modulator

Calibration

Memory

Copyright © Cirrus Logic, Inc. 2005

(All Rights Reserved)

Calibration µC

Digital Filter

XIN XOUT

Clock

Gen.

VD+

Calibration

Register

Control

Register

Output

Register

CS

SCLK

SDI

SDO

AUG ‘05

DS246F5

1

TABLE OF CONTENTS

CHARACTERISTICS & SPECIFICATIONS ........................................................4

ANALOG CHARACTERISTICS...................................................................4

ANALOG CHARACTERISTICS...................................................................5

5V DIGITAL CHARACTERISTICS .............................................................. 6

3 V DIGITAL CHARACTERISTICS ..................................... ... .... ... ... ... ........6

DYNAMIC CHARACTERISTICS ................................................................. 6

ABSOLUTE MAXIMUM RATINGS.............................................................. 7

SWITCHING CHARACTERISTICS .............................................................8

GENERAL DESCRIPTION .......................................................... ... ................... 10

Analog Input ............................. ... .... ... ... ... ....................................... ... .... .. 10

Analog Input Model ............... .... ...................................... .... ... ... ... .... .. 10

Voltage Reference Input Model .......................................................... 10

Serial Port .................................................................................................11

Command Register Descriptions ........................................................ 12

Serial Port Interface ...........................................................................13

Serial Port Initialization ....................................................................... 15

System Initialization ........................... .... ... ... ... .... ... ............................ 15

Configuration Register .............................................................................. 15

Latch Output Pins .................. ....................................... ... .... ... ... ... .... .. 15

Power Consumption ...........................................................................15

Output Word Rate ..............................................................................16

Digital Filter ........................................................................................16

Clock Generator .............................................. .... ............................... 16

Reset System ..................................................................................... 16

Port Flag ....................... ....................................... ... ... ... ... .... ... ............17

Calibration .......................................................................................... 17

Configuration Register Descriptions .................................................20

Performing Conversions ........................... .... ...................................... .... .. 21

Performing Conversions with PF bit = 0 ....... ... .... ... ... ... ... ....... ... ... .... .. 21

Performing Conversions with PF bit = 1 ....... ... .... ... ... ... ... ....... ... ... .... .. 21

Output Coding ....................................................................................22

............................................................................................................ 22

Power Supply Arrangements ....................................................................23

Getting Started ......................................................................................... 25

PCB Layout ........................... ... ... .... ... ... ... ....................................... ... .... .. 25

PIN DESCRIPTIONS ......................................................................................... 26

SPECIFICATION DEFINITIONS ........................................................................ 28

ORDERING INFORMATION ..............................................................................29

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ......29

PACKAGE DIMENSIONS .................................................................................30

CS5529

Calibration Registers ................................................................... 17

Offset Register ... ... ....................................... ... ... .... ... ... ... ......17

Gain Register ........................................................................ 18

Self Calibration ............................................................................ 18

System Calibration .............................. ....................................... .. 18

Limitations in Calibration Range .................................................. 19

Calibration Tips ............................................................................19

Single Conversion ........................................................................ 21

Continuous Conversions ........................ ...................................... 21

2 DS246F5

LIST OF FIGURES

o

r

d

e
s
s

s

d

R

N

S

E

D

A

M

Y

o

Input models for AIN+ and AIN- pins......................................................... 11

Input model for VREF+ and VREF- pins. .................................................. 11

CS5529 Register Diagram. ....................................................................... 11

Command and Data Word Timing.............................. ...... ... ... .... ... ... ... .... .. 14

Filter Response (Normalized to Output Word Rate = 1)............................ 16

Self Calibration of Offset. .......................................................................... 18

Self Calibration of Gain. ............................................................................ 18

System Calibration of Offset...................................................................... 18

System Calibration of Gain........................................................................ 19

CS5529 Configured with a +5.0 V Analog Supply..................................... 23

CS5529 Configured with ±2.5 V Analog Supplies..................................... 23

CS5529 Configured with ±3.0 V Supplies. ................................................ 24

REVISION HISTORY

Revision Date Changes

CS5529

F4 Sep ‘04 Added lead-free device ordering information..
F5 Aug ‘05 Updated legal notice. Added MSL data.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE
Cirrus Logic, Inc. and i ts subsidiaries (“Cirr us”) believe that the information contained in t his document is accurate and re liable. However, the information is subject t

change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant info
mation to verify, before placing orders, that inform ation being relied on is current and complete. All prod ucts are sold subject to the term s and conditions of sale supp lie
at the time of order acknowl edgment, i ncludin g those per taining to warra nty, in demnifica tion, an d limitat ion of l iabili ty. No r esponsibility is assumed by Cirrus for th
use of this information, including use of this inform atio n as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third partie
This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyright
trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copie
to be made of the information on l y for use wi t h i n you r or g aniz a ti on wit h res p ect to Cirr u s integrated circuits or oth er pr od uct s of Cirr us . This con sen t do es no t exte n
to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

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TY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE I
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this docu ment may b e trademar ks
service marks of their respective owners.

DS246F5 3

CHARACTERISTICS & SPECIFICATIONS

CS5529

ANALOG CHARACTERISTICS (T

VREF- = 0.0 V, F
(See Notes 1 and 2.)

Accuracy

Linearity Error - ±0.0015 ±0.003 %FS
No Missing Codes 16 - - Bits
Bipolar Offset (Note 3) - ±1 ±2 LSB

Unipolar Offset (Note 3) - ±2 ±4 LSB
Offset Drift (Notes 3 and 4) - 11 - nV/°C

Bipolar Gain Error - ±8 ±31 ppm
Unipolar Gain Error - ±16 ±63 ppm
Gain Drift (Note 4) - 1 - ppm/°C

Noise (Notes 5 and 6)

Output Word Rate (Hz) -3 dB Filter Frequency (Hz) Noise (µV)

= 32.768 kHz, OWR (Output Word Rate) = 15 Sps, Bipolar Mode, Input Range = ±2.5 V.)

CLK

Parameter Min Typ Max Unit

1.88 1.64 4.5

3.76 3.27 5.0

7.51 6.55 7.0

15.0 12.7 15

30.0 25.4 45

61.6 50.4 190

84.5 70.7 900

101.1 84.6 3000

= 25 °C; VA± = ±2.5 V ±5%, VD+ = 5 V ±5%, VREF+ = 2.5 V,

A

16
16

Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.

2. Specifications guaranteed by design, characterization, and/or test.

3. Specification applies to the device only and does not include any eff ec ts by external parasitic
thermocouples.

4. Drift over specified temperature range after calibration at power-up at 25 °C.

5. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.

6. For peak-to-peak noise multiply by 6.6 for all ranges and output rates.

Specifications are subject to change without notice.

4 DS246F5

CS5529

ANALOG CHARACTERISTICS (Continued)

Parameter Min Typ Max Unit

Analog Input

Common Mode + Signal on AIN+ or AIN- (Bipolar/Unipolar Mode)

Single Supply
Dual Supply

Common Mode Rejection dc

50, 60Hz
Input Capacitance - 10 - pF
CVF Current AIN+, AIN- (Note 7) - 16 - nA

System Calibration Specifications

Full Scale Calibration Range, with VREF = 2.5 V (Note 8) 1.0 - 3.5 V
Offset Calibration Range (Bipolar/Unipolar Mode) - - ±1.25 V

Voltage Reference Input

Range {(VREF+) - (VREF-)} (Note 9) 1.0 2.5 5 V
REF+ VA- - VA+ V
REF- VA- - VA+ V
Common Mode Rejection dc

50, 60 Hz
Input Capacitance - 16 - pF
CVF Current (Note 7) - 8 - nA

Power Supplies

DC Power Supply Currents (Normal Mode)

I

A+

I

D+

Power Consumption Normal Mode (Note 10)

Low Power Mode

Standby

Sleep
Power Supply Rejection dc Positive Supplies

dc Negative Supply

0.0

VA-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

120
120

110
130

400
110

2.6

1.8
1

500

80
80

VA+
VA+

-

-

-

-

520
150

3.5

2.5

-

-

-

-

mW
mW
mW

µW

V
V

dB
dB

dB
dB

µA
µA

dB
dB

Notes: 7. See the section of the data sheet which discusses Analog Input Models.

8. The minimum Full Scale Calibration Range (FSCR) is limited by the maximum allowed gain register
value (with margin). The maximum FSCR is limited by the ∆Σ modulator’s 1’s density range. See
“Analog Input” section for details. Also see “Limitations in Calibration Range”.

9. VREF must be less than or equal to supply voltages.

10. All outputs unloaded. All inputs CMOS levels. Power consumption scales linearly with changes in
supply voltage.

DS246F5 5

CS5529

5V DIGITAL CHARACTERISTICS (T

= 25 °C; VA± = ±2.5V ±5%, VD+ = 5V ± 5 % .)(See Notes 2 and

A

11.)

Parameter Symbol Min Typ Max Unit

High-level Input Voltage: All Pins Except XIN, SCLK

XIN

SCLK

Low-level Input Voltage: All Pins Except XIN, SCLK

XIN

SCLK

High-level Output Voltage: All Pins Except SDO (Note 12)

SDO, I

Low-level Output V oltage: All Pins Except SDO, I

SDO, I

= -5.0mA

out

= 1.6mA

out

= 5.0mA

out

Input Leakage Current I
3-state Leakage Current I
Digital Output Pin Capacitance C

Notes: 11. All measurements performed under static conditions.

12. I

= -100 µA unless stated otherwise. (VOH = 2.4 V @ I

out

out

V

IH

V

IH
IH

IL
IL
IL

OH
OH

OL
OL

in

OZ

out

(VD+)-0.45

V
V

V
V

V
V

V
V

= -40 µA).

0.6VD+

(VD+)-0.9

-

-

-

(VD+)-1.0
(VD+)-1.0--

-

-

-

-

-

-

-

-

-

-

-

-

-

0.8

2.0

0.6

-

-

0.4

0.4

-±1±10µA

--±10µA

-9-pF

V
V
V

V
V
V

V
V

V
V

3 V DIGITAL CHARACTERISTICS (T

= 25 °C; VA± = ±2.5 V ±5%, VD+ = 3.0 V ±5%.)

A

(See Notes 2 and 11.)

Parameter Symbol Min Typ Max Unit

High-level Input Voltage: All Pins Except XIN, SCLK

XIN

SCLK

Low-level Input Voltage: All Pins Except XIN, SCLK

XIN

SCLK

High-level Output Voltage: All Pins Except SDO, I

SDO, I

Low-level Output V oltage: All Pins Except SDO, I

SDO, I

= -400 µA

out

= -5.0 mA

out

= 400 µA

out

= 5.0 mA

out

Input Leakage Current I
3-state Leakage Current I
Digital Output Pin Capacitance C

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Units

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

V

OH

V

OH

V

OL

V

OL
in

OZ

out

0.6VD+

(VD+)-0.9

(VD+)-0.45

-

-

-

(VD+)-0.3
(VD+)-1.0--

-

-

-±1±10µA

--±10µA

-9-pF

-

-

-

-

-

-

-

-

-

-

-

0.16 VD+

0.5

0.6

-

-

0.3

0.4

V
V
V

V
V
V

V
V

V
V

Modulator Sampling Frequency f
Filter Settling Time to 1/2 LSB (Full Scale Step) t

s
s

XIN/4 Hz

1/f

out

s

6 DS246F5

CS5529

ABSOLUTE MAXIMUM RATINGS (DGND = 0 V) (See Note 13.)

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Notes 14 and 15)

Positive Digital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies (Notes 16 and 17) I
Output Current I

VD+
VA+

VA-

IN

OUT

-0.3

-0.3

-6.0

-

-

-

--±10mA

--±25mA

+6.0
+6.0
+0.3

Power Dissipation (Note 18) PDN - - 8 mW
Analog Input Voltage AIN and VREF pins V

Digital Input Voltage V
Ambient Operating Temperature T
Storage Temperature T

INA
IND

A

stg

(VA-) + (-0.3) - (VA+)+0.3 V

-0.3 - (VD+)+0.3 V

-40 - +85 °C

-65 - +150 °C

Notes: 13. All voltages with respect to ground.

14. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.3 V; and |VA-| must be ≤ VA+.

15. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.75 V.

16. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.

17. Transient current of up to 100mA will not cause SCR latch -up. Maximum input current for a power
supply pin is ±50 mA.

18. Total power dissipation, including all input currents and output currents.

V
V
V

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

DS246F5 7

CS5529

SWITCHING CHARACTERISTICS (T

Input Levels: Logic 0 = 0 V, Logic 1 = VD+; C

= 50pF)

L

= 25 °C; VA ± = ±2.5 V ±5%, VD+ = 3 V ±5% or 5 V ±5%;

A

Parameter Symbol Min Typ Max Unit

Master Clock Frequency: External Clock or Internal Oscillator

XIN 30 32.768 100 kHz

(Note19)
Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 20)

Any Digital Input Except SCLK

SCLK

Any Digital Output

Fall Times (Note 20)

Any Digital Input Except SCLK

SCLK

Any Digital Output

t

t

rise

rise

-

-

-

-

-

-

-

-

50

-

-

50

1.0

100

-

1.0

100

-

µs
µs
ns

µs
µs
ns

Start-up

Oscillator Start-up Time XTAL = 32.768 kHz (Note 21) t
Power-on Reset Period t

ost

por

-500-ms

- 1002 - XIN
cycles

Serial Port Timing

Serial Clock Frequency SCLK 0 - 2 MHz
Serial Clock Pulse Width High

Pulse Width Low

t

1

t

2

250
250

-

-

-

-

ns
ns

SDI Write Timing

CS

Enable to Valid Latch Clock t
Data Set-up Time prior to SCLK rising t
Data Hold Time After SCLK Rising t
SCLK Falling Prior to CS

Disable t

3
4
5
6

50 - - ns

50 - - ns
100 - - ns
100 - - ns

SDO Read Timing

to Data Valid t

CS
SCLK Falling to New Data Bit t

Rising to SDO Hi-Z t

CS

7
8
9

--150ns

--150ns

--150ns

Notes: 19. Device parameters are specified with 32.768 kHz clock, however, clocks up to 100 kHz can be used for

increased throughput.

20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.

8 DS246F5

CS

CS5529

SCLK

CS

SDI

SCLK

t3

MSB

t3

t1

t2

Continuous Running SCLK Timing (Not to Scale)

MSB-1

t2

t6

LSB

t6t4 t5 t1

SDI Write Timing (Not to Scale)

CS

SDO

t7

MSB MSB-1

t8

LSB

t2

t9

SCLK

t1

SDO Read Timing (Not to Scale)

DS246F5 9

CS5529

GENERAL DESCRIPTION

The CS5529 is a 16-bit ∆Σ Analog-to-Digital Con­verter (ADC) which includes coarse/fine charge
buffers, a fourth order ∆Σ modulator, a calibration
microcontroller, eight digital filters which provide
selectable decimation rates, a 6-bit output latch,
and a three-wire serial interface. The ADC is opti­mized to digitize unipolar or bipolar signals in in­dustrial applications.

The digital filters provide eight selectable output
word rates (OWRs) of 1.88 Sps, 3.76 Sps, 7.51 Sps,

15.0 Sps, 30.0 Sps, 61.6 Sps, 84.5 Sps, 101.1 Sps
when operated from a 32.768 kHz watch crystal or
equivalent clock (output word rates can be in­creased by approximately 3X by using 100 kHz
clock). The filters are designed to settle to full ac­curacy for the selected output word rate in one con­version. When operated at word rates of 15 Sps or
less (XIN = 32.768 kHz), the filter rejects both 50
Hz and 60 Hz line interference simultaneously.

Analog Input

The CS5529 provides a nominal 2.5 V input span
when the gain register is 1.0 decimal and the differ­ential reference voltage between VREF+ and
VREF- is 2.5 V. The gain registers content is used
during calibration to set the gain slope of the
ADC’s transfer function. The differential reference
voltage magnitude and the gain register are two
factors that can be used to scale the nominal 2.5 V
input span. After reset, the gain register defaults to

1.0 decimal. In this case, the external voltage be­tween the VREF+ pin and the VREF- pin sets the
ADC’s nominal full scale input span to 2.5 V. If a
user want to modify the input span, either the gain
register or the reference voltage’s magnitude needs
to be changed. For example, if a 1.25 V reference is
used in place of the nominal 2.5 V input, the full­scale span is cut in half. To achieve the same 1.25V
input span, the user could simply use a 2.5 V refer­ence and modify the gain register to 2.0 decimal.

Note that to keep from saturating the analog front
end, the input span must stay at or below 1.5 times
the reference voltage. This corresponds to a gain
register of 0.666... when a 2.5 V reference voltage
is used.

Note: When a smaller reference voltage is used,

the resulting code widths are smaller. Since
the output codes exhibit more changing
codes for a fixed amount of noise, the
converter appears noisier.

Calibration can also affect the ADC’s full scale
span because system gain calibration can be used to
increase or decrease the full scale span of the
ADC’s transfer functions. At its limit, the input full
scale can be reduced to the point in which the gain
register reaches its upper limit of 3.999... (this will
occur when the ADC is gain calibrated with an in­put signal less than or equal to approximately 1/4 of
its nominal full scale, if the ADC does not have in­trinsic gain error). Calibration and its effects on the
analog input span is detailed in a later section of the
data sheet.

Analog Input Model

Figure 1 illustrates the input models for the AIN
pins. The model includes a coarse/fine charge buff­er which reduces the dynamic current demands
from the signal source. The buffer is designed to
accommodate rail to rail (common-mode plus sig­nal) input voltages. Typical CVF (sampling) cur­rent is about 16nA (XIN = 32.768 kHz, see Figure

1). Application Note 30, “Switched-Capacitor A/D
Input Structures”, details various input architec­tures.

Voltage Reference Input Model

Figure 2 illustrates the input models for the VREF
pins. It includes a coarse/fine charge buffer which
reduces the dynamic current demand of the exter­nal reference. Typical CVF (sampling) current is
about 8nA (XIN = 32.768 kHz, see Figure 2).

The reference’s buffer is designed to accommodate
rail-to-rail (common-mode plus signal) input volt-

10 DS246F5