Cirrus Logic CS5526 User Manual

CS5525 CS5526

16-bit/20-bit, Multi-range ADC with 4-bit Latch

Features

z Delta-sigma A/D Converter

- Linearity Error: 0.0015%FS

- Noise-free Resolution: 18-bits

z Bipolar/Unipolar Input Ranges

- 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V

z Chopper Stabilized Instrumentation Amplifier z On-chip Charge Pump Drive Circuitry z 4-bit Output Latch z Simple three-wire serial interface

- SPI™ and Microwire™ Compatible

- Schmitt Trigger on Serial Clock (SCLK)

z Programmable Output Word Rates

- 3.76 Sps to 202 Sps (XIN = 32.768 kHz)

- 11.47 Sps to 616 Sps (XIN = 100 kHz)

z Output Settles in One Conversion Cycle z Simultaneous 50/60 Hz Noise Rejection z System and Self-calibration with

Read/Write Registers

z Single +5 V Analog Supply

+3.0 V or +5 V Digital Supply

z Low-power Mode Consumption: 4.9 mW

- 1.8 mW in 1 V, 2.5 V, and 5 V Input Ranges

General Description

The 16-bit CS5525 and the 20-bit CS5526 are highly integrated ∆Σ A/D converters which include an instrumentation amplifier, a PGA (programmable gain amplifier), eight digital filters, and self and system calibration circuitry.

The converters are designed to provide their own negative supply which enables their on-chip instrumentation amplifiers to measure bipolar ground-referenced signals ≤±100 mV. By directly supplying NBV with -2.5 V and with VA+ at 5 V, can be measured.

The digital filters provide programmable output update rates between 3.76 Sps to 202 Sps (XIN = 32.768 kHz). Output word rates can be increased by approximately 3X by using XIN = 100 kHz. Each filter is designed to settle to full accuracy for its output update rate in one conversion cycle. The filters with word rates of 15 Sps or less (XIN = 32.768 kHz) reject both 50 and 60 Hz ( interference simultaneously.

Low power, single conversion settling time, programmable output rates, and the ability to handle negative input signals make these single supply products ideal solutions for isolated and non-isolated applications.

ORDERING INFORMATION

See page 29.

±2.5 V signals (with respect to ground)

±3 Hz) line

AIN+

AIN-

NBV

A0 A1 A2 A3

http://www.cirrus.com

VA+ AGND VREF+ VREF- VD+DGND

X20

Latch

Programmable

Gain

Calibration

Memory

CPD

Differential

4th Order

Delta-Sigma

Modulator

Calibration µC

Digital Filter

Clock

Gen.

XIN XOUT

Calibration

Control

Output

SCLK

SDI

SDO

AUG ‘05

DS202F5

CS5525 CS5526

ANALOG CHARACTERISTICS (T

NBV = -2.1 V, FCLK = 32.768 kHz, OWR (Output Word Rate) = 15 Sps, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.)

Parameter

Accuracy

Linearity Error - ±0.0015 ±0.003 - ±0.0007 ±0.0015 %FS No Missing Codes 16 - - 20 - - Bits Bipolar Offset (Note 3) - ±1±2 -±16 ±32 LSB Unipolar Offset (Note 3) - ±2 ±4-±32 ±64 LSB Offset Drift (Notes 3 and 4) - 20 - - 20 - nV/°C Bipolar Gain Error - ±8 ±31 - ±8 ±31 ppm Unipolar Gain Error - ±16 ±62 - ±16 ±62 ppm Gain Drift (Note 4) - 1 3 - 1 3 ppm/°C

Voltage Reference Input

Range (VREF+) - (VREF-) 1 2.5 3.0 1 2.5 3.0 V Common Mode Rejection dc

50, 60 Hz Input Capacitance - 16 - - 16 - pF CVF Current (Note 5) - 0.6 - - 0.6 - µA/V

= 25 °C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND,

CS5525 CS5526

Min Typ Max Min Typ Max Unit

110 130

dB dB

Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.

2. Specifications guaranteed by design, characterization, and/or test.

3. Specification applies to the device only and does not include any effec ts by exte rn al pa ra sit ic thermocouples. LSB = LSB

4. Drift over specified temperature range after calibration at power-up at 25 °C.

5. See the section of the data sheet which discusses input models on page 15.

for the CS5525, and LSB20 for the CS5526.

RMS NOISE (Notes 6 and 7)

Output Rate

(Sps)

3.76 3.27 90 nV 90 nV 130 nV 1.0 µV 2.0 µV 4.0 µV

7.51 6.55 110 nV 130 nV 190 nV 1.5 µV 3.0 µV 7 µV

15.0 12.7 170 nV 200 nV 250 nV 2.0 µV 5.0 µV 10 µV

30.1 25.4 250 nV 300 nV 500 nV 4.0 µV 10 µV 15 µV

60.0 50.4 500 nV 1.0 µV 1.5 µV 15 µV 45 µV 85 µV

123.2 (Note 8) 103.6 2.0 µV 4.0 µV 8.0 µV 72 µV 190 µV 350 µV

168.9 (Note 8) 141.3 10 µV 20.0 µV 30 µV 340 µV 900 µV 2.0 mV

202.3 (Note 8) 169.2 30 µV 55 µV 105 µV 1.1 mV 2.4 mV 5.3 mV

Notes: 6. Wideband noise aliased into the baseband. Referred to the input. Typical val ues shown for 25 °C.

7. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.

8. For input ranges <100 mV and output word rates >60 Sps, 32.768 kHz chopping frequency is used.

-3 dB Filter Frequency

25 mV 55 mV 100 mV 1 V 2.5 V 5 V

Specifications are subject to change without notice.

Input Range, (Bipolar/Unipolar Mode)

2 DS202F5

CS5525 CS5526

ANALOG CHARACTERISTICS (Continued)

Parameter Min Typ Max Unit

Analog Input

Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV

Range = 1 V , 2.5 V, or 5 V

NBV = AGND Range = 25 mV, 55 mV, or 100 mV

Range = 1 V , 2.5 V, or 5 V

Common Mode Rejection dc

50, 60 Hz

-0.150 NBV

1.85

0.0

120

120 Input Capacitance - 10 - pF CVF Current on AIN+ or AIN- (Note 5)

Range = 25 mV, 55 mV, or 100 mV Range = 1 V , 2.5 V, or 5 V

100

1.2

System Calibration Specifications

Full-scale Calibration Range Bipolar/Unipolar Mode (Note 9)

25 mV 55 mV 100 mV 1 V

2.5 V 5 V

17.5

38.5 70

0.70

1.75

3.50

Offset Calibration Range Bipolar/Unipolar Mode

25 mV 55 mV 100 mV (Note 10) 1 V

2.5 V 5 V

Power Supplies

DC Power Supply Currents (Normal Mode) I

NBV

A+

D+

Power Consumption Normal Mode (Note 11)

Low Power Mode Standby Sleep

Power Supply Rejection dc Positive Supplies

dc NBV

1.65 15

475

9.4

4.9

1.2

500

110

0.950 VA+

2.65 VA+

300

32.5

71.5

105

dB dB

µA/V

mV mV mV

1.30

3.25 VA+

±12.5 ±27.5

±50

mV mV mV

±0.5

±1.25 ±2.50

2.2 30

700

12.7

8.5

µA µA

mW mW mW

µW

dB dB

V V V V

V V V

Notes: 9. The minimum Full-scale Calibration Range (FSCR) is limited by the maximum allowed gain register

value (with margin). The maximum FSCR is limited by the ∆Σ modulator’s 1’s density range.

10. The maximum full-scale signal can be limited by saturation of circuitry within the internal signal path.

11. All outputs unloaded. All input CMOS levels.

DS202F5 3

CS5525 CS5526

5 V DIGITAL CHARACTERISTICS (T

= 25 °C; VA+, VD+ = 5 V ±5%; GND = 0;

See Notes 2 and 12.))

Parameter Symbol Min Typ Max Unit

High-level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

Low-level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

High-level Output Voltage

All Pins Except CPD and SDO (Note 13)

CPD, I SDO, I

= -4.0 mA

out

= -5.0 mA

out

Low-level Output Voltage

All Pins Except CPD and SDO, I

CPD, I

SDO, I

= 1.6 mA

out

= 2 mA

out

= 5.0 mA

out

Input Leakage Current I 3-state Leakage Current I Digital Output Pin Capacitance C

0.6 VD+

3.5

(VD+) - 0.45

0.0

(VA+) - 1.0 (VD+) - 1.0 (VD+) - 1.0

out

-±1±10µA

--±10µA

-9-pF

VD+

0.8

1.5

0.6

0.4

V V V

Notes: 12. All measurements performed under static conditions.

13. I

3.0 V DIGITAL CHARACTERISTICS (T

= -100 µA unless stated otherwise. (VOH = 2.4 V @ I

out

= 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0;

See Notes 2 and 12.))

Parameter Symbol Min Typ Max Unit

High-level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

Low-level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

High-level Output Voltage

All Pins Except CPD and SDO, I

CPD, I SDO, I

= -400 µA

out

= -4.0 mA

out

= -5.0 mA

out

Low-level Output Voltage

All Pins Except CPD and SDO, I

CPD, I

SDO, I

= 400 µA

out

= 2 mA

out

= 5.0 mA

out

Input Leakage Current I 3-state Leakage Current I Digital Output Pin Capacitance C

out

= -40 µA.)

0.6 VD+

0.54 VA+

(VD+) - 0.45

0.0

(VA+) - 0.3 (VD+) - 1.0 (VD+) - 1.0

VD+

0.16 VD+

1.5

0.6

0.3

0.4

V V V

-±1±10µA

--±10µA

-9-pF

4 DS202F5

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Unit

Modulator Sampling Frequency f Filter Settling Time to 1/2 LSB (Full Scale Step) t

CS5525 CS5526

s s

XIN/2 Hz

1/f

out

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND = 0 V; See Note 14.))

Parameter Symbol Min Typ Max Unit

DC Power Supplies Positive Digital

Positive Analog

Analog Reference V oltage (VREF+) - (VREF-) VRef

VD+

VA+

diff

2.7

4.75

5.0

5.25

1.0 2.5 3.0 V

V V

Negative Bias Voltage NBV -1.8 -2.1 -2.5 V

Notes: 14. All voltages with respect to ground.

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 14.)

Parameter Symbol Min Max Unit

DC Power Supplies (Note 15)

Positive Digital

Positive Analog Negative Bias Voltage Negative Potential NBV +0.3 -3.0 V Input Current, Any Pin Except Supplies (Note 16 and 17) I

Output Current I Power Dissipation (Note 18) PDN - 500 mW

Analog Input Voltage VREF pins

AIN Pins

Digital Input Voltage V Ambient Operating Temperature T Storage Temperature T

VD+

VA+

OUT

INR

INA

IND

stg

-0.3

+6.0 +6.0

V V

-±10mA

-±25mA

-0.3

NBV - 0.3

(VA+) + 0.3 (VA+) + 0.3

V V

-0.3 (VD+) + 0.3 V

-40 85 °C

-65 150 °C

Notes: 15. No pin should go more negative than NBV - 0.3 V.

16. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.

17. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.

18. Total power dissipation, including all inpu t currents and output currents.

WARNING: Operation at or beyo nd these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

DS202F5 5

CS5525 CS5526

SWITCHING CHARACTERISTICS (T

Input Levels: Logic 0 = 0 V, Logic 1 = VD+; C

= 50 pF.))

= 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;

Parameter Symbol Min Typ Max Unit

Master Clock Frequency (Note 19)

Internal Clock

External Clock

XIN

30 30

32.768

100

kHz

Master Clock Duty Cycle 40 - 60 % Rise Times (Note 20)

Any Digital Input Except SCLK

SCLK

Any Digital Output

Fall Times (Note 20)

Any Digital Input Except SCLK

SCLK

Any Digital Output

rise

fall

1.0

100

1.0

100

µs µs ns

Start-up

Oscillator Start-up Time XTAL = 32.768 kHz (Note 21) t Power-on Reset Period t

ost

por

-500-ms

- 1003 - XIN cycles

Serial Port Timing

Serial Clock Frequency SCLK 0 - 2 MHz SCLK Falling to CS

Falling for continuous running SCLK

100 - - ns

(Note 22)

Serial Clock Pulse Width High

Pulse Width Low

250 250

ns ns

SDI Write Timing

Enable to Valid Latch Clock t Data Set-up Time prior to SCLK rising t Data Hold Time After SCLK Rising t SCLK Falling Prior to CS

Disable t

3 4 5 6

50 - - ns

50 - - ns 100 - - ns 100 - - ns

SDO Read Timing

to Data Valid t

CS SCLK Falling to New Data Bit t

Rising to SDO Hi-Z t

7 8 9

--150ns

Notes: 19. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 100 kHz can be used

for increased throughput.

20. Specified using 10% and 90% points on wa veform of interest. Output loaded with 50 pF.

21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.

22. Applicable when SCLK is continuously running.

6 DS202F5

SCLK

CS5525 CS5526

Continuous Running SCLK Timing (Not to Scale)

SDO

SCLK

MSB

MSB-1 LSBSDI

SDI Write Timing (Not to Scale)

MSB-1 LSB

SDO Read Timing (Not to Scale)

DS202F5 7

CS5525 CS5526

DETAILED DESCRIPTION

The CS5525 and CS5526 are 16-bit and 20-bit pin compatible converters which include a chopperstabilized instrumentation amplifier input, and an on-chip programmable gain amplifier. They are both optimized for measuring low-level unipolar or bipolar signals in process control and medical applications.

The CS5525/26 also include a fourth order deltasigma modulator, a calibration microcontroller, eight digital filters, a 4-bit analog latch, and a serial port. The digital filters provide any one of eight different output update rates.

The CS5525/26 include a CPD (Charge Pump Drive) output (shown in Figure 1). CPD provides a negative bias voltage to the on-chip instrumentation amplifier when used with a combination of external diodes and capacitors. This enables the CS5525/26 to measure negative voltages with re-

spect to ground, making the converters ideal for thermocouple temperature measurements.

Theory of Operation

The CS5525/26 A/D converters are designed to operate from a single +5 V analog supply and provide several different input ranges. See the Analog Characteristics section on page 3 for details.

Figure 1 illustrates the CS5525/26 connected to generate their own negative bias supply using the on-chip CPD (Charge Pump Drive). This enables the CS5525/26 to measure ground referenced signals with magnitudes down to NBV (Negative Bias Voltage, approximately -2.1 V in this example). Figure 2 illustrates a charge pump circuit when the converters are powered from a +3.0 V digital supply. Alternatively, the negative bias supply can be generated from a negative supply voltage or a resistive divider as illustrated in Figure 3.

Figure 1. CS5525/26 Configured to use on-chip charge pump to supply NBV.

8 DS202F5

CS5525 CS5526

Figure 4 illustrates the CS5525/26 connected to measure ground referenced unipolar signals of a positive polarity using the 1 V, 2.5 V, and 5 V input voltage ranges on the converter. For the 25 mV, 55 mV, and 100 mV ranges the signal must have a common mode near +2.5 V (NBV = 0V).

The CS5525/26 are optimized for the measurement of thermocouple outputs, but they are also well suited for the measurement of ratiometric bridge transducer outputs. Figure 5 illustrates the CS5525/26 connected to measure the output of a ratiometric differential bridge transducer while operating from a single +5 V supply.

2N5087

or similar

NBV

10µF

Figure 2. Charge Pump Drive Circuit for VD+ = 3 V. Figure 3. Alternate NBV Circuits.

-5V

34.8K

30.1K

2.0K

NBV

2.1K

-5V

10 µF

Figure 4. CS5525/26 Configured for ground-referenced Unipolar Signals.

DS202F5 9

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