CIRRUS LOGIC CS5521, CS5522, CS5523, CS5524 Service Manual

CS5521/22/23/24/28

16-bit or 24-bit, 2/4/8-channel ADCs with PGIA

Features

z Low Input Current (100 pA), Chopper-

stabilized Instrumentation Amplifier

z Scalable Input Span (Bipolar/Unipolar)

- 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V,

2.5V, 5V

- External: 10 V, 100 V

z Wide V
z Fourth Order Delta-Sigma A/D Converter
z Easy to Use Three-wire Serial Interface Port

- Programmable/Auto Channel Sequencer with
Conversion Data FIFO

- Accessible Calibration Registers per Channel

- Compatible with SPI™

z System and Self Calibration
z Eight Selectable Word Rates

- Up to 617 Sps (XIN = 200 kHz)

- Single Conversion Settling

- 50/60 Hz ±3 Hz Simultaneous Rejection

z Single +5 V Power Supply Operation

- Charge Pump Drive for Negative Supply

- +3 to +5 V Digital Supply Operation

z Low Power Consumption: 6.0 mW

Input Range (+1 to +5 V)

REF

and Microwire

General Description

The CS5521/22/23/24/28 are highly integrated ∆Σ ana­log-to-digital converters (ADCs) which use charge­balance techniques to achieve 16-bit (CS5521/23) and
24-bit (CS5522/24/28) performance. The ADCs
either two-channel (CS5521/22), four-channel
(CS5523/24), or eight-channel (CS5528) devices and
include a low-input-current, chopper-stabilized instru­mentation amplifier. To permit selectable input spans of
25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs
include a PGA (programmable gain amplifier). To ac­commodate ground-based thermocouple applications,
the devices include a charge pump drive which provides
a negative bias voltage to the on-chip amplifiers.

These devices also include a fourth-order ∆Σ modulator
followed by a digital filter
output word rates

. The digital filters are designed to settle

which provides eight selectable

to full accuracy within one conversion cycle and when
operated at word rates below 30 Sps, they reject both
50 Hz and 60 Hz interference.

These single-supply products are ideal solutions for
measuring isolated and non-isolated, low-level signals in
process control applications.

ORDERING INFORMATION

See page 52.

come as

AIN1+

AIN1-

AIN2+

AIN2-

AIN3+

AIN3-

AIN4+

AIN4-

NBV

http://www.cirrus.com

MUX

CS5524

Shown

VA+ AGND VREF+ VREF- VD+DGND

X1

Differential

4th Order

∆Σ

Modulator

Data FIFO &

Calibration R eg ist er s

(All Rights Reserved)

Digital Filter

+

X20

Latch

A0 A1CPD

X1

Gain

X1

Programmable

Clock

Gen.

XIN XOUT

Copyright © Cirrus Logic, Inc. 2005

Controller,

Setup Registers,

&

Channel Scan

Logic

Serial Port

Interface

CS

SCLK
SDI
SDO

AUG ‘05

DS317F4

TABLE OF CONTENTS

o

r

d

e
s
s

s

d

R

N

S

E

D

A

M

Y

o

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5

ANALOG CHARACTERISTICS................................................................................................5

TYPICAL RMS NOISE, CS5521/23.......................................................................................... 7

TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 .................................................... 7

TYPICAL RMS NOISE, CS5522/24/28..................................................................................... 8

TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 ............................................... 8

5 V DIGITAL CHARACTERISTICS...........................................................................................9

3 V DIGITAL CHARACTERISTICS...........................................................................................9

DYNAMIC CHARACTERISTICS ............................................................................................ 10

RECOMMENDED OPERATING CONDITIONS .....................................................................10

ABSOLUTE MAXIMUM RATINGS .........................................................................................10

SWITCHING CHARACTERISTICS ........................................................................................ 11

2. GENERAL DESCRIPTION ..................................................................................................... 13

2.1 Analog Input ........ ....................................... ... ....................................... ... .........................13

2.1.1 Instrumentation Amplifier .........................................................................................14

2.1.2 Coarse/Fine Charge Buffers ...................................... ...................................... ... 14

2.1.3 Analog Input Span Considerations ..........................................................................15

2.1.4 Measuring Voltages Higher than 5 V .................................................................. 15

2.1.5 Voltage Reference ........................................................................ ... ...................16

2.2 Overview of ADC Register Structure and Operating Modes ............................................16

2.2.1 System Initialization ................................... ... ... ....................................... ... .........18

2.2.2 Serial Port Initialization Sequence ............................. ... ... ... .... ............................ 18

2.2.3 Command Register Quick Reference ...................................... ... ... .... ...............19

2.2.4 Command Register Descriptions ........................................................................20

2.2.5 Serial Port Interface ...................................... ... ... ....................................... ... ......25

2.2.6 Reading/Writing the Offset, Gain, and Configuration Registers ................. .........26

2.2.7 Reading/Writing the Channel-Setup Registers ...................................................26

2.2.7.1 Latch Outputs ............ .... ... ....................................... ... ......................... 28

2.2.7.2 Channel Select Bits ............................................................................. 28

2.2.7.3 Output Word Rate Selection ...............................................................28

2.2.7.4 Gain Bits ........... ....................................... ... ...................................... ... 28

CS5521/22/23/24/28

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE
Cirrus Logic, Inc. and i ts subsidiaries (“Cirrus”) believe that the i nformation contained in this document is accurate and reliable. However, th e information is subject t

change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant info
mation to verify, before placing orders, that inform ation being relied on is current and complete. All prod ucts are sold subject to the term s and conditions of sale supp lie
at the time of order acknowl edgment, i ncludin g those per taining to warra nty, in demnifica tion, an d limitat ion of l iabili ty. No r esponsibility is assumed by Cirrus for th
use of this information, including use of this inform atio n as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third partie
This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyright
trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copie
to be made of the information on l y for use wi t h i n you r or g aniz a ti on wit h res p ect to Cirr u s integrated circuits or ot h er pr od uc t s of Cirrus. This consent does not ext en
to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPE
TY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE I
AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICE
LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO B
FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIE
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH
MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTO
ER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM AN
AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document m ay be tradem arks
service marks of their respective owners.

SPI is a trademark of Motorola, Inc.

2 DS317F4

CS5521/22/23/24/28

2.2.7.5 Unipolar/Bipolar Bit ............. ... ....................................... ... ................... 28

2.2.8 Configuration Register ..................... ... ....................................... ... ...................... 28

2.2.8.1 Chop Frequency Select ...................................................................... 28

2.2.8.2 Conversion/Calibration Control Bits ........... ......................................... 28

2.2.8.3 Power Consumption Control Bits ........................................................ 28

2.2.8.4 Charge Pump Disable ............................. ... ... ...................................... 29

2.2.8.5 Reset System Control Bits .................................................................. 29

2.2.8.6 Data Conversion Error Flags .............................................................. 29

2.3 Calibration .................................................................... ... ....................................... ......... 31

2.3.1 Self Calibration .......................... ....................................... ... ................................ 31

2.3.2 System Calibration .............................. ... .... ...................................... .... ............... 32

2.3.3 Calibration Tips ... ....................................... ... ....................................... ... ............ 34

2.3.4 Limitations in Calibration Range ......................................................................... 34

2.4 Performing Conversions and Reading the Data Conversion FIFO .................................. 34

2.4.1 Conversion Protocol ......................... ................................................................... 35

2.4.1.1 Single, One-Setup Conversion ........................................................... 35

2.4.1.2 Repeated One-Setup Conversions without Wait ................................ 35

2.4.1.3 Repeated One-Setup Conversions with Wait ..................................... 36

2.4.1.4 Single, Multiple-Setup Conversions .................................................... 36

2.4.1.5 Repeated Multiple-Setup Conversions without Wait ........................... 37

2.4.1.6 Repeated Multiple-Setup Conversions with Wait ................................ 37

2.4.2 Calibration Protocol .......................... ....................................... ... ......................... 38

2.4.3 Example of Using the CSRs to Perform Conversions and Calibrations .............. 38

2.5 Conversion Output Coding .............................................................................................. 40

2.5.1 Conversion Data FIFO Descriptions ................................................................... 41

2.6 Digital Filter ..................................................................................................................... 42

2.7 Clock Generator .............................. ... ... ....................................... ... ................................ 42

2.8 Power Supply Arrangements ................. .... ... ... ....................................... ... ...................... 43

2.8.1 Charge Pump Drive Circuits ......................................... ... ................................... 45

2.9 Digital Gain Scaling ........................................................................................................ 45

2.10 Getting Started .............................................................................................................. 46

2.11 PCB Layout ................................................................................................................... 47

3. PIN DESCRIPTIONS .............................................................................................................. 48

3.1 Clock Generator .............................. ... ... ....................................... ... ................................ 49

3.2 Control Pins and Serial Data I/O ..................................................................................... 49

3.3 Measurement and Reference Inputs ............................................................................... 49

3.4 Power Supply Connections ............................. ... .... ...................................... .... ............... 50

4. SPECIFICATION DEFINITIONS ............................................................................................. 51

5. ORDERING INFORMATION .................................................................................................. 52

6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ............................ 52

7. PACKAGE DIMENSION DRAWINGS ................................................................................... 53

DS317F4 3

LIST OF FIGURES

Figure 1. Continuous Running SCLK Timing (Not to Scale) .........................................................12

Figure 2. SDI Write Timing (Not to Scale).....................................................................................12

Figure 3. SDO Read Timing (Not to Scale)...................................................................................12

Figure 4. Multiplexer Configurations.............................................................................................. 13

Figure 5. Input Models for AIN+ and AIN- pins, £(100 mV Input Ranges......................................14

Figure 6. Input Models for AIN+ and AIN- pins, >100 mV input ranges ........................................14

Figure 7. Input Ranges Greater than 5 V ......................................................................................16

Figure 8. Input Model for VREF+ and VREF- Pins........................................................................ 16

Figure 9. CS5523/24 Register Diagram........................................................................................17

Figure 10. Command and Data Word Timing................................................................................ 25

Figure 11. Self Calibration of Offset (Low Ranges)....................................................................... 32

Figure 12. Self Calibration of Offset (High Ranges)......................................................................32

Figure 13. Self Calibration of Gain (All Ranges) ...........................................................................32

Figure 14. System Calibration of Offset (Low Ranges)................................................................. 32

Figure 15. System Calibration of Offset (High Ranges) ................................................................33

Figure 16. System Calibration of Gain (Low Ranges)...................................................................33

Figure 17. System Calibration of Gain (High Ranges) ..................................................................33

Figure 18. Filter Response (Normalized to Output Word Rate = 1) .............................................. 42

Figure 19. Typical Linearity Error for CS5521/23.......................................................................... 42

Figure 20. Typical Linearity Error for CS5522/24/28.....................................................................42

Figure 21. CS5522 Configured to use on-chip charge pump to supply NBV ................................43

Figure 22. CS5522 Configured for ground-referenced Unipolar Signals.......................................44

Figure 23. CS5522 Configured for Single Supply Bridge Measurement....................................... 44

Figure 24. Charge Pump Drive Circuit for VD+ = 3 V.................................................................... 45

Figure 25. Alternate NBV Circuits .................................................................................................45

CS5521/22/23/24/28

LIST OF TABLES

Table 1. Relationship between Full Scale Input, Gain Factors, and Internal Analog

Signal Limitations .............................................................................................................15

Table 2. Command Register Quick Reference.............................................................................. 19

Table 3. Channel-Setup Registers................................................................................................27

Table 4. Configuration Register.....................................................................................................30

Table 5. Offset and Gain Registers...............................................................................................31

Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28......................................40

REVISION HISTORY

Revision Date Changes

F3 May 2003
F4 August 2005 Added lead-free device ordering information. Updated legal notice.

4 DS317F4

1. CHARACTERISTICS AND SPECIFICATIONS

CS5521/22/23/24/28

ANALOG CHARACTERISTICS (T

= 25° C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND,

A

NBV = -2.1 V, XIN = 32.768 kHz, CFS1-CFS0 = ‘00’, OWR (Output Word Rate) = 15 Sps, Bipolar Mode, Input
Range = ±100 mV; See Notes 1 and 2.)

CS5521/23 CS5522/24/28

Parameter

UnitMin Typ Max Min Typ Max

Accuracy

Resolution - - 16 - - 24 Bits
Linearity Error - ±0.0015 ±0.003 - ±0.0007 ±0.0015 %FS
Bipolar Offset (Note 3) - ±1±2 -±16 ±32 LSB
Unipolar Offset (Note 3) - ±2 ±4-±32 ±64 LSB
Offset Drift (Notes 3 and 4) - 20 - - 20 - nV/°C
Bipolar Gain Error - ±8 ±31 - ±8 ±31 ppm
Unipolar Gain Error - ±16 ±62 - ±16 ±62 ppm
Gain Drift (Note 4) - 1 3 - 1 3 ppm/°C

Power Supplies

Power Supply Currents (Normal Mode)

(Note 5)I

I

I

A+

D+

NBV

-

-

-

1.0
90

400

1.4
135
570

-

-

-

1.5
90

525

1.9
135
700

mA

µA
µA

Power Consumption (Note 6)

Normal Mode
Low Power Mode
Standby
Sleep

-

N/A

-

-

6.0

N/A

1.2

500

8.9

N/A

-

-

-

-

-

-

9

5.5

1.2

500

12

7.5

-

-

mW
mW
mW

µW

Power Supply Rejection

Positive Supplies
dc NBV

-

-

120
110

-

-

-

-

120
110

-

-

dB
dB

N
N

Notes: 1. Applies after system calibration at any temperature within -40° C ~ +85° C.

2. Specifications guaranteed by design, characterization, and/or test.

3. Specif ica tio n ap plies to th e de vice on ly and do es not inc lud e an y eff ec ts by ex te rn al para sitic
thermocouples. LSB

: N is 16 for the CS5521/23 and N is 24 for the CS5522/24/28

N

4. Drift over specified temperature range after calibration at power-up at 25° C.

5. Measured with Charge Pump Drive off.

6. All outputs unloaded. All input CMOS levels and the CS5521/23 do not have a low power mode.

DS317F4 5

CS5521/22/23/24/28

ANALOG CHARACTERISTICS (Continued)

Parameter Min Typ Max Unit

Analog Input

Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode
NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV

Range = 1 V , 2.5 V, or 5 V

NBV = AGND Range = 25 mV, 55 mV, or 100 mV (Note 7)

Range = 1 V , 2.5 V, or 5 V

CVF Current on AIN+ or AIN- (Note 8)

Range = 25 mV, 55 mV, or 100 mV
Range = 1 V , 2.5 V, or 5 V

Input Current Drift (Note 8)

Range = 25 mV, 55 mV, or 100 mV - 1 - pA/°C
Input Leakage for Multiplexer when Off - 10 - pA
Common Mode Rejection dc

50, 60 Hz
Input Capacitance - 10 - pF

Voltage Reference Input

Range (VREF+) - (VREF-) 1 2.5 VA+ V
VREF+
VREF- NBV ­CVF Current (Note 8) - 5.0 - n A
Common Mode Rejection dc

50, 60 Hz

Input Capacitance - 16 - pF

System Calibration Specifications

Full Scale Calibration Range (VREF = 2.5V) Bipolar/Unipolar Mode

25 mV

55 mV

100 mV

1 V

2.5 V

5 V
Offset Calibration Range Bipolar/Unipolar Mode

25 mV

55 mV

100 mV (Note 9)

1 V

2.5 V

5 V

-0.150
NBV

1.85

0.0

-

-

-

-

(VREF-)+1

-

-

10
25
40

0.40

1.0

2.0

-

-

-

-

-

-

-

-

-

-

100

10

120
120

-VA+V

110
130

-

-

-

-

-

-

-

-

-

-

-

-

0.950
VA+

2.65
VA+

300

-

-

-

(VREF+)-1

-

-

32.5

71.5

105

1.30

3.25
VA+

±12.5
±27.5

±50

±0.5

±1.25
±2.50

pA
nA

dB
dB

dB
dB

mV
mV
mV

mV
mV
mV

V
V
V
V

V

V
V
V

V
V
V

Notes: 7. For the CS5528, the 25 mV, 55 mV and 100 mV ranges cannot be used unless NBV is powered at -1.8

to -2.5 V

8. See the section of the data sheet which discusses input models. Chop clock is 256 Hz (XIN/128) for
PGIA (programmable gain instrumentation amplifier). XIN = 32.768 kHz.

9. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path.

6 DS317F4

TYPICAL RMS NOISE, CS5521/23 (Notes 10 and 11)

CS5521/22/23/24/28

Output Rate

(Sps)

1.88 1.64 90 nV 148 nV 220 nV 1.8 µV 3.9 µV 7.8 µV

3.76 3.27 122 nV 182 nV 310 nV 2.6 µV 5.7 µV 11.3 µV

7.51 6.55 180 nV 267 nV 435 nV 3.7 µV 8.5 µV 18.1 µV

15.0 12.7 280 nV 440 nV 810 nV 5.7 µV 14 µV 28 µV

30.0 25.4 580 nV 1.1 µV 2.1 µV 18.2 µV 48 µV 96 µV

61.6 (Note 12) 50.4 2.6 µV 4.9 µV 8.5 µV 92 µV 238 µV 390 µV

84.5 (Note 12) 70.7 11 µV 27 µV 43 µV 458 µV 1.1 mV 2.4 mV

101.1 (Note 12) 84.6 41 µV 72 µV 130 µV 1.2 mV 3.4 mV 6.7 mV

Notes: 10. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C.

11. To estimate Peak-to-Peak Noise, multiply RMS noise by 6.6 for all ranges and output rates.

12. For input ranges <100 mV and output rates ≥60Sps, 16.384 kHz chopping frequency is used.

-3 dB Filter
Frequency

25 mV 55 mV 100 mV 1 V 2.5 V 5 V

Input Range, (Bipolar/Unipolar Mode)

TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 (Note 13)

Output Rate

(Sps)

1.88 1.64 16 16 16 16 16 16

3.76 3.27 16 16 16 16 16 16

7.51 6.55 15 16 16 16 16 16

15.0 12.7 15 15 15 16 16 16

30.0 25.4 14 14 14 14 14 14

61.6 (Note 12) 50.4 12 12 12 12 12 12

84.5 (Note 12)70.7999999

101.1 (Note 12)84.6888888

-3 dB Filter
Frequency

25 mV 55 mV 100 mV 1 V 2.5 V 5 V

Input Range, (Bipolar Mode)

Notes: 13. For bipolar mode, the number of bits of Noise Free Resolution is LOG((2XInput Range)/(6.6xRMS

Noise))/LOG(2) rounded to the nearest bit. For unipolar mode, the number of bits of Noise Free
Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the
CS5521/23’s output conversions are 16 bits. Noise free Resolution numbers are based upon
VREF = 2.5 V and XIN = 32.768 kHz. The values will be affected directly by changes in VREF, but the
effects due to changes in the XIN frequency will be minor.

DS317F4 7

TYPICAL RMS NOISE, CS5522/24/28 (Notes 14 and 15)

CS5521/22/23/24/28

Output Rate

(Sps)

1.88 1.64 90 nV 95 nV 140 nV 1.5 µV 3 µV 6 µV

3.76 3.27 110 nV 130 nV 190 nV 2 µV 4 µV 8 µV

7.51 6.55 170 nV 200 nV 275 nV 2.5 µV 6 µV 11.5 µV

15.0 12.7 250 nV 330 nV 580 nV 4.5 µV 10 µV 20 µV

30.0 25.4 500 nV 1 µV 1.5 µV 16 µV 45 µV 85 µV

61.6 (Note 16) 50.4 2 µV 4 µV 8 µV 72 µV 195 µV 350 µV

84.5 (Note 16) 70.7 10 µV 20 µV 35 µV 340 µV 900 µV 2 mV

101.1 (Note 16) 84.6 30 µV 60 µV 105 µV 1.1 mV 3 mV 5.3 mV

Notes: 14. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C.

15. To estimate Peak-to-Peak Noise, multiply RMS noise by 6.6 for all ranges and output rates.

16. For input ranges <100 mV and output rates ≥60 Sps, 16.384 kHz chopping frequency is used.

-3 dB Filter
Frequency

25 mV 55 mV 100 mV 1 V 2.5 V 5 V

Input Range, (Bipolar/Unipolar Mode)

TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 (Note 17)

Output Rate

(Sps)

1.88 1.64 16 17 18 18 18 18

3.76 3.27 16 17 17 17 18 18

7.51 6.55 15 16 17 17 17 17

15.0 12.7 15 16 16 16 16 16

30.0 25.4 14 14 14 14 14 14

61.6 (Note 16) 50.4 12 12 12 12 12 12

84.5 (Note 16) 70.7 10 10 10 10 10 10

101.1 (Note 16)84.6888888

-3 dB Filter
Frequency

25 mV 55 mV 100 mV 1 V 2.5 V 5 V

Input Range, (Bipolar Mode)

Notes: 17. For bipolar mode, the number of bits of Noise Free Resolution is LOG((2XInput Range)/(6.6xRMS

Noise))/LOG(2) rounded to the nearest bit. For unipolar mode, the number of bits of Noise Free
Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the
CS5522/24/28’s output conversions are 24 bits. Noise free Resolution numbers are based upon
VREF = 2.5 V and XIN = 32.768 kHz. The values will be affected directly by changes in VREF, but the
effects due to changes in the XIN frequency will be minor.

8 DS317F4

CS5521/22/23/24/28

5 V DIGITAL CHARACTERISTICS (T

= 25° C; VA+, VD+ = 5 V ±5%; GND = 0;

A

See Notes 2 and 18.))

Parameter Symbol Min Typ Max Unit

High-level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

Low-level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

High-level Output Voltage

All Pins Except CPD and SDO (Note 19)

CPD, I
SDO, I

= -4.0 mA

out

= -5.0 mA

out

Low-level Output Voltage

All Pins Except CPD and SDO, I

CPD, I

SDO, I

= 1.6 mA

out

= 2 mA

out

= 5.0 mA

out

Input Leakage Current I
3-state Leakage Current I
Digital Output Pin Capacitance C

Notes: 18. All measurements performed under static conditions.

19. I

= -100 µA unless stated otherwise. (VOH = 2.4 V @ I

out

V

IH

V

IL

V

OH

V

OL

in

OZ

out

(VD+) - 0.45

= -40 µA.)

out

0.6 VD+

(VD+)-0.5

-

-

-

(VA+) - 1.0
(VD+) - 1.0
(VD+) - 1.0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

0.8

1.5

0.6

-

-

-

0.4

0.4

0.4

V
V
V

V
V
V

V
V
V

V
V
V

-±1±10µA

--±10µA

-9-pF

3 V DIGITAL CHARACTERISTICS (T

= 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0;

A

See Notes 2 and 18.)

Parameter Symbol Min Typ Max Unit

High-level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

Low-level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

High-level Output Voltage

All Pins Except CPD and SDO, I

CPD, I
SDO, I

= -400 µA

out

= -4.0 mA

out

= -5.0 mA

out

Low-level Output Voltage

All Pins Except CPD and SDO, I

CPD, I

SDO, I

= 400 µA

out

= 2 mA

out

= 5.0 mA

out

Input Leakage Current I
3-state Leakage Current I
Digital Output Pin Capacitance C

V

IH

0.6 VD+

(VD+)-0.5

(VD+) - 0.45

V

IL

-

-

-

V

OH

(VA+) - 0.3
(VD+) - 1.0
(VD+) - 1.0

V

OL

-

-

-

in

OZ

out

-±1±10µA

--±10µA

-9-pF

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

0.16 VD+

0.3

0.6

-

-

-

0.3

0.4

0.4

V
V
V

V
V
V

V
V
V

V
V
V

DS317F4 9

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Unit

Modulator Sampling Frequency f
Filter Settling Time to 1/2 LSB (Full-scale Step) t

CS5521/22/23/24/28

s
s

XIN/4 Hz

1/f

out

s

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND = 0 V; See Note 20.)

Parameter Symbol Min Typ Max Unit

DC Power Supplies Positive Digital

Positive Analog

Analog Reference V oltage (VREF+) - (VREF-) VRef

VD+
VA+

diff

2.7

4.75

5.0

5.0

5.25

5.25

1.0 2.5 VA+ V

V
V

Negative Bias Voltage NBV -1.8 -2.1 -2.5 V

Notes: 20. All voltages with respect to ground.

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 20.)

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Note 21)

Positive Digital

Positive Analog
Negative Bias Voltage Negative Potential NBV +0.3 -2.1 -3.0 V
Input Current, Any Pin Except Supplies (Note 22 and 23) I
Output Current I
Power Dissipation (Note 24) PDN - - 500 mW
Analog Input Voltage VREF pins

AIN Pins
Digital Input Voltage V
Ambient Operating Temperature T
Storage Temperature T

VD+
VA+

IN

OUT

V

INR

V

INA

IND

A

stg

-0.3

-0.3

-

-

+6.0
+6.0

V
V

--±10mA

--±25mA

NBV -0.3
NBV -0.3

--(VA+) + 0.3
(VA+) + 0.3VV

-0.3 - (VD+) + 0.3 V

-40 - 85 °C

-65 - 150 °C

Notes: 21. No pin should go more negative than NBV - 0.3 V.

22. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.

23. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.

24. Total power dissipation, including all input currents and output currents.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

10 DS317F4

CS5521/22/23/24/28

SWITCHING CHARACTERISTICS (T

Levels: Logic 0 = 0 V, Logic 1 = VD+; C

= 50 pF.))

L

= 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;

A

Parameter Symbol Min Typ Max Unit

Master Clock Frequency (Note 25)

External Clock or Internal Oscillator (CS5522/24/28)

(CS5521/23)

XIN

30
30

32.768

32.768

200
130

kHz

kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 26)

Any Digital Input Except SCLK

SCLK

Any Digital Output

Fall Times (Note 26)

Any Digital Input Except SCLK

SCLK

Any Digital Output

t

rise

t

fall

-

-

-

-

-

-

-

-

50

-

-

50

1.0

100

-

1.0

100

-

µs
µs
ns

µs
µs
ns

Start-up

Oscillator Start-up Time XTAL = 32.768 kHz (Note 27) t
Power-on Reset Period t

ost

por

-500-ms

- 2006 - XIN
cycles

Serial Port Timing

Serial Clock Frequency SCLK 0 - 2 MHz
SCLK Falling to CS

Falling for continuous running SCLK

t

0

100 - - ns

(Note 28)

Serial Clock Pulse Width High

Pulse Width Low

t

1

t

2

250
250

-

-

-

-

ns
ns

SDI Write Timing

CS

Enable to Valid Latch Clock t
Data Set-up Time prior to SCLK rising t
Data Hold Time After SCLK Rising t

SCLK Falling Prior to CS

Disable t

3
4
5

6

50 - - ns
50 - - ns

100 - - ns
100 - - ns

SDO Read Timing

CS

to Data Valid t
SCLK Falling to New Data Bit t

CS

Rising to SDO Hi-Z t

7
8

9

--150ns

--150ns

--150ns

Notes: 25. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 200 kHz

(CS5522/24/28) or 130 kHz (CS5521/23) can be used for increased throughput.

26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.

28. Applicable when SCLK is continuously running.

Specifications are subject to change without notice.

DS317F4 11

CS

CS

SCLK

CS5521/22/23/24/28

t

0

t

t

t

3

1

t

2

Figure 1. Continuous Running SCLK Timing (Not to Scale)

t

3

6

CS

SDO

SCLK

SCLK

t

7

MSB

MSB

MSB-1 LSBSDI

t

4

Figure 2. SDI Write Timing (Not to Scale)

t

5

t

1

t

2

t

6

t

9

MSB-1 LSB

t

8

t

2

t

1

Figure 3. SDO Read Timing (Not to Scale)

12 DS317F4

2. GENERAL DESCRIPTION

CS5521/22/23/24/28

The CS5521/22/23/24/28 are highly integrated ∆Σ
Analog-to-Digital Converters (ADCs) which use
charge-balance techniques to achieve 16-bit
(CS5521/23) and 24-bit (CS5522/24/28) perfor­mance. The ADCs

come as either two-channel
(CS5521/22), four-channel (CS5523/24), or eight­channel (CS5528) devices, and include a low input
current, chopper-stabilized instrumentation ampli­fier. To permit selectable input spans of 25 mV,
55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs in­clude a PGA (programmable gain amplifier). To
accommodate ground-based thermocouple applica­tions, the devices include a CPD (Charge Pump
Drive) which provides a negative bias voltage to
the on-chip amplifiers.

These devices also include a fourth order DS mod­ulator followed by a digital filter
eight selectable output word rates of

which provides

1.88 Sps,

3.76 Sps, 7.51 Sps, 15 Sps, 30 Sps, 61.6 Sps,

84.5 Sps, and 101.1 Sps

(XIN = 32.768 kHz).

The
devices are capable of producing output update
rates up to 617 Sps when a 200 kHz clock is used
(CS5522/24/28) or up to 401 Sps using a 130 kHz
clock (CS5521/23). Further note that the digital fil-

ters are designed to settle to full accuracy within
one conversion cycle and simultaneously reject
both 50 Hz and 60 Hz interference when operated
at word rates below 30 Sps (assuming a XIN clock
frequency of 32.768 kHz).

To ease communication between the ADCs and a
micro-controller, the converters include an easy to
use three-wire serial interface which is SPI™ and
Microwire™ compatible.

2.1 Analog Input

Figure 4 illustrates a block diagram of the analog in­put signal path inside the CS5521/22/23/24/28. The
front end consists of a multiplexer (break before
make configuration), a chopper-stabilized instru­mentation amplifier with fixed gain of 20X,
coarse/fine charge buffers, and a programmable gain
section. For the 25 mV, 55 mV, and 100 mV input
ranges, the input signals are amplified by the 20X in­strume ntati on amp lifi er. For the 1 V, 2.5 V, and 5 V
input ranges, the instrumentation amplifier is by­passed and the input signals are connected to the
Programmable Gain block via coarse/fine charge
buffers.

NBV

CS5522

IN+

M
U

IN-

X

CS5524

IN+

M

*

U

*

X

*

CS5528

M

*

U

*

X

*

IN+

IN-

IN-

IN+

IN-

Figure 4. Multiplexer Configurations

X20

Programmable

Gain

NBV also supplies the negative
supply voltage for the coarse/fine
change buffers

VREF+

Differential

4th

delta-

modulator

VREF-

order

sigma

Digital

Filter

AIN2+

AIN2-

AIN1+

AIN1-

AIN4+

AIN4-

AIN1+

AIN1-

AIN8+
AIN7+

AIN1+

DS317F4 13

CS5521/22/23/24/28

2.1.1 Instrumentation Amplifier

The instrumentation amplifier is chopper stabilized
and is activated any time conversions are performed
with the low-level input ranges, ≤100 mV. The am­plifier is powered from VA+ and from the NBV
(Negative Bias Voltage) pin allowing the
CS5521/22/23/24/28 to be operated in either of two
analog input configurations. The NBV pin can be bi­ased to a negative voltage between -1.8 V and

-2.5 V, or tied to AGND (for the CS5528, NBV has
to be between -1.8 V and -2.5 V for the ranges below
100 mV when the amplifier is engaged). The com­mon-mode-plus-signal range of the instrumentation
amplifier is 1.85 V to 2.65 V with NBV grounded.
The common-mode-plus-signal range of the instru­mentation amplifier is -0.150 V to 0.950 V with
NBV between -1.8 V to -2.5 V. Whether NBV is
tied between -1.8 V and -2.5 V or tied to AGND,
the (Common Mode + Signal) input on AIN+ and
AIN- must stay between NBV and VA+.

Figure 5 illustrates an analog input model for the
ADCs when the instrumentation amplifier is en­gaged. The CVF (sampling) input current for each
of the analog input pins depends on the CFS1 and
CFS0 (Chop Frequency Select) bits in the configu­ration register (see Configuration Register for de­tails). Note that the CVF current is lowest with the

CFS bits in their default states (cleared to logic 0s).
Further note that the CVF current into the instru­mentation amplifier is less than 300 pA over -40°C
to +85°C. Note that Figure 5 is for input current
modeling only. For physical input capacitance see
‘Input Capacitance’ specification under ANALOG
CHARACTERISTICS. Also refer to Applications
Note AN30 - “Switched-Capacitor A/D Converter

Input Structures” for more details on input models

and input sampling currents.

Note: Residual noise appears in the converter’s baseband for

output word rates greater than 61.6 Sps if the CFS bits
are logic 0 (chop clock = 256 Hz). For word rates of
30 Sps and lower, 256 Sps chopping is recommended,
and for 61.6 Sps, 84.5 Sps and 101.1 Sps word rate set­tings, 4096 Hz chopping is recommended.

2.1.2 Coarse/Fine Charge Buffers

The unity gain buffers are activated any time conver­sions are performed with the high-level inputs rang­es, 1 V, 2.5 V, and 5 V. The un ity gain buf fers are
designed to accommodate rail-to-rail input signals.
The common-mode-plus-signal range for the unity
gain buffer amplifier is NBV to VA+.

Typical CVF (sampling) current for the unity gain
buffer amplifiers is about 10 nA
(XIN = 32.768 kHz, see Figure 6).

25 m V, 55 mV, and 100 mV Ranges

AIN

V≤25 mV

os

i=fV C

osn

CFS1/CFS0 = 00, f = 256 Hz
CFS1/CFS0 = 01, f = 4096 Hz
CFS 1/CFS0 = 10, f = 16.384 kHz
CFS1/CFS0 = 11, f = 1024 Hz

Figure 5. Input Models for AIN+ and AIN- pins, ≤(100

mV Input Ranges

14 DS317F4

C=48pF

V≤25 mV

os

i=fV C

Figure 6. Input Models for AIN+ and AIN- pins, >100

1 V, 2.5 V and 5 V Ranges

AIN

osn

,

φ

Fine

1

φ

Coarse

1

C=20pF

f=32.768 kHz

mV input ranges

CS5521/22/23/24/28

2.1.3 Analog Input Span Considerations

The CS5521/22/23/24/28 is designed to measure
full-scale ranges of 25 mV, 55 mV, 100 mV, 1 V,

2.5 V, and 5 V. Other full scale values can be ac­commodated by performing a system calibration
within the limits specified. See the Calibration sec­tion for more details. Another way to change the
full scale range is to increase or to decrease the
voltage reference to a voltage other than 2.5 . See
the Voltage Reference section for more details.

Three factors set the operating limits for the input
span. They include: instrumentation amplifier satu­ration, modulator 1’s density, and a lower reference
voltage. When the 25 mV, 55 mV, or 100 mV
range is selected, the input signal (including the
common-mode voltage and the amplifier offset
voltage) must not cause the 20X amplifier to satu­rate in either its input stage or output stage. To pre­vent saturation, the absolute voltages on AIN+ and
AIN- must stay within the limits specified (refer to
the Analog Input section). Additionally, the differ­ential output voltage of the amplifier must not ex­ceed 2.8 V. The equation

is the differential input voltage and VOS is the ab­solute maximum offset voltage for the instrumenta­tion amplifier (VOS will not exceed 40 mV). If the
differential output voltage from the amplifier ex­ceeds 2.8 V, the amplifier may saturate, which will
cause a measurement error.

The input voltage into the modulator must not
cause the modulator to exceed a low of 20 percent
or a high of 80 percent 1's density. The nominal
full-scale input span of the modulator (from 30 per­cent to 70 percent 1’s density) is determined by the
VREF voltage divided by the Gain Factor. See
Table 1

to determine if the CS5521/22/23/24/28 is

being used properly. For example, in the 55 mV
range, to determine the nominal input voltage to the
modulator, divide VREF (2.5 V) by the Gain Fac­tor (2.2727).

When a smaller voltage reference is used, the re­sulting code widths are smaller causing the con­verter output codes to exhibit more changing codes
for a fixed amount of noise. Table 1 is based upon
a VREF = 2.5 V. For other values of VREF, the
values in Table 1 must be scaled accordingly.

ABS(VIN + VOS) x 20 = 2.8 V

defines the differential output limit, where

VIN = (AIN+) - (AIN-)

Input Range

± 25 mV
± 55 mV

± 100 mV

± 1.0 V - 2.5V 2.5 ± 1.0 V ± 1.5 V
± 2.5 V - 2.5V 1.0 ± 2.5 V ± 5.0 V
± 5.0 V - 2.5V 0.5 ± 5.0 V 0V, VA+

Note: 1. The converter's actual input range, the delta-sigma's nominal full-scale input, and the delta -sig m a's

(1)

Table 1. Relationship between Full Scale Input, Gain Factors, and Internal Analog

maximum full-scale input all scale directly with the value of the voltage reference. The values in the
table assume a 2.5

2. The 2.8 V limit at the output of the 20X amplifier is the differential output voltage.

Max. Differential Output

20X Amplifier

(2)

2.8 V

(2)

2.8 V

(2)

2.8 V

V VREF voltage.

Signal Limitations

2.1.4 Measuring Voltages Higher than 5 V

Some systems require the measurement of voltages
greater than 5 V. The input current of the instru-

VREF Gain Factor

2.5V 5 ± 0.5 V ± 0.75 V

2.5V 2.272727... ± 1.1 V ± 1.65 V

2.5V 1.25 ± 2.0 V ± 3.0 V

∆-Σ Nominal

Differential Input

(1)

(1)

∆-Σ

Max. Input

DS317F4 15

CS5521/22/23/24/28

mentation amplifier, typically 100 pA, is low
enough to permit large external resistors to divide
down a large external signal without significant
loading. Figure 7 illustrates an example circuit. Re­fer to Application Note 158 for more details on
high-voltage (>5 V) measurement.

2.1.5 Voltage Reference

The CS5521/22/23/24/28 devices are specified for
operation with a 2.5 V reference voltage between
the VREF+ and VREF- pins of the device. For a
single-ended reference voltage, such as the
LT1019-2.5, the reference voltage is input into the
VREF+ pin of the converter and the VREF- pin is
grounded.

The differential voltage between the VREF+ and
VREF- can be any voltage from 1.0 V up to VA+,
however, the VREF+ cannot go above VA+ and the
VREF- pin can not go below NBV.

10

VA+

+

PGIA

-

Ω

0.1 µF

VD+

∆Σ

ADC

±10V

+5 V

1 M

Voltage

Divider

0.1 µF

10 K

VREF+

VREF-

Ω

2.5 V

Ω

Figure 8 illustrates the input models for the VREF
pins. The dynamic input current for each of the pins
can be determined from the models shown.

2.2 Overview of ADC Register Structure and Operating Modes

The CS5521/22/23/24/28 ADCs have an on-chip
controller, which includes a number of user-acces­sible registers. The registers are used to hold offset
and gain calibration results, configure the chip's
operating modes, hold conversion instructions, and
to store conversion data words. Figure 9 depicts a
block diagram of the on-chip controller’s internal
registers for the CS5523/24.

Each of the converters has 24-bit registers to func­tion as offset and gain calibration registers for each
channel. The converters with two channels have
two offset and two gain calibration registers, the
converters with four channels have four offset and
four gain calibration registers, and the eight chan­nel converter has eight offset and eight gain cali­bration registers. These registers hold calibration
results. The contents of these registers can be read
or written by the user. This allows calibration data
to be off-loaded into an external EEPROM. The
user can also manipulate the contents of these reg­isters to modify the offset or the gain slope of the
converter.

The converters include a 24-bit configuration reg­ister of which 17 of the bits are used for setting op­tions such as the conversion mode, operating power
options, setting the chop clock rate of the instru-

PGIA set for

100 mV

+

chop clock = 256 Hz

NBV

≈

-2.1 V

V

Charge Pump

Regulator

1N4148

µ

F

10

+

CPD

0.033

1N4148BAT85

µ

F

Figure 7. Input Ranges Greater than 5 V

DGND

Charge Pump

Circuitry

VREF

V ≤ 25mV

os

i = fV C

osn

f = 32.768 kHz

Figure 8. Input Model for VREF+ and VREF- Pins

Fin e

φ

1

Coarse

φ

2

C = 10pF

16 DS317F4

CS5521/22/23/24/28

mentation amplifier, and providing a number of
flags which indicate converter operation.

A group of registers, called Channel Set-up Regis­ters, are also included in the converters. These reg­isters are used to hold pre-loaded conversion
instructions. Each channel set-up register is 24 bits
wide and holds two 12-bit conversion instructions
(Setups). Upon power-up, these registers can be
initialized by the user’s microcontroller with con­version instructions. The user can then use bits in
the configuration register to choose a conversion
mode.

Several conversion modes are possible. Using the
single conversion mode, an 8-bit command word
can be written into the serial port. The command in­cludes pointer bits which ‘point’ to a 12-bit com­mand in one of the Channel Setup Registers which
is to be executed. The 12-bit commands can be set­up to perform a conversion on any of the input
channels of the converter. More than one of the 12­bit Setups can be used for the same analog input
channel. This allows the user to convert on the
same signal with either a different conversion
speed, a different gain range, or any of the other op­tions available in the Setup Register. The user can

set up the registers to perform conversions using
different conversion options on each of the input
channels.

The ADCs also include multiple-channel conver­sion capability. User bits in the configuration regis­ter of the ADCs can be configured to sequence
through the 12-bit command Setups, performing a
conversion according to the content of each 12-bit
Setup. This channel scanning capability can be
configured to run continuously, or to scan through
a specified number of Setup Registers and stop un­til commanded to continue. In the multiple-channel
scanning modes, the conversion data words are
loaded into an on-chip data FIFO. The converter is­sues a flag on the SDO pin when a scan cycle is
completed so the user can read the FIFO. More de­tails are given in the following pages.

Instructions are provided on how to initialize the
converter, perform offset and gain calibrations, and
to configure the converter for the various conver­sion modes. Each of the bits of the configuration
register and of the Channel Setup Registers is de­scribed. A list of examples follows the description
section. Table 2 can be used to decode all valid
commands (the first 8 bits into the serial port).

4 (24) 4 (24) 4 (12 x 2) 8 x 24

AIN1

AIN2

AIN3

AIN4

Off 1

Off 2

Off 3

Off 4

1 x 24

Configuration

Chop Frequency
Multiple Conversions
Depth Pointer
Loop
Read Convert
Powerdown Modes
Flags
Etc.

Figure 9. CS5523/24 Register Diagram

Gain 1

Gain 2

Gain 3

Gain 4

Setup 1

Setup 3

Setup 5

Setup 7

Setup 2

Setup 4

Setup 6

Setup 8

Latch Outputs
Channel Select
Output Word Rate
PGA Selection
Unipolar/Bipolar

DATA

FIFO

SDO

DS317F4 17