Cirrus Logic CS5509-AS, CS5509-AP Datasheet

CS5509

Single Supply, 16-Bit A/D Converter

Features

l

Delta-Sigma A/D Converter

- 16-bit No Missing Codes

- Linearity Error: ±0.0015%FS

l

Differential Input

- Pin Selectable Unipolar/Bipolar Ranges

- Common Mode Rejection

105 dB @ dc 120 dB @ 50, 60 Hz

l

Either 5 V or 3.3 V Digital Interface

l

On-chip Self-Calibration Circuitry

l

Output Update Rates up to 200/second

l

Ultra Low Power: 1.7 mW

I

Description

The CS5509 is a single supply, 16-bit, serial-output CMOS A/D converter. The CS5509 uses charge-balanced (delta-sigma) techniques to provide a low cost, high resolution measurement at output word rates up to 200 samples per second.

The on-chip digital filter offers superior line rejection at 50 Hz and 60 Hz when the device is operated from a

32.768 kHz clock (outpu t word rate = 20 Hz.). The CS5509 has on-chip self-calibration circuitry which

can be initiated at any time or temperature to ensure minimum offset and full-scale errors.

Low power, high resolution and small package size make the CS5509 an ideal solution for loop-powered transmitters, panel meters, weigh scales and battery powered instrument s.

ORDERING INFORMATION

CS5509-AP -40° to +85° C 16-pin Plastic DIP CS5509-AS -40° to +85° C 16-pin SOIC

VREF+ VREF- DGND VD+

910 12

7

AIN+

8

AIN-

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

Differential

4th-Order

Delta-Sigma

Modulator

Calibration SRAM

VA+

11

Interface

Digital

Filter

Calibration µC

24

CONV XIN

Copyright  Cirrus Logic, I nc. 1997

(All Rights Reserv ed)

13

Serial

Logic

OSC

XOUT

1

CS

14

SCLK

15

SDATA

16

DRDY

3

CAL

6

BP/UP

5

MAR ‘95

DS125F1

1

CS5509

ANALOG CHARACTERISTICS (T

VREF- = 0V; f

= 330kHz; Bipolar Mode; R

CLK

= 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V,

A

= 50Ω with a 10nF to GND at AIN; AIN- = 2.5V; unless

source

otherwise specified.) (Notes 1, 2)

Parameter* Min Typ Max Units

Accuracy

Linearity Error f f f f

Differential Nonlinearity Full Scale Error (Note 3) Full Scale Drift ( Note 4) Unipolar Offset (Note 3) Unipolar Offset Drift (Note 4) Bipolar Offset (Note 3) Bipolar Offset Drift (Note 4) -

= 32.768 kHz

CLK

= 165 kHz

CLK

= 247.5 kHz

CLK

= 330 kHz

CLK

-

0.0015

0.005

±

0.25

±

0.25

±

0.5

±

0.5

±

0.5

±

0.25

±

0.25

0.003

0.0125

±

0.5

±

2

±

%FS

±

%FS

±

%FS

±

%FS

LSB LSB

-LSB

±

2

LSB

-LSB

±

1

LSB

-LSB

Noise (Referred to Output) - 0.16 - LSB

Analog In put

Analog Input Range: Unipolar

Bipolar (Note 5, 6)

Common Mode Rejection: dc f

= 32.768kHz 50,60 Hz (Note 2)

CLK

-

120

0 to +2.5

±2.5

105

-

Volts Volts

-

Input Capacitance - 15 - pF DC Bias Current (Note 1) - 5 - nA

Power Supplies

DC Power Supply Currents: I

Total

I

Analog

I

Digital

-

360 300

60

450

-

Power Dissipation (Note 7) - 1.7 2.25 mW

Power Supply Rejection - 80 - dB

Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5509’s source

impedance requirements. Refer to the text section

Analog Input Impedance Considerations.

2. Specifications guaranteed by design, characterization and/or test.

3. Applies after calibration at the temper ature of interest.

4. Total drift over the specified temperature range since calibration at power-up at 25°C.

5. The input is differential. Therefore, GND ≤ Signal + Common Mode Voltage ≤ VA+.

6. The CS5509 can accept input voltages up to the VA+ analog supply. In unipolar mode the CS5509 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative than 0 Volts. In bipolar mode the CS5509 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all

0’s if the input becomes more negative in magnitude than -((VREF+)-(VREF-)).

7. All outputs unloaded. All inputs CMOS levels.

dB dB

µ µ µ

rms

A A A

* Refer to the Specification Definitions immediately following the Pin Description Section.

Specifications are subject to change without notice.

2 DS125F1

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Units

Modulator Sampling Frequency f Output Update Rate (CONV = 1) f Filter Corner Frequency f Settling Time to 1/2 LSB (FS S tep) t

s

out

-3dB s

CS5509

f

/2 Hz

clk

f

/1622 Hz

clk

f

/1928 Hz

clk

1/f

out

s

5V DIGITAL CHARACTERISTICS (T

= 25°C; VA+, VD+ = 5V ± 10%; GND = 0.)

A

(Notes 2, 8)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

All Pins Except XIN

Low-Level Input Voltage: XIN

All Pins Except XIN High-Level Output Voltage (Note 9) Low-Level Output Voltage I

= 1.6mA

out

Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance

V

IH

V

IH

V

IL

V

IL

V

OH

V

OL

I

in

I

OZ

C

out

Notes: 8. All measurements are performed under static conditions.

9. I

= -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ I

out

3.3V DIGITAL CHARACTERISTICS (T

= 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; GND =

A

0.) (Notes 2, 8)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

All Pins Except XIN

Low-Level Input Voltage: XIN

All Pins Except XIN High-Level Output Voltage I Low-Level Output Voltage I

= -400µA

out

= 400µA

out

Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance

V

IH

V

IH

V

IL

V

IL

V

OH

V

OL

I

in

I

OZ

C

out

3.5

2.0

-

1.5

0.8

V V

(VD+)-1.0 - - V

--0.4V

-

--

±

1

±

10

±

10

µ

A

µ

A

-9-pF

= -40 µA).

out

0.7VD+

0.6VD+

-

0.3VD+

0.16VD+

V V

(VD+)-0.3 - - V

--0.3V

-

--

±1 ±10 µA

±10 µA

-9-pF

DS125F1 3

CS5509

5V SWITCHING CHARACTERISTICS (T

Logic 0 = 0V, Logic 1 = VD+; C

= 50 pF.) (Note 2)

L

= 25°C; VA+, VD+ = 5V ± 10%; Input Levels:

A

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Os cillator:

External Clock:

XIN

f

clk

30.0

Master Clock Duty Cycle Rise Times: Any Digital Input (Note 10)

t

rise

Any Digital Output

Fall Times: Any Digital Input (Note 10)

t

fall

Any Digital Output

Start-Up

Power-On Reset Period (Note 11) Oscillator Start-up Time XTAL=32.768 kHz (Note 12) Wake-up Period (Note 13)

t

wup

res osu

Calibration

CONV Pulse Width (CAL=1) (Note 14) CONV and CAL High to Start of Calibration Start of Calibration to End of Calibration

t

ccw

scl cal

100 - - ns

Conversion

CONV Pulse Width CONV High to Start of Conversion Set Up Time BP/UP stable prior to DRDY

t

cpw

t t

bus

scn

100 - - ns

82/f

falling Hold Time BP/UP stable after DRDY falls Start of Conversion to End of Conversion (Note 15)

t

buh con

Notes: 10. Specified using 10% and 90% points on waveform of interest.

11. An internal power-on-reset is activated whenever power is applied to the device.

12. Oscillator start-up time varies with the crystal parameters. This specifi cation does not apply when using an external clock source.

13. The wake-up period begins once the osc illator starts; or when usi ng an external f power-on reset time elapses.

14. Calibration can also be initi ated by pulsing CAL high whi le CONV=1.

15. Conversion time will be 1622/f

if CONV remains high continuous ly.

clk

30

32.768

-

53.0 330

kHz kHz

40 - 60 %

-

50

20

-

1.0

-

1.0

-

µ

ns

µ

ns

s

-10-ms

- 500 - ms

- 1800/f

clk

--2/f

- 3246/f

clk

--2/f

clk

--s

-s

+200 ns

clk

-s

+200 ns

clk

0--ns

- 1624/f

clk

-

, after the

clk

s

4 DS125F1

CS5509

3.3V SWITCHING CHARACTERISTICS (T

Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Os cillator:

External Clock: Master Clock Duty Cycle Rise Times: Any Digital Input (Note 10)

Any Digital Output Fall Times: Any Digital Input (Note 10)

Any Digital Output

Start-Up

Power-On Reset Period (Note 11) Oscillator Start-up Time XTAL=32.768 kHz (Note 12) Wake-up Period (Note 13)

Calibration

CONV Pulse Width (CAL=1) (Note 14) CONV and CAL High to Start of Calibration Start of Calibration to End of Calibration

Conversion

CONV Pulse Width CONV High to Start of Conversion Set Up Time BP/UP stable prior to DRDY

falling Hold Time BP/UP stable after DRDY falls Start of Conversion to End of Conversion (Note 15)

= 50 pF.) (Note 2)

L

= 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;

A

XIN

f

clk

30.0 30

32.768

-

53.0 330

40 - 60 %

t

wup

t

cpw

t t

t

rise

fall

res

osu

ccw

scl cal

scn

bus

buh con

-

50

20

-

1.0

-

1.0

-

-10-ms

- 500 - ms

- 1800/f

clk

-s

100 - - ns

--2/f

- 3246/f

clk

+200 ns

clk

-s

100 - - ns

--2/f

82/f

clk

--s

+200 ns

clk

0--ns

- 1624/f

clk

-

kHz kHz

µ

s

ns

µ

s

ns

s

DS125F1 5

XIN

XIN/2

CAL

CONV

STATE

t

ccw

t

scl

t

cal

Calibration StandbyStandby

Figure 1. Calibratio n Timing (No t to Scale)

CS5509

XIN

XIN/2

CONV

DRDY

BP/UP

STATE

t

cpw

t

scn

t

con

Conversion StandbyStandby

Figure 2. Conversion Timing (Not to Scale)

bus

t

buh

6 DS125F1

CS5509

5V SWITCHING CHARACTERISTICS (T

= 0V, Logic 1 = VD+; C

Serial Clock Serial Clock Pulse Width High

Access Time: CS Low to data valid (Note 16) Maximum Delay Time: SCLK falling to new SDATA bit

Output Float Delay CS High to output Hi-Z (Note 18)

Notes: 16. If

CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for 2 clock cycles. The propagation delay time may be as great as 2 f guarantee proper clocking of SDATA when usi ng asynchronous sooner than 2 f

17. SDATA transitions on the falli ng edge of SCLK. Note that a rising SCLK must oc cur to enable the serial port shifting mechanism before falli ng edges can be recognized.

CS is returned high before all data bits are output, the SDATA output will complete the current data

18. If bit and then go to high impedance.

= 50 pF.) (Note 2)

L

Parameter Symbol Min Typ Max Units

Pulse Width Low

(Note 17)

SCLK falling to Hi-Z

+ 200 ns after

clk

CS goes low.

= 25°C; VA+, VD+ = 5V ± 10%; Input Levels: Logic 0

A

f

t

t t

sclk

ph

t

pl

csd

dd

fd1 fd2

0-2.5MHz

200 200

-

ns ns

- 60 200 ns

- 150 310 ns

-

60

160

cycles plus 200 ns. To

clk

150 300

ns ns

CS, SCLK(i) should not be taken high

3.3V SWITCHING CHARACTERISTICS (T

Input Levels : Logic 0 = 0V , Logic 1 = V D+; C

Parameter Symbol Min Typ Max Units

Serial Clock Serial Clock Pulse Width High

Access Time: CS Low to data valid (Note 16) Maximum Delay Time: SCLK falling to new SDATA bit

Output Float Delay CS High to output Hi-Z (Note 18)

SCLK falling to Hi-Z

= 50pF.) (Note 2)

L

Pulse Width Low

(Note 17)

= 25°C; VA+ = 5V ± 10%, VD+ = 3.3V ± 5%;

A

f

t

t t

sclk

ph

t

pl

csd

dd

fd1 fd2

0 - 1.25 MHz

200 200

-

- 100 200 ns

- 400 600 ns

-

70

320

150 500

ns ns

DS125F1 7

DRDY

CS5509

CS

SCLK(i)

DRDY

CS

SDATA(o) Hi-Z

SCLK(i)

t

csd

t

csd

MSB-1MSB MSB-2SDATA(o) Hi-Z

t

dd

MSB-1MSB LSB+2 LSB+1 LSB

t

dd

Figure 3. Timing Relationships (Not to Scale)

t

ph

t

pl

t

fd1

t

fd2

8 DS125F1

CS5509

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Positive Digital

Positive Analog Analog Reference Voltage (Note 20) (VREF+)-(VREF-) 1.0 2.5 3.6 V Analog Input Voltage: (Note 6)

Unipolar

Bipolar

Notes: 19. All voltages with respect to ground.

20. The CS5509 can be operated with a reference voltage as low as 100 mV; but with a corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and GND.

VD+ VA+

VAIN VAIN

3.15

4.5

5.0

0

-((VREF+)-(VREF-))--

5.5

(VREF+)-(VREF-) (VREF+)-(VREF-)VV

V V

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Min Typ Max Units

DC Power Supplies: Ground (Note 21)

Positive Digital (Note 22)

Positive Analog Input Current, Any Pin Except Supplies (Notes 23 & 24) Output Current

GND

VD+ VA+

I

in

I

out

Power Dissipation (Total) (Note 25) Analog Input Voltage AIN and VREF pins Digital Input Voltage Ambient Operating Temperature Storage Temperature

V

INA

V

IND

T

A

T

stg

Notes: 21. No pin should go more positive than (VA+)+0.3V.

22. VD+ must always be less than (VA+)+0.3V, and can never exceed +6.0 V.

23. Applies to all pins including continuous overvoltage conditions at the analog i nput (AIN) pin.

24. Transient currents of up to 100mA wi ll not cause SCR l atch-up. Maximum input current for a power supply pin is ± 50 mA.

25. Total power dissipation, including all input currents and output currents.

* WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

-0.3

--

-

(VD+)-0.3

-

± ±

- - 500 mW

-0.3 - (VA+)+0.3 V

-0.3 - (VD+)+0.3 V

-40 - 85

-65 - 150

6.0

6.0 10 25

V V

V mA mA

°

C

°

C

DS125F1 9