Cirrus Logic CS5509-AS, CS5509-AP Datasheet

CS5509

Single Supply, 16-Bit A/D Converter

Features

l

Delta-Sigma A/D Converter

- 16-bit No Missing Codes

- Linearity Error: ±0.0015%FS

l

Differential Input

- Pin Selectable Unipolar/Bipolar Ranges

- Common Mode Rejection

105 dB @ dc
120 dB @ 50, 60 Hz

l

Either 5 V or 3.3 V Digital Interface

l

On-chip Self-Calibration Circuitry

l

Output Update Rates up to 200/second

l

Ultra Low Power: 1.7 mW

I

Description

The CS5509 is a single supply, 16-bit, serial-output
CMOS A/D converter. The CS5509 uses charge-bal­anced (delta-sigma) techniques to provide a low cost,
high resolution measurement at output word rates up to
200 samples per second.

The on-chip digital filter offers superior line rejection at
50 Hz and 60 Hz when the device is operated from a

32.768 kHz clock (outpu t word rate = 20 Hz.).
The CS5509 has on-chip self-calibration circuitry which

can be initiated at any time or temperature to ensure
minimum offset and full-scale errors.

Low power, high resolution and small package size
make the CS5509 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and battery
powered instrument s.

ORDERING INFORMATION

CS5509-AP -40° to +85° C 16-pin Plastic DIP
CS5509-AS -40° to +85° C 16-pin SOIC

VREF+ VREF- DGND VD+

910 12

7

AIN+

8

AIN-

Cirrus Logic, Inc.
Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.crystal.com

Differential

4th-Order

Delta-Sigma

Modulator

Calibration SRAM

VA+

11

Interface

Digital

Filter

Calibration µC

24

CONV XIN

Copyright  Cirrus Logic, I nc. 1997

(All Rights Reserv ed)

13

Serial

Logic

OSC

XOUT

1

CS

14

SCLK

15

SDATA

16

DRDY

3

CAL

6

BP/UP

5

MAR ‘95

DS125F1

1

CS5509

ANALOG CHARACTERISTICS (T

VREF- = 0V; f

= 330kHz; Bipolar Mode; R

CLK

= 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V,

A

= 50Ω with a 10nF to GND at AIN; AIN- = 2.5V; unless

source

otherwise specified.) (Notes 1, 2)

Parameter* Min Typ Max Units

Accuracy

Linearity Error f
f
f
f

Differential Nonlinearity ­Full Scale Error (Note 3) ­Full Scale Drift ( Note 4) ­Unipolar Offset (Note 3) ­Unipolar Offset Drift (Note 4) ­Bipolar Offset (Note 3) ­Bipolar Offset Drift (Note 4) -

= 32.768 kHz

CLK

= 165 kHz

CLK

= 247.5 kHz

CLK

= 330 kHz

CLK

-

-

-

-

0.0015

0.0015

0.0015

0.005

±

0.25

±

0.25

±

0.5

±

0.5

±

0.5

±

0.25

±

0.25

0.003

0.003

0.003

0.0125

±

0.5

±

2

±

%FS

±

%FS

±

%FS

±

%FS

LSB
LSB

-LSB

±

2

LSB

-LSB

±

1

LSB

-LSB

Noise (Referred to Output) - 0.16 - LSB

Analog In put

Analog Input Range: Unipolar

Bipolar (Note 5, 6)

Common Mode Rejection: dc
f

= 32.768kHz 50,60 Hz (Note 2)

CLK

-

-

-

120

0 to +2.5

±2.5

105

-

-

-

Volts
Volts

-

­Input Capacitance - 15 - pF
DC Bias Current (Note 1) - 5 - nA

Power Supplies

DC Power Supply Currents: I

Total

I

Analog

I

Digital

-

-

-

360
300

60

450

-

­Power Dissipation (Note 7) - 1.7 2.25 mW

Power Supply Rejection - 80 - dB

Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5509’s source

impedance requirements. Refer to the text section

Analog Input Impedance Considerations.

2. Specifications guaranteed by design, characterization and/or test.

3. Applies after calibration at the temper ature of interest.

4. Total drift over the specified temperature range since calibration at power-up at 25°C.

5. The input is differential. Therefore, GND ≤ Signal + Common Mode Voltage ≤ VA+.

6. The CS5509 can accept input voltages up to the VA+ analog supply. In unipolar mode the CS5509
will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will
output all 0’s if the input becomes more negative than 0 Volts. In bipolar mode the CS5509 will
output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all

0’s if the input becomes more negative in magnitude than -((VREF+)-(VREF-)).

7. All outputs unloaded. All inputs CMOS levels.

dB
dB

µ
µ
µ

rms

A
A
A

* Refer to the Specification Definitions immediately following the Pin Description Section.

Specifications are subject to change without notice.

2 DS125F1

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Units

Modulator Sampling Frequency f
Output Update Rate (CONV = 1) f
Filter Corner Frequency f
Settling Time to 1/2 LSB (FS S tep) t

s

out

-3dB
s

CS5509

f

/2 Hz

clk

f

/1622 Hz

clk

f

/1928 Hz

clk

1/f

out

s

5V DIGITAL CHARACTERISTICS (T

= 25°C; VA+, VD+ = 5V ± 10%; GND = 0.)

A

(Notes 2, 8)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

All Pins Except XIN

Low-Level Input Voltage: XIN

All Pins Except XIN
High-Level Output Voltage (Note 9)
Low-Level Output Voltage I

= 1.6mA

out

Input Leakage Current
3-State Leakage Current
Digital Output Pin Capacitance

V

IH

V

IH

V

IL

V

IL

V

OH

V

OL

I

in

I

OZ

C

out

Notes: 8. All measurements are performed under static conditions.

9. I

= -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ I

out

3.3V DIGITAL CHARACTERISTICS (T

= 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; GND =

A

0.) (Notes 2, 8)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

All Pins Except XIN

Low-Level Input Voltage: XIN

All Pins Except XIN
High-Level Output Voltage I
Low-Level Output Voltage I

= -400µA

out

= 400µA

out

Input Leakage Current
3-State Leakage Current
Digital Output Pin Capacitance

V

IH

V

IH

V

IL

V

IL

V

OH

V

OL

I

in

I

OZ

C

out

3.5

2.0

-

-

-

-

-

-

-

-

1.5

0.8

V
V

V
V

(VD+)-1.0 - - V

--0.4V

-

--

±

1

±

10

±

10

µ

A

µ

A

-9-pF

= -40 µA).

out

0.7VD+

0.6VD+

-

-

-

-

-

-

-

-

0.3VD+

0.16VD+

V
V

V
V

(VD+)-0.3 - - V

--0.3V

-

--

±1 ±10 µA

±10 µA

-9-pF

DS125F1 3

CS5509

5V SWITCHING CHARACTERISTICS (T

Logic 0 = 0V, Logic 1 = VD+; C

= 50 pF.) (Note 2)

L

= 25°C; VA+, VD+ = 5V ± 10%; Input Levels:

A

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Os cillator:

External Clock:

XIN

f

clk

30.0

Master Clock Duty Cycle
Rise Times: Any Digital Input (Note 10)

t

rise

Any Digital Output

Fall Times: Any Digital Input (Note 10)

t

fall

Any Digital Output

Start-Up

Power-On Reset Period (Note 11)
Oscillator Start-up Time XTAL=32.768 kHz (Note 12)
Wake-up Period (Note 13)

t

t

t

wup

res
osu

Calibration

CONV Pulse Width (CAL=1) (Note 14)
CONV and CAL High to Start of Calibration
Start of Calibration to End of Calibration

t

t

t

ccw

scl
cal

100 - - ns

Conversion

CONV Pulse Width
CONV High to Start of Conversion
Set Up Time BP/UP stable prior to DRDY

t

cpw

t
t

bus

scn

100 - - ns

82/f

falling
Hold Time BP/UP stable after DRDY falls
Start of Conversion to End of Conversion (Note 15)

t

t

buh
con

Notes: 10. Specified using 10% and 90% points on waveform of interest.

11. An internal power-on-reset is activated whenever power is applied to the device.

12. Oscillator start-up time varies with the crystal parameters. This specifi cation does not apply when
using an external clock source.

13. The wake-up period begins once the osc illator starts; or when usi ng an external f
power-on reset time elapses.

14. Calibration can also be initi ated by pulsing CAL high whi le CONV=1.

15. Conversion time will be 1622/f

if CONV remains high continuous ly.

clk

30

32.768

-

53.0
330

kHz
kHz

40 - 60 %

-

-

-

-

50

20

-

-

1.0

-

1.0

-

µ

ns

µ

ns

s

s

-10-ms

- 500 - ms

- 1800/f

clk

--2/f

- 3246/f

clk

--2/f

clk

--s

-s

+200 ns

clk

-s

+200 ns

clk

0--ns

- 1624/f

clk

-

, after the

clk

s

4 DS125F1

CS5509

3.3V SWITCHING CHARACTERISTICS (T

Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Os cillator:

External Clock:
Master Clock Duty Cycle
Rise Times: Any Digital Input (Note 10)

Any Digital Output
Fall Times: Any Digital Input (Note 10)

Any Digital Output

Start-Up

Power-On Reset Period (Note 11)
Oscillator Start-up Time XTAL=32.768 kHz (Note 12)
Wake-up Period (Note 13)

Calibration

CONV Pulse Width (CAL=1) (Note 14)
CONV and CAL High to Start of Calibration
Start of Calibration to End of Calibration

Conversion

CONV Pulse Width
CONV High to Start of Conversion
Set Up Time BP/UP stable prior to DRDY

falling
Hold Time BP/UP stable after DRDY falls
Start of Conversion to End of Conversion (Note 15)

= 50 pF.) (Note 2)

L

= 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;

A

XIN

f

clk

30.0
30

32.768

-

53.0
330

40 - 60 %

t

t

t

t

t

wup

t

t

t

t

cpw

t
t

t

t

rise

fall

res

osu

ccw

scl
cal

scn

bus

buh
con

-

-

-

-

50

20

-

1.0

-

-

1.0

-

-10-ms

- 500 - ms

- 1800/f

clk

-s

100 - - ns

--2/f

- 3246/f

clk

+200 ns

clk

-s

100 - - ns

--2/f

82/f

clk

--s

+200 ns

clk

0--ns

- 1624/f

clk

-

kHz
kHz

µ

s

ns

µ

s

ns

s

DS125F1 5

XIN

XIN/2

CAL

CONV

STATE

t

ccw

t

scl

t

cal

Calibration StandbyStandby

Figure 1. Calibratio n Timing (No t to Scale)

CS5509

XIN

XIN/2

CONV

DRDY

BP/UP

STATE

t

cpw

t

t

scn

t

con

Conversion StandbyStandby

Figure 2. Conversion Timing (Not to Scale)

bus

t

buh

6 DS125F1

CS5509

5V SWITCHING CHARACTERISTICS (T

= 0V, Logic 1 = VD+; C

Serial Clock
Serial Clock Pulse Width High

Access Time: CS Low to data valid (Note 16)
Maximum Delay Time: SCLK falling to new SDATA bit

Output Float Delay CS High to output Hi-Z (Note 18)

Notes: 16. If

CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f
guarantee proper clocking of SDATA when usi ng asynchronous
sooner than 2 f

17. SDATA transitions on the falli ng edge of SCLK. Note that a rising SCLK must oc cur to enable the
serial port shifting mechanism before falli ng edges can be recognized.

CS is returned high before all data bits are output, the SDATA output will complete the current data

18. If
bit and then go to high impedance.

= 50 pF.) (Note 2)

L

Parameter Symbol Min Typ Max Units

Pulse Width Low

(Note 17)

SCLK falling to Hi-Z

+ 200 ns after

clk

CS goes low.

= 25°C; VA+, VD+ = 5V ± 10%; Input Levels: Logic 0

A

f

t

t

t

t
t

sclk

ph

t

pl

csd

dd

fd1
fd2

0-2.5MHz

200
200

-

-

-

-

ns
ns

- 60 200 ns

- 150 310 ns

-

-

60

160

cycles plus 200 ns. To

clk

150
300

ns
ns

CS, SCLK(i) should not be taken high

3.3V SWITCHING CHARACTERISTICS (T

Input Levels : Logic 0 = 0V , Logic 1 = V D+; C

Parameter Symbol Min Typ Max Units

Serial Clock
Serial Clock Pulse Width High

Access Time: CS Low to data valid (Note 16)
Maximum Delay Time: SCLK falling to new SDATA bit

Output Float Delay CS High to output Hi-Z (Note 18)

SCLK falling to Hi-Z

= 50pF.) (Note 2)

L

Pulse Width Low

(Note 17)

= 25°C; VA+ = 5V ± 10%, VD+ = 3.3V ± 5%;

A

f

t

t

t

t
t

sclk

ph

t

pl

csd

dd

fd1
fd2

0 - 1.25 MHz

200
200

-

-

-

-

- 100 200 ns

- 400 600 ns

-

-

70

320

150
500

ns
ns

ns
ns

DS125F1 7

DRDY

CS5509

CS

SCLK(i)

DRDY

CS

SDATA(o) Hi-Z

SCLK(i)

t

csd

t

csd

MSB-1MSB MSB-2SDATA(o) Hi-Z

t

dd

MSB-1MSB LSB+2 LSB+1 LSB

t

dd

Figure 3. Timing Relationships (Not to Scale)

t

ph

t

pl

t

fd1

t

fd2

8 DS125F1

CS5509

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Positive Digital

Positive Analog
Analog Reference Voltage (Note 20) (VREF+)-(VREF-) 1.0 2.5 3.6 V
Analog Input Voltage: (Note 6)

Unipolar

Bipolar

Notes: 19. All voltages with respect to ground.

20. The CS5509 can be operated with a reference voltage as low as 100 mV; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and GND.

VD+
VA+

VAIN
VAIN

3.15

4.5

5.0

5.0

0

-((VREF+)-(VREF-))--

5.5

5.5

(VREF+)-(VREF-)
(VREF+)-(VREF-)VV

V
V

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Min Typ Max Units

DC Power Supplies: Ground (Note 21)

Positive Digital (Note 22)

Positive Analog
Input Current, Any Pin Except Supplies (Notes 23 & 24)
Output Current

GND

VD+
VA+

I

in

I

out

Power Dissipation (Total) (Note 25)
Analog Input Voltage AIN and VREF pins
Digital Input Voltage
Ambient Operating Temperature
Storage Temperature

V

INA

V

IND

T

A

T

stg

Notes: 21. No pin should go more positive than (VA+)+0.3V.

22. VD+ must always be less than (VA+)+0.3V, and can never exceed +6.0 V.

23. Applies to all pins including continuous overvoltage conditions at the analog i nput (AIN) pin.

24. Transient currents of up to 100mA wi ll not cause SCR l atch-up. Maximum input current for a power
supply pin is ± 50 mA.

25. Total power dissipation, including all input currents and output currents.

* WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

-0.3

-0.3

-0.3

--

--

-

(VD+)-0.3

-

-

±
±

- - 500 mW

-0.3 - (VA+)+0.3 V

-0.3 - (VD+)+0.3 V

-40 - 85

-65 - 150

6.0

6.0
10
25

V
V

V
mA
mA

°

C

°

C

DS125F1 9

CS5509

GENERAL DESCRIPTION

The CS5509 is a low power, 16-bit, monolithic
CMOS A/D converter designed specifically for
measurement of dc signals. The CS5509 in­cludes a delta-sigma charge-balance converter, a
voltage reference, a calibration microcontroller
with SRAM, a digital filter a nd a seria l interface.

The CS5509 is optimized to operate from a

32.768 kHz crystal but can be driven by an ex­ternal clock whose frequency is between 30 kHz
and 330 kHz. When the digital filter is operated
with a 32.768 kHz clock, the filter has zeros pre­cisely at 50 and 60 Hz line frequencies and
multiples thereof.

The CS5509 uses a "start convert" command to
start a convolution cycle on the digital filter.
Once the filter cycle is completed, the output
port is updated. When operated with a

32.768 kHz clock the ADC converts and updates
its output port at 20 samples/sec. The output port
operates in a synchronous externally-clocked in­terface format.

tion of this command will not occur until the
complete wake-up period elapses. If no com­mand is given, the device enters the standby
state.

Calibration

After the initial application of power, the
CS5509 must enter the calibration state prior to
performing accurate conversions. During calibra­tion, the chip executes a two-step process. The
device first performs an offset calibration and
then follows this with a gain calibration. The
two calibration steps determine the zero refer­ence point and the full scale reference point of

the converter’s transfer function. From these
points it calibrates the zero point and a gain
slope to be used to properly scale the output
digital codes when doing conversions.

The calibration state is entered whenever the
CAL and CONV pins are high at the same time.
The state of the CAL and CONV pins at power­on are recognized as commands, but will not be
executed until the end of the 1800 clock cycle
wake-up period.

THEORY OF OPERATION

If CAL and CONV become active (high) during
the 1800 clock cycle wake-up time, the con-

Basic Converter Operation

verter will wait until the wake-up period elapses
before executing the calibration. If the wake-up

The CS5509 A/D converter has three operating
states. These are stand-by, calibration, and con­version. When power is first applied, an internal
power-on reset delay of about 10 ms resets all of
the logic in the device. The oscillator must then
begin oscillating before the device can be con­sidered functional. After the power-on reset is

time has elapsed, the converter will be in the
standby mode waiting for instruction and will
enter the calibration cycle immediately if CAL
and CONV become active. The calibration lasts
for 3246 clock cycles. Calibration coefficients
are then retained in the SRAM (static RAM) for
use during conversion.

applied, the device enters the wake-up period for
1800 clock cycles after clock is present. This
allows the delta-sigma modulator and other cir­cuitry (which are operating with very low

The state of BP/UP is ignored during calibration
but should remain stable throughout the calibra­tion period to minimize noise.

currents) to reach a stable bias condition prior to
entering into either the calibration or conversion
states. During the 1800 cycle wake-up period,
the device can accept an input command. Execu-

10 DS125F1

When conversions are performed in unipolar
mode or in bipolar mode, the converter uses the
same calibration factors to compute the digital

CS5509

output code. The only difference is that in bipo­lar mode the on-chip microcontroller offsets the
computed output word by a code value of
8000H. This means that the bipolar measure­ment range is not calibrated from full scale
positive to full scale negative. Instead it is cali­brated from the bipolar zero scale point to full
scale positive. The slope factor is then extended
below bipolar zero to accommodate the negative
input signals. The converter can be used to con­vert both unipolar and bipolar signals by
changing the BP/UP pin. Recalibration is not re­quired when switching between unipolar and
bipolar modes.

At the end of the calibration cycle, the on-chip
microcontroller checks the logic state of the
CONV signal. If the CONV input is low the de­vice will enter the standby mode where it waits
for further instruction. If the CONV signal is
high at the end of the calibration cycle, the con­verter will enter the conversion state and
perform a conversion on the input channel. The
CAL signal can be returned low any time after
calibration is initiated. CONV can also be re­turned low, but it should never be taken low and
then taken back high until the calibration period
has ended and the converter is in the standby
state. If CONV is taken low and then high
again with CAL high while the converter is cali­brating, the device will interrupt the current
calibration cycle and start a new one. If CAL is
taken low and CONV is taken low and then high
during calibration, the calibration cycle will
continue as the conversion command is disre­garded. The state of BP/UP is not important
during calibrations.

If an "end of calibration" signal is desired, pulse
the CAL signal high while leaving the CONV
signal high continuously. Once the calibration is
completed, a conversion will be performed. At
the end of the conversion, DRDY will fall to in­dicate the first valid conversion after the
calibration has been completed.

Conversion

The conversion state can be entered at the end of
the calibration cycle, or whenever the converter
is idle in the standby mode. If CONV is taken
high to initiate a calibration cycle ( CAL also
high), and remains high until the calibration cy­cle is compl eted (CAL is taken low after CON V
transitions high), the converter will begin a con­version upon completion of the calibration
period.

The BP/UP pin is not a latched input. The
BP/UP pin controls how the output word from
the digital filter is processed. In bipolar mode
the output word computed by the digital filter is
offset by 8000H (see Understanding Converter
Calibration). BP/UP can be changed after a con­version is started as long as it is stable for 82
clock cycles of the conversion period prior to
DRDY falling. If one wishes to intermix meas­urement of bipolar and unipolar signals on
various input signals, it is best to switch the
BP/UP pin immediately after DRDY falls and
leave BP/UP stable until DRDY falls again.

The digital filter in the CS5509 has a Finite Im­pulse Response and is designed to settle to full
accuracy in one conversion time.

If CONV is left high, the CS5509 will perform
continuous conversions. The conversion time
will be 1622 clock cycles. If conversion is initi­ated from the standby state, there may be up to
two XIN clock cycles of uncertainty as to when
conversion actually begins. This is because the
internal logic operates at one half the external
clock rate and the exact phase of the internal

clock may be 180° out of phase relative to the
XIN clock. When a new conversion is initiated
from the standby state, it will take up to two
XIN clock cycles to begin. Actual conversion
will use 1624 clock cycles before DRDY goes
low to indicate that the serial port has been up­dated. See the Serial Interface Logic section of

DS125F1 11

CS5509

the data sheet for information on reading data
from the serial port.

In the event the A/D conversion command
(CONV going positive) is issued during the con­version state, the current conversion will be
terminated and a new conversion will be initi­ated.

Voltage Reference

The CS5509 uses a differential voltage referenc e
input. The positive input is VREF+ and the
negative input is VREF-. The voltage between
VREF+ and VREF- can range from 1 volt mini­mum to 3.6 volts maximum. The gain slope will
track changes in the reference without recalibra­tion, accommodating ratiometric applications.

Analog Input Range

Unipolar Input

Voltage

>(VREF - 1.5 LSB) FFFF >(VREF - 1.5 LSB)

VREF - 1.5 LSB

VREF/2 - 0.5 LSB

+0.5 LSB

<(+0.5 LSB) 0000 <(-VREF +0.5 LSB)

Note: Table excludes common mode volt age on the
signal and reference inputs.

Table 1. Output Coding

Output

Codes

FFFF
FFFE VREF - 1.5 LSB

8000

7FFF -0. 5 LSB

0001
0000 -VREF +0.5 LSB

Bipolar Input

Voltage

component which is 0.5 volts above the maxi­mum input of 3.0 (3.5 volts peak; 3.0 volts dc
plus 0.5 volts peak noise) and still accurately
convert the input signal (XIN = 32.768 kHz).
This assumes that the signal plus noise ampli­tude stays within the supply voltages.

The analog input range is set by the magnitude
of the voltage between the VREF+ and VREF­pins. In unipolar mode the input range will
equal the magnitude of the voltage reference. In
bipolar mode the input voltage range will equate
to plus and minus the magnitude of the voltage
reference. While the voltage reference can be as
great as 3.6 volts, its common mode voltage can
be any value as long as the reference inputs
VREF+ and VREF- stay within the supply volt­ages VA+ and GND. The differential input
voltage can also have any common mode value
as long as the maximum signal magnitude stays
within the supply voltages.

The A/D converter is intended to measure dc or
low frequency inputs. It is designed to yield ac­curate conversions even with noise exceeding
the input voltage range as long as the spectral
components of this noise will be filtered out by
the digital filter. For example, with a 3.0 volt
reference in unipolar mode, the converter will
accurately convert an input dc signal up to

3.0 volts with up to 15% overrange for 60 Hz
noise. A 3.0 volt dc signal could have a 60 Hz

The CS5509 converters output data in binary
format when converting unipolar signals and in
offset binary format when converting bipolar
signals. Table 1 outlines the output coding for
both unipolar and bipolar measurement modes.

Converter Performance

The CS5509 A/D converter has excellent linear­ity performance. Calibration minimizes the
errors in offset and gain. The CS5509 device
has no missing code performance to 16-bits.
Figure 4 illustrates the DNL of the CS5509. The
converter achieves Common Mode Rejection
(CMR) at dc of 105 dB typical, and CMR at 50
and 60 Hz of 120 dB typical.

The CS5509 can experience some drift as tem­perature changes. The CS5509 uses
chopper-stabilized techniques to minimize drift.
Measurement errors due to offset or gain drift
can be eliminated at any time by recalibrating
the converter.

12 DS125F1

+1

+1/2

0

DNL (LSB)

-1/2

-1
0 65,535

Figure 4. CS5509 Differential Nonlinearity plot.

32,768

Codes

CS5509

Analog Input Impedance Considerations

The analog input of the CS5509 can be modeled
as illustrated in Figure 5. Capacitors (15 pF
each) are used to dynamically sample each of
the inputs (AIN+ and AIN-). Every half XIN cy­cle the switch alternately connects the capacitor
to the output of the buffer and then directly to
the AIN pin. Whenever the sample capacitor is
switched from the output of the buffer to the
AIN pin, a small packet of charge (a dynamic
demand of current) is required from the input
source to settle the voltage of the sample capaci­tor to its final value. The voltage on the output
of the buffer may differ up to 100 mV from the
actual input voltage due to the offset voltage of
the buffer. Timing allows one half of a XIN
clock cycle for the voltage on the sample capaci­tor to settle to its final v alue.

An equation for the maximum acceptable source
resistance is derived.

−

)

ln

1





Ve +




V

e

15pF(100mv

(

15pF + C

EXT




)





Rs

=

max

2XIN (15pF + C

EXT

This equation assumes that the offset voltage of
the buffer is 100 mV, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable. C

is the combination

EXT

of any external or stray capacitance.
For a maximum error voltage (Ve) of 10 µV in

the CS5509 (1/4LSB at 16-bits), the above equa­tion indicates that when operating from a

32.768 kHz XIN, source resistances up to
110 kΩ are acceptable in the absence of external

capacitance (C

EXT

= 0).

AIN+

V

≤

100 mV

os

AIN-

V

≤

100 mV

os

Figure 5. Analog Input Model

DS125F1 13

+

-

+

-

15 pF

Internal
Bias
Voltage

15 pF

The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input imped­ance applies to the voltage reference inputs as
well.

-20

-40

-60

-80

-100

Attenuation (dB)

-120

-140

-160

X1
X2

0

0
0

40

402.8380805.66

Frequency (Hz)

X1 = 32.768kHz
X2 = 330.00kHz

XIN = 32.768 kHz

120

160

1208.5

1611.3

200

2014.2

240

2416.9

CS5509

Frequency Notch Frequency Minimum

(Hz) D epth (Hz) Att enua tion

(dB) (dB)

50 125.6 50±1% 55.5

60 126.7 60±1% 58.4
100 145.7 100±1% 62.2
120 136.0 120±1% 68.4
150 118.4 150±1% 74.9
180 132.9 180±1% 87.9
200 102.5 200±1% 94.0
240 108.4 240±1% 104.4

Figure 6. Filter Magnitude Plot to 260 Hz

0

-20

-40

-60

-80

Attenuation (dB)

-100

-120

-140
0 5 10 15 20 25 30 35 40 45 50

Flatness

Frequency

1
2

3
4

5
6
7
8

9
10
17

dB

-0.010

-0.041

-0.093

-0.166

-0.259

-0.374

-0.510

-0.667

-0.846

-1.047

-3.093

Frequency (Hz)

XIN = 32.768 kHz

Figure 7. Filter Magnitude Plot to 50 Hz

Digital Filter Characteristics

The digital filter in the CS5509 is the combina­tion of a comb filter and a low pass filter. The
comb filter has zeros in its transfer function
which are optimally placed to reject line interfer­ence frequencies (50 and 60 Hz and their
multiples) when the CS5509 is clocked at

32.768 kHz. Figures 6, 7 and 8 illustrate the
magnitude and phase characteristics of the filter.

Table 2. Filter Notch Attenuation (XIN = 32.768 kHz)

180

135

90

45

0

-45

Phase (Degrees)

-90
XIN = 32.768 kHz

-135

-180
0 5 10 1 5 2 0 25 30 35 40 45 50

Frequen cy (Hz)

Figure 8. Filter Phase Plot to 50 Hz

Figure 6 illustrates the filter attenuation from dc
to 260 Hz. At exactly 50, 60, 100, and 120 Hz
the filter provides over 120 dB of rejection. Ta­ble 2 indicates the filter attenuation for each of
the potential line interference frequencies when
the converter is operating with a 32.768 kHz
clock. The converter yields excellent attenuation
of these interference frequencies even if the fun-

damental line frequency should vary ± 1% from

14 DS125F1

CS5509

its specified frequency. The -3dB corner fre­quency of the filter when operating from a

32.768 kHz clock is 17 Hz. Figure 8 illustrates
that the phase characteristics of the filter are pre­cisely linear phase.

If the CS5509 is operated at a clock rate other
than 32.768 kHz, the filter characteristics, in­cluding the comb filter zeros, will scale with the
operating clock frequency. Therefore, optimum
rejection of line frequency interference will oc­cur with the CS5509 running at 32.768 kHz.

Anti-Alias Con sideratio ns for Spec tral
Measurement Applications

Input frequencies greater than one half the out­put word rate (CONV = 1) may be aliased by
the converter. To prevent this, input signals
should be limited in frequency to no greater than
one half the output word rate of the converter
(when
CONV =1). Frequencies close to the modulator
sample rate (XIN/2) and multiples thereof may
also be aliased. If the signal source includes
spectral components above one half the output
word rate (when CONV = 1) these components
should be removed by means of low-pass filter­ing prior to the A/D input to prevent aliasing.
Spectral components greater than one half the
output word rate on the VREF inputs (VREF+
and VREF-) may also be aliased. Filtering of the
reference voltage to remove these spectral com­ponents from the reference voltage is desirable.

Crystal Oscillator

The CS5509 is designed to be operated using a

32.768 kHz "tuning fork" type crystal. One end
of the crystal should be connected to the XIN
input. The other end should be attached to
XOUT. Short lead lengths should be used to
minimize stray capacitance.

Over the industrial temperature range (-40 to
+85 °C) the on-chip gate oscillator will oscillate

with other crystals in the range of 30 kHz to 53
kHz. The chip will operate with external clock
frequencies from 30 kHz to 330 kHz over the in­dustrial temperature range. The 32.768 kHz
crystal is normally specified as a time-keeping
crystal with tight specifications for both initial
frequency and for drift over temperature. To
maintain excellent frequency stability, these
crystals are specified only over limited operating

temperature ranges (i.e. -10 °C to +60 °C) by the
manufacturers. Applications of these crystals
with the CS5509 does not require tight initial
tolerance or low tempco drift. Therefore, a lower
cost crysta l with looser init ial tolerance a nd tem­pco will generally be adequate for use with the
CS5509. Also check with the manufacturer
about wide temperature range application of
their standard crystals. Generally, even those
crystals specified for limited temperature range
will operate over much larger ranges if fre­quency stability over temperature is not a
requirement. The frequency stability can be as

bad as ±3000 ppm over the operating tempera­ture range and still be typically better than the
line frequency (50 Hz or 60 Hz) stability over
cycle-to-cycle during the course of a day.

Serial Interface Logic

The digital filter in the CS5509 takes 1624 clock
cycles to compute an output word once a con­version begins. At the end of the conversion
cycle, the filter will attempt to update the serial
port. Two clock cycles prior to the update
DRDY will go high. When DRDY goes high
just prior to a port update it checks to see if the
port is either empty or unselected (CS = 1). If
the port is empty or unselected, the digital filter
will update the port with a new output word.
When new data is put into the port DRDY will
go low.

DS125F1 15

CS5509

Reading Serial Data

SDATA is the output pin for the serial data.
When CS goes low after new data becomes
available (DRDY goes low), the SDATA pin
comes out of Hi-Z with the MSB data bit pre­sent. SCLK is the input pin for the serial clock.
If the MSB data bit is on the SDATA pin, the
first rising edge of SCLK enables the shifting
mechanism. This allows the falling edges of
SCLK to shift subsequent data bits out of the
port. Note that if the MSB data bit is output and
the SCLK signal is high, the first falling edge of
SCLK will be ignored because the shifting
mechanism has not become activated. After the
first rising edge of SCLK, each subsequent fall­ing edge will shift out the serial data. Once the
LSB is present, the falling edge of SCLK will
cause the SDATA output to go to Hi-Z and
DRDY to return high. The serial port register
will be updated with a new data word upon the
completion of another conversion if the serial
port has been emptied, or if the CS is inactive
(high).

VD+ or GND pins; VD+ must remain more
positive than the GND pin.

Figure 9a illustrates the System Connection Dia­gram for the CS5509. Note that all supply pins

are bypassed with 0.1 µF capacitors and that the
VD+ digital supply is derived from the VA+
supply. Figure 9b illustrates the CS5509 operat­ing from a +5V analog supply and +3.3V digital
supply.

When using separate supplies for VA+ and
VD+, VA+ must be established first. VD+
should never become more positive than VA+
under any operating condition. Remember to in­vestigate transient power-up conditions, when
one power supply may have a faster rise time.

CS can be operated asynchronously to the
DRDY signal. The DRDY signal need not be
monitored as long as the CS signal is taken low
for at least two XIN clock cycles plus 200 ns
prior to SCLK being toggled. This ensures that
CS has gained control over the serial port.

Power Supplies and Grounding

The analog and digital supply pins to the
CS5509 are brought out on separate pins to
minimize noise coupling between the analog and
digital sections of the chip. In the digital section
of the chip the supply current flows into the
VD+ pin and out of the GND pin. As a CMOS
device, the CS5509 requires that the supply volt­age on the VA+ pin always be more positive
than the voltage on any other pin of the device.
If this requirement is not met, the device can
latch-up or be damaged. In all circumstances the
VA+ voltage must remain more positive than the

Schematic & Layout Review Service

Confirm Optimum

Confirm Optimum

Schematic & Layout

Schematic & Layout

Before Building Your Board.

Before Building Your Board.

For Our Free Review Service

For Our Free Review Service

Call Applications Engineering.

Call Applications Engineering.

Call:[phone]

16 DS125F1

10

CS5509

Ω

+5V
Analog
Supply

Analog

Signal

Voltage
Reference

+

-

Optional

Clock

Source

32.768 kHz

0.1

14

15

1
2

3
6

16

0.1

µ

F

Serial

Data

Interface

Control

Logic

µ

F

10

4

5

7
8

9

11

XIN

XOUT

CS5509

AIN+
AIN-

VREF+

VREF-

13

VD+VA+

SCLK

SDATA

CS

CONV

CAL

BP/UP

DRDY

GND

12

Figure 9a. System Connection Diagram Using a Single Supply

DS125F1 17

+5V
Analog
Supply

Note: VD+ must never be more positive than VA+

0.1

µ

F

11

13

VD+VA+

0.1

µ

F

CS5509

+3.3V to +5V

Digital

Supply

Analog

Signal

Voltage
Reference

Optional

+

-

Clock

Source

32.768 kHz

10

4

5

7
8

9

XIN

XOUT

CS5509

AIN+
AIN-

VREF+

VREF-

GND

SCLK

SDATA

CS

CONV

CAL

BP/UP

DRDY

14

15

1
2

3
6

16

Serial

Data

Interface

Control

Logic

12

Figure 9b. System Connection Diagram Using Split Supplies

18 DS125F1

PIN DESCRIPTIONS*

CS5509

CHIP SELECT CS DRDY DATA READY

CONVERT CONV SDATA SERIAL DATA OUTPUT

CALIBRATE CAL SCLK SERIAL CLOCK INPUT

CRYSTAL IN XIN VD+ POSITIVE DIGITA L POWER

CRYSTAL OUT XOUT GND GROUND

BIPOLAR/UNIPOLAR BP/
DIFFERENTIAL ANALOG INPUT AIN+ VREF- VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT AIN- VREF+ VOLTAGE REFERENCE INPUT

*Pinout applies to both PDIP and SOIC

UP VA+ POSITIVE ANALO G POWER

1
2
3
4

5
6

7
8

16
15
14
13
12
11
10

9

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 4, 5.

A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).

Serial Output I/O

CS - Chip Select, Pin 1.

This input allows an external device to access the serial port.

DRDY - Data Ready, Pin 16.

Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).

SDATA - Serial Data Output, Pin 15.

SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK. Data is output MSB first and advances to the next data bit on the falling
edges of SCLK. SDATA will be in a high impedance state when not transmitting data.

SCLK - Serial Clock Input, Pin 14.

A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin
must not be allowed to float.

DS125F1 19

Control Input Pins

CAL - Calibrate, Pin 3.

When taken high the same time that the CONV pin is taken high the c onverter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.

CONV - Convert, Pin 2.

The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If
CONV is held high (CAL low) the converter will do continuous conversions.

BP/UP - Bipolar/Unipolar, Pin 6.

The BP/UP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.

Measurement and Reference Inputs

AIN+, AIN- - Differential Analog Inputs, Pins 7, 8.

Analog differential inputs to the delta-sigma modulator.

CS5509

VREF+, VREF- - Differential Voltage Reference Inputs, Pins 9, 10.

A differential voltage reference on these pins operates as the voltage reference for the
converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.

Power Supply Connections

VA+ - Positive Analog Power, Pin 11.

Positive analog supply voltage. Nominally +5 volts.

VD+ - Positive Digital Power, Pin 13.

Positive digital supply voltage. Nominally +5 volts or +3.3 volts.

GND - Ground, Pin 12.

Ground.

20 DS125F1

SPECIFICATION DEFINITIONS

Linearity Error

The deviation of a code from a straight line which connects the two endpoints of the A/D
Converter transfer function. One endpoint is located 1/2 LSB below the first code transition
and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in
percent of full-scale.

Differential Nonlinearity

The deviation of a code’s width from the ideal width. Units in LSBs.

Full Scale Error

The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3⁄2 LSB].
Units are in LSBs.

Unipolar Offset

The deviation of the first code transition from the ideal (1⁄2 LSB above the voltage on the AIN­pin.) when in unipolar mode (BP/UP low). Units are in LSBs.

CS5509

Bipolar Offset

The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1⁄2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs

DS125F1 21

CS5509

APPENDIX

The following companies provide 32.768 kHz crystals in many package varieties and temperature
ranges.

Fox Electronics
5570 Enterprise Parkway
Fort Meyers, FL 33905
[phone]

Micro Crystal Division / SMH
702 West Algonquin Road
Arlington Heights, IL 60005
[phone]

SaRonix
4010 Transport Street
Palo Alto, California 94303
[phone]

Statek
512 North Main
Orange, California 92668
[phone]

IQD Ltd.
North Street
Crewkerne
Somerset TA18 7AK
England
01460 77155

Taiwan X’ta l Corp.
5F. No. 16, Sec 2, Chung Yang S. RD.
Reitou, Taipei, Taiwan R. O. C.
Tel: [phone]
Fax: [phone]

Interquip Limited
24/F Million Fortune Industrial Centre
34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: [phone]
Fax: [phone]

S& T Enterprises, Ltd.
Rm 404 Blk B
Sea View Estate
North Point, Hong Kong
Tel: [phone]
Fax: [phone]

Mr. Darren Mcleod
Hy-Q International Pty. Ltd.
12 Rosella Road,
FRANKSON, 3199
Victoria, Australia
Tel: [phone]
Fax: [phone]

Mr. Pierre Hersberger
Microcrystal/DIV. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
065 53 05 57

22 DS125F1

CDB5509

Evaluation Board for the CS5509 A/D Converter

Features

l

Operation with on-board 32.768 kHz crystal
or off-board clock source

l

DIP Switch Selectable:

- BP/UP mode

l

On-board precision voltage reference

l

Access to all digital control pins

I

AIN+

Description

The CDB5509 is a circuit board designed to provide
quick evaluation of the CS5509 A/D converter.

The board prov ides buffered digital signals, an on-board
precision volt age reference, o ptions for usi ng an externa l
clock, and a momentary switch to initiate calibra tion.

ORDERING INFORMATION

CDB5509 Evaluation Board

CS5509

B

U

F
F

E

R
S

H

E

A
D
E
R

AIN-

VREF

Cirrus Logic, Inc.
Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.crystal.com

+5V

Copyright  Cirrus Logic, I nc. 1998

GND

(All Rights Reserv ed)

CLKIN

MAR ‘95

DS125DB1

23

Introduction

The CDB5509 evaluation board provides a quick
means of testing the CS5509 A/D converter. The
CS5509 converter requires a minimal amount of
external circuitry. The evaluation board comes
configured with the A/D converter chip operat­ing from a 32.768 kHz crystal and with an
off-chip precision 2.5 volt reference. The board
provides access to all of the digital interface pins
of the CS5509 chip.

Evaluation Board Overview

CDB5509

Most applications will not require the buffer ICs
for proper operation.

To put the board in operation, select either bipo­lar or unipolar mode with DIP switch S2. Then
press the CAL pushbutton after the board is
powered up. This initiates calibration of the con­verter which is required before measurements
can be taken. With CONV high (S2-3 open) the
converter will convert continuously. Figure 3 il­lustrates the CAB5509 adapter board. The
CAB5509 translates a CS5505 pinout to a
CS5509 pinout.

The board provides a complete means of making
the CS5509 A/D converter chip function. The
user must provide a means of taking the output
data from the board in serial format and using it
in his system.

Figure 1 illustrates the schematic for the board.
The board comes configured for the A/D con­verter chip to operate from the 32.768 kHz
watch crystal. A BNC connector for an external
clock is provided on the board. To connect the
external BNC source to the converter chip, a cir­cuit trace must be cut. Then a jumper must be
inserted in the proper holes to connect the XIN
pin of the converter to the input line from the

BNC. The BNC input is terminated with a 50Ω
resistor. Remove this resistor if driving from a
logic gate. See the schematic in Figure 1.

The board comes with the A/D converter VREF+
and VREF- pins hard-wired to the 2.5 volt
bandgap voltage reference IC on the board.

Figures 4 and 5 illustrate the evaluation board
layout while Figure 6 illustrates the component
placement (silkscreen) of the evaluation board.

All of the control pins of the CS5509 are avail­able at the J1 header connector. Buffer ICs U2
and U3 are used to buffer the converter for inter­face to off-board circuits. The buffers are used
on the evaluation board only because the exact
loading and off-board circuitry is unknown.

24 DS125DB1

DS125DB1 25

+5V

GND

External

VREF

AIN+

AIN-

6.8V

+5

C9

0.1µF

+

-

D1

R31
100k

R12

100k

+5

C5

C2

+

10 µF 0.1 µF

2

6

LT1019

-2.5 V
4

402

R4

402 C15

R13

R8

5

25k

AGND

DGND

C8

0.1 µF

CLKIN

R22

+5

CAL

C11

0.01 µF

C17

µ

0.1

F

R23

100k

R24

100k

R25

100k

R16

11 12

U3D

13

R10 20k

VD+
1

U2A

2

45

U2B

67

U2C

10 9

U2D

U2E

U2F

8

VD+

100k

R11
100k

R17

3

47k

R18

VD+

R19

100k

47k

VD+

R20
100k

1211

1514

56

U3B

VD+

4

14

U3A

3

1

R21

47k

VD+

7

U3C

8

9

10

2

Note: Buffers not required for general applications.

kHz

VD+

C10

0.1 µF

13

VD+

3

CAL

TP10

2

CONV

TP9

1

CS

TP8

TP7

TP11

16

DRDY

TP12

15

SDATA

TP13

14

SCLK

TP14

6

BP/UP

GND

12

Y1

+5

C7

µ

0.1

F

R27

1K

200

1A

R26

1K

1B

2A

2B

3A

3B

0.01 µF

R3
50

R2

C19

10nF

C20
10nF

TP6

TP15

10

9

7

8

VREF+

VREF-

AIN+

AIN-

R9

10

11

VA+

U1

CS5509

XIN

XOUT

45

32.768

10

VD+

0.1 µF

C18

R1

100k

+

C16
10 µF

S2

+5
+5
DRDY

SCLK
SDATA

J2

CAL

CONV

CS

A0

A1

DRDY

SDATA

SCLKO

SCLKI

BP/UP

J1

U2 74HC4050
U3 74HC125

A1
A0

CONV
BP/UP

CDB5509

Figure 1. ADC Connections

CDB5509

CS DRDY

CONV SDATA

CAL SCLK

XIN VD+

XOUT GND

UP VA+

BP/

AIN+ VREF-

AIN- VREF+

Figure 2. CS5509 Pin Layout

1
2
3
4

5
6

7
8

(Top View)

1

16
15
14
13
12
11
10

9

24

116

89

1312

Figure 3. CAB 5509 A dapter Board

26 DS125DB1

CDB5509

Figure 4. Top Ground Plane Layer (NOT TO SCALE)

DS125DB1 27

CDB5509

Figure 5. Bottom Trace Layer (NOT TO SCALE)

28 DS125DB1

CDB5509

A

A

CDB5509

Figure 6. Silk Screen Layer (NOT TO SCALE)

DS125DB1 29