Cirrus Logic CS5509 User Manual

Single-supply, 16-bit A/D Converter

Differential

4th order

delta-sigma

modulator

VD+

13

VA+VREF+9VREF-

10

AIN-

8

AIN+

7

Calibration

SRAM

Serial

Interface

Logic

Digital

Filter

XIN4XOUT

5

CONV

2

Calibration µC

OSC

CAL

3 6

BP/UP

CS

1

DRDY

16

SDATA

15

SCLK

14

11

GND

12

CS5509

Features

 Delta-sigma A/D Converter

- 16-bit, No Missing Codes

- Linearity Error: ±0.0015%FS



Differential Input

- Pin-selectable Unipolar/Bipolar Ranges

- Common Mode Rejection

105 dB @ dc 120 dB @ 50, 60 Hz



Either 5V or 3.3V Digital Interface

 On-chip Self-calibration Circuitry  Output Update Rates up to 200/second  Ultra Low Power: 1.7 mW

I

Description

The CS5509 is a single-supply, 16-bit, serial-output CMOS A/D converter. The CS5509 uses charge-balanced (delta-sigma) techniques to provide low-cost, high-resolution measurements at output word rates up to 200 samples per second.

The on-chip digital filter offers superior line rejection at 50Hz and 60Hz when the device is operated from a

32.768 kHz clock (output word rate = 20 Sps). The CS5509 has on-chip self-calibration circuitry which

can be initiated at any time or temperature to ensure minimum offset and full-scale errors.

Low power, high resolution, and small package size make the CS5509 an ideal solution for loop-powered transmitters, panel meters, weigh scales, and battery powered instruments.

ORDERING INFORMATION

CS5509-ASZ -40 °C to +85 °C 16-pin SOIC Lead Free

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2009

SEP ‘09

DS125F3

1

CS5509

ANALOG CHARACTERISTICS (T

VREF- = 0V; f

= 32.768 kHz; Bipolar Mode; R

CLK

= 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; VREF+ = 2.5V,

A

= 40 Ω with a 10 nF to GND at AIN; AIN- = 2.5V; unless oth-

source

erwise specified.) (Notes 1 and 2)

Parameter* Min Typ Max Unit

Accuracy

Linearity Error f

= 32.768 kHz

CLK

f

= 165 kHz

CLK

f

= 247.5 kHz

CLK

f

= 330 kHz

CLK

-

0.0015

0.005

0.003

0.0125

± %FS ± %FS ± %FS

± %FS Differential Nonlinearity - ±0.25 ±0.5 LSB Full-scale Error (Note 3) - ±0.25 ±2 LSB Full-scale Drift (Note 4) - ±0.5 - LSB Unipolar Offset (Note 3) - ±0.5 ±2 LSB Unipolar Offset Drift (Note 4) - ±0.5 - LSB Bipolar Offset (Note 3) - ±0.25 ±1 LSB Bipolar Offset Drift (Note 4) - ±0.25 - LSB

Noise (Referred to Output) - 0.16 -

LSB

Analog Input

Analog Input Range Unipolar

Bipolar (Notes 5 and 6)

Common Mode Rejection dc f

= 32.768 kHz 50, 60 Hz (Note 2)

CLK

-

120

0 to +2.5

±2.5

105

-

V V

dB

dB Input Capacitance - 15 - pF DC Bias Current (Note 1) - 5 - nA

Power Supplies

DC Power Supply Currents I

Total

I

Analog

I

Digital

-

350 300

60

450

-

µA

µA Power Dissipation (Note 7) - 1.7 2.25 mW Power Supply Rejection - 80 - dB

rms

Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5509's source

impedance requirements. Refer to the text section Analog Input Impedance Considerations.

2. Specifications guaranteed by design, characterization and/or test.

3. Applies after calibration at the temperature of interest.

4. Total drift over the specified temperature range since calibration at power-up at 25 °C.

5. The input is differential. Therefore, GND ≤ Signal + Common Mode Voltage ≤ VA+.

6. The CS5509 can accept input voltages up to the VA+ analog supply. In unipolar mode the CS5509 will output all 1's if the dc input magnitude ((AIN+) - (AIN-)) exceeds ((VREF+) - (VREF-)) and will output all 0's if the input becomes more negative than 0 Volts. In bipolar mode the CS5509 will output all 1's if the dc input magnitude ((AIN+) - (AIN-)) exceeds ((VREF+) - (VREF-)) and will output all 0's if the input becomes more negative in magnitude than -((VREF+) - (VREF-)).

7. All outputs unloaded. All inputs CMOS levels.

* Refer to the Specification Definitions immediately following the Pin Description Section.

2 DS125F3

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Unit

Modulator Sampling Frequency Output Update Rate (CONV = 1) Filter Corner Frequency Settling Time to 1/2 LSB (FS Step)

f

out

f

-3dB

CS5509

f

clk

f

clk

/2

clk

/1622 /1928

1/f

out

Hz Hz Hz

s

f

s

t

s

5V DIGITAL CHARACTERISTICS (T

= 25 °C; VA+, VD+ = 5V ±5%; GND = 0) (Notes 2 and 8)

A

Parameter Symbol Min Typ Max Unit

High-level Input Voltage XIN

All Pins Except XIN

V

IH

Low-level Input Voltage XIN

All Pins Except XIN

High-level Output Voltage (Note 9) Low-level Output Voiltage I

= 1.6 mA V

out

Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance

V

IL

V

OH

OL

I

in

I

OZ

C

out

Notes: 8. All measurements are performed under static conditions.

9. I

3.3V DIGITAL CHARACTERISTICS (T

= -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4 V at I

out

= 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; GND = 0)

A

(Notes 2 and 8)

Parameter Symbol Min Typ Max Unit

High-level Input Voltage XIN

All Pins Except XIN

V

IH

Low-level Input Voltage XIN

All Pins Except XIN

High-level Output Voltage (Note 9) Low-level Output Voltage I

= 1.6 mA V

out

Input Leakage Current 3-state Leakage Current Digital Output Pin Capacitance

V

IL

V

OH

OL

I

in

I

OZ

C

out

3.5

2.0

-

1.5

0.8

V V

(VD+) -1.0 - - V

--0.4V

-±1±10µA

--±10µA

-9-pF

= -40 µA).

out

0.7 VD+

0.6 VD+

-

0.3 VD+

0.16 VD+

V V

(VD+) -0.3 - - V

--0.3V

-±1±10µA

--±10µA

-9-pF

Specifications are subject to change without notice

DS125F3 3

CS5509

5V SWITCHING CHARACTERISTICS (T

Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

= 50 pF) (Note 2)

L

= 25 °C; VA+, VD+ = 5V ±5%;

A

Parameter Symbol Min Typ Max Unit

Master Clock Frequency Internal Oscillator

External Clock

XIN

f

clk

30.0 30

32.768

-

53.0 330

kHz

kHz Master Clock Duty Cycle 40 - 60 % Rise Times Any Digital Input (Note 10)

Any Digital Output

Fall Time Any Digital Input (Note 10)

Any Digital Output

t

rise

t

fall

-

50

20

-

1.0

-

1.0

-

Start-Up

Power-On Reset Period (Note 11) Oscillator Start-up Time XTAL = 32.768 kHz (Note 12) Wake-up Period (Note 13)

t

res osu wup

-10-ms

-500-ms

-

1800/f

clk

-s

Calibration

CONV Pulse Width (CAL = 1) (Note 14) CONV and CAL High to Start of Calibration Start of Calibration to End of Calibration

t

ccw

t

scl

cal

100 - - ns

+200

clk

2/f

clk

-s

--

-

3246/f

Conversion

CONV Pulse Width CONV High to Start of Conversion Set Up Time BP/UP Hold Time BP/UP

stable prior to DRDY falling

stable after DRDY falls

Start of Conversion to End of Conversion (Note 15)

t

cpw

t

scn

t

bus

t

buh

t

con

100 - - ns

+200

--

82/f

clk

2/f

clk

--s

0--ns

-

1624/f

clk

-s

µs ns

ns

Notes: 10. Specified using 10% and 90% points on waveform of interest.

11. An internal power-on-reset is activated whenever power is applied to the device.

12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when using an external clock source.

13. The wake-up period begins once the oscillator starts; or when using an external f

, after the power-on

clk

reset time elapses.

14. Calibration can also be initiated by pulsing CAL high while CONV=1.

15. Conversion time will be 1622/f

if CONV remains high continuously.

clk

4 DS125F3

CS5509

3.3V SWITCHING CHARACTERISTICS (T

Levels: Logic 0 = 0V, Logic 1 = VD+; C

= 50 pF) (Note 2)

L

= 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; Input

A

Parameter Symbol Min Typ Max Unit

Master Clock Frequency Internal Oscillator

External Clock

XIN

f

clk

30.0 30

32.768

-

53.0 330

kHz

kHz Master Clock Duty Cycle 40 - 60 % Rise Times Any Digital Input (Note 10)

Any Digital Output

Fall Time Any Digital Input (Note 10)

Any Digital Output

t

rise

fall

-

50

20

-

1.0

-

1.0

-

Start-Up

Power-On Reset Period (Note 11) Oscillator Start-up Time XTAL = 32.768 kHz (Note 12) Wake-up Period (Note 13)

t

res

t

osu

t

wup

-10-ms

-500-ms

-

1800/f

clk

-s

Calibration

CONV Pulse Width (CAL = 1) (Note 14) CONV and CAL High to Start of Calibration Start of Calibration to End of Calibration

t

ccw

scl cal

100 - - ns

+200

clk

2/f

clk

-s

--

-

3246/f

Conversion

CONV Pulse Width CONV High to Start of Conversion Set Up Time BP/UP Hold Time BP/UP

stable prior to DRDY falling

stable after DRDY falls

Start of Conversion to End of Conversion (Note 15)

t

cpw

t

scn

t

bus

t

buh

t

con

100 - - ns

+200

--

82/f

clk

2/f

clk

--s

0--ns

-

1624/f

clk

-s

µs ns

ns

DS125F3 5

CS5509

t

ccw

XIN

Calibration StandbyStandby

t

scl

t

cal

XIN/2

STATE

CAL

CONV

Figure 1. Calibration Timing (Not to Scale)

XIN

XIN/2

t

buh

Conversion StandbyStandby

CONV

STATE

t

scn

t

con

DRDY

BP/UP

t

bus

t

cpw

Figure 2. Conversion Timing (Not to Scale)

6 DS125F3

CS5509

5V SWITCHING CHARACTERISTICS (T

0V, Logic 1 = VD+; C

= 50 pF) (Note 2)

L

= 25 °C; VA+, VD+ = 5V ±5%; Input Levels: Logic 0 =

A

Parameter Symbol Min Typ Max Unit

Serial Clock Serial Clock Pulse Width High

Pulse Width Low

Access Time CS

Low to data valid (Note 16)

f

t

sclk

ph

t

pl

csd

0-2.5MHz

200 200

-

ns ns

-60200ns

Maximum Delay Time (Note 17)

t t

t

dd

fd1 fd2

-150310ns

-

60

160

150 300

ns ns

SCLK falling to new SDATA bit Output Float Delay CS

High to output Hi-Z (Note 18)

SCLK falling to Hi-Z

Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high

for 2 clock cycles. The propagation delay time may be as great a s 2 f proper clocking of SDATA when using asynchronous CS 2 f

+ 200 ns after CS goes low.

clk

, SCLK(i) should not be taken high sooner than

cycles plus 200 ns. To guarantee

clk

17. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial port shifting mechanism before falling edges can be recognized.

18. If CS

is returned high before all data bits are output, the SDATA output will complete the current data

bit and then go to high impedance.

3.3V SWITCHING CHARACTERISTICS (T

Levels: Logic 0 = 0V, Logic 1 = VD+; C

= 50 pF) (Note 2)

L

= 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; Input

A

Parameter Symbol Min Typ Max Unit

Serial Clock Serial Clock Pulse Width High

Pulse Width Low

Access Time CS

Low to data valid (Note 16)

Maximum Delay Time (Note 17) SCLK falling to new SDATA bit

Output Float Delay CS

High to output Hi-Z (Note 18)

SCLK falling to Hi-Z

f

t

t t

sclk

ph

t

pl

csd

dd

fd1 fd2

0 - 1.25 MHz

200 200

-

ns ns

-100200ns

-400600ns

-

70

320

150 500

ns ns

DS125F3 7

CS5509

SCLK(i)

MSB-1MSB MSB-2SDATA(o) Hi-Z

MSB-1MSB LSB+2 LSB+1 LSB

SCLK(i)

SDATA(o) Hi-Z

t

fd1

t

csd

t

dd

t

ph

t

pl

t

dd

t

csd

CS

DRDY

t

fd2

Figure 3. Timing Relationships (Not to Scale)

8 DS125F3