Cirrus Logic CS5508 User Manual

CS5505/6/7/8

Copyright  Cirrus Logic, Inc. 2009

http://www.cirrus.com

CS5505/6/7/8

Very Low Power, 16-bit & 20-bit A/D Converters

OCT ‘09

DS59F7

Very Low Power, 16-Bit and 20-Bit A/D Converters

Features

Description

l Very Low Power Consumption

- Single supply +5 V operation: 1.7 mW

- Dual supply ±5 V operation: 3.2 mW

l Offers superior performance to VFCs and

multi-slope integrating ADCs

l Differential Inputs

- Single-channel (CS5507/8) and Four-channel (CS5505/6) pseudo-differential versions

l Either 5 V or 3.3 V Digital Interface l Linearity Error:

- ±0.0015% FS (16-bit CS5505/7)

- ±0.0007% FS (20-bit CS5506/8)

l Output update rates up to 100 Sps l Flexible Serial Port l Pin-Selectable Unipolar/Bipolar Ranges

I

The CS5505/6/7/8 are a family of low power CMOS A/D converters which are ideal for measuring low-frequency signals representing physical, chemical, and biological processes.

The CS 5507/8 have single-channel differential anal

og and reference inputs while the CS5505/6 have four pseudo-differ

ential analog input channels. The CS5505/7 have a 16-bit output word. The CS5506/8 have a 20-bit output word.The CS5505/6/7/8 sample

ommand up to 100 Sps

upon c

.

The on-chip digital filter offers superior li ne rejection at 50 and 60 Hz when the device is operated from a

32.768 kHz clock (output word rate = 20 Sps).

The CS 5505/6/7/8 include on-chip self-calibration circuitry whi

ch c

an be initiated at any time or temperature

to ensure minimum offset and full-scale errors.

The CS5505/6/7/8 serial port offers two general-purpose modes for the direct interface to shift r egisters or synchr microcontroll

s serial ports of indust

onou

ers.

ry-standard

ORDERING INFORMATION

See page 30.

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

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DS59F4

1

CS5505/6/7/8

2 DS59F7

CS5505/6/7/8

ANALOG CHARACTERISTICS

±

3.3V

5%; VREF+ = 2.5V(external); VREF- = 0V; f

(TA = T

to T

MIN

= 32.768kHz; Bipolar Mode; R

CLK

; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =

MAX

= 1kΩ with a 10nF

source

to AGND at AIN; Anal og input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)

CS5505/7-A CS5507-S

Parameter* Min Typ Max Min Typ Max Units

Specified Temperature Range -40 to +85 -55 to +125

°

C

Accuracy

Linearity Error - 0.0015 0.003 - 0.0015 0.003

Differential Nonlinearity -

Full Scale Error (Note 3) -

Full Scale Drift (Note 4) -

Unipolar Offset (Note 3) -

Unipolar Offset Drift (Note 4) -

Bipolar Offset (Note 3) -

Bipolar Offset Drift (Note 4) -

±

0.25

±

0.25

± ± ±

±

0.25

±

0.25

0.5

±

0.5

±

2

--

±

2

--

±

1

--

-

±

0.25

±

0.5

±

2

±

1

±

1

±

0.5

±

0.5

±

0.5

±

-LSB

±

-LSB

±

-LSB

±

%FS

LSB

16

LSB

16

2

4

2

Noise (Referred to Output) - 0.16 - - 0.16 - LSB-

rms

16

Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the

master clock frequency. Both sour ce resistance and shunt capacitance are therefore critical in determining the CS5505/6/7/8’s source impedance requirements. For more information refer to the text section

Analog Input Impedance Consi derations.

2. Specifications guaranteed by desi gn, characterization and/or test.

3. Applies after calibration at the temperature of interest.

4. Total drift over the specified temperature range since calibration at power-up at 25°C. Recalibration at any temperature will remove these errors.

Unipolar Mode Bipolar Mode

mV LSB’s % FS ppm FS LSB’s % FS ppm FS

10 0.26 0.0004 4 0.13 0.0002 2 19 0.50 0.0008 8 0.26 0.0004 4 38 1.00 0.0015 15 0.50 0.0008 8 76 2.00 0.0030 30 1.00 0.0015 15

152 4.00 0.0061 61 2.00 0.0030 30

VREF = 2.5V

CS5505/7; 16-Bit Unit Conversion Factors

* Refer to the Specification Definitions immediately following the Pin Description Section.

Specifications are subject to change without notice.

2 DS59F7

CS5505/6/7/8

DS59F7 3

CS5505/6/7/8

ANALOG CHARACTERISTICS

3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; f

(TA = T

to T

MIN

= 32.768kHz ; Bipolar Mode; R

CLK

; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =

MAX

source

= 1kΩ with a

10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)

CS5506/8-B CS5508-S

Parameter* Min Typ Max Min Typ Max Units

Specified Temperature Range -40 to +85 -55 to +125

°

Accuracy

Linearity Error - 0.0007 0.0015 - 0.0015 0.003

Differential Nonlinearity

±

%FS

Bits

(No Missing Codes) 20 - - 20 - -

Full Scale Error (Note 3) -

Full Scale Drift (Note 4) -

Unipolar Offset (Note 3) -

Unipolar Offset Drift (Note 4) -

Bipolar Offset (Note 3) -

Bipolar Offset Drift (Note 4) -

±

4

±

8

±

8

±

8

±

4

±

4

±

32

--

±

32

--

±

16

--

-

±

8

±

32

±

16

±

16

±

8

±

8

±

32

±

64

±

32

LSB

-LSB

LSB

-LSB

LSB

-LSB

Noise (Referred to Output) - 2.6 - - 2.6 - LSB-

rms

C

20

Unipolar Mode Bipolar Mode

mV LSB’s % FS ppm FS LSB’s % FS ppm FS

0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12

1.192 0.50 0.0000477 0.47 0.26 0.0000238 0.24

2.384 1.00 0.0000954 0.95 0.50 0.0000477 0.47

4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95

9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91 VREF = 2.5V

CS5506/8; 20-Bit Unit Conversion Factors

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Units

f

Modulator Sampling Frequency f Output Update Rate (CONV = 1) f Filter Corner Frequency f

Settling Time to

1

⁄2 LSB (FS Step)

s

out

-3dB

t

s

/2 Hz

clk

f

/1622 Sps

clk

f

/1928 Hz

clk

1/f

out

s

DS59F7 3

CS5505/6/7/8

4 DS59F7

CS5505/6/7/8

ANALOG CHARACTERISTICS

3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; f 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)

Parameter* Min Typ Max Min Typ Max Units

Specified Temperature Range -40 to +85 -55 to +125

(TA = T

to T

MIN

= 32.768kHz ; Bipolar Mode; R

CLK

CS5505/7 CS5506/8 CS5507/8-S

; VA+ = 5V

MAX

±

10%; VA- = -5V ± 10%; VD+ =

= 1kΩ with a

source

°

Analog Input

Analog Input Range: Unipolar (VAIN+)-(VAIN-) Bi polar (Note 5)

Common Mode Rejection: dc

50, 60 Hz (Note 6)-120

Off Channel Isolation - 120 - - 120 - dB

Input Capacitance - 15 - - 15 - pF

DC Bias Current (Note 1) - 5 - - 5 - nA

0 to +2.5

±

2.5

105

-

0 to +2.5

±

2.5

-

120

105

-

Volts Volts

dB dB

Voltage Reference (Output)

VREFOUT Voltage - (VA+)-2.5 - - (VA+)-2.5 - Volts

VREFOUT Voltage Tolerance - - 4.0 - - 4.0 %

C

VREFOUT Voltage Temperature Coefficient - 60 - - 60 -

VREFOUT Line Regulation - 1.5 - - 1.5 - mV/Volt

VREFOUT Output Voltage Noise

0.1 to 10 Hz

VREFOUT: Sour ce Current

Sink Current

-50- -50-

-

3

50

-

50

ppm/°C

µ

V

p-p

3

µ

A

µ

A

Power Supplies

DC Power Supply Currents: I

Power Dissipation: (Note 7)

SLEEP inactive SLEEP active

Power Supply Rejection: Positive Supplies

Negative Supplies

Notes: 5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and

VA- supply voltages.

6. XIN = 32.768 kHz. Guaranteed by design and / or characterization.

7. All outputs unloaded. Al l inputs CMOS levels. SLEEP mode controlled by M/SLP pin. SLEEP active = M/SLP pin at (VD+)/2 input level.

Total

I

Analog

I

Digital

-

340 300

40

3.2 5

80 80

450

-

4.5 10

-

340 300

40

3.2 10

80 80

450

-

4.5 25

-

µ

A

µ

A

µ

A

mW

µ

W

dB dB

4 DS59F7

CS5505/6/7/8

DS59F7 5

CS5505/6/7/8

5V DIGITAL CHARACTERISTICS

(TA = T

MIN

to T

; VA+VD+ = 5V ± 10%; VA-= -5V ± 10%;

MAX

DGND = 0.) All measurements below are performed under static conditions. (Note 2)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

M/SLP

All Pins Except XIN and M/SLP

Low-Level Input Voltage: XIN

M/SLP

All Pins Except XIN and M/SLP

M/SLP SLEEP Active Threshold (Note 8) V

High-Level Output Voltage (Note 9) V

Low Level Output Vol tage I

= 1.6 mA V

out

Input Leakage Current I

3-State Leakage Current I

Digital Output Pi n Capacitance C

V V V

SLP

OH

OL

in

OZ

out

IH IH IH

IL IL IL

3.5

0.9VD+

2.0

-

1.5

0.1VD+

0.8

V V V

0.45VD+ 0.5VD+ 0.55VD+ V

(VD+)-1.0 - - V

--0.4V

-110

--

±10µ

µ

A

-9-pF

Notes: 8. Under normal operation this pin should be tied to VD+ or DGND. Anytime the voltage on the M/SLP

pin enters the SLEEP active threshold range the device will enter the power down condition. Returning to the active state r equires elapse of the power-on reset period, the oscillator to start-up, and elapse of the wake-up period.

9. I

= -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ I

out

= -40 µA).

out

3.3V DIGITAL CHARACTERISTICS

(TA = T

MIN

to T

; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;

MAX

VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

M/SLP

All Pins Except XIN and M/SLP

Low-Level Input Voltage: XIN

M/SLP

All Pins Except XIN and M/SLP

M/SLP SLEEP Active Threshold (Note 8) V

High-Level Output Voltage I

Low Level Output Vol tage I

= -400 µA

out

= 400 µA

out

Input Leakage Current I

3-State Leakage Current I

Digital Output Pi n Capacitance C

V

VIH

V

VIL

V

SLP

V

OZ

IH

OH

OL

in

out

0.7VD+

0.9VD+

0.6VD+

IL

-

IL

-

0.3VD+

0.1VD+

0.16VD+

0.43VD+ 0.45VD+ 0.47VD+ V

(VD+)-0.3 - - V

--0.3V

-110

--

-9-pF

-

±10 µA

V V V

µA

DS59F7 5

CS5505/6/7/8

6 DS59F7

CS5505/6/7/8

5V SWITCHING CHARACTERISTICS

VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

(TA = T

to T

MIN

MAX;

= 50 pF.) (Note 2)

L

VA+, VD+ = 5V ± 10%;

Parameter Symbol Min Typ Max Units

Master Clock Frequency: Internal Oscillator: -A,B

-S

External Clock:

XIN

or

f

clk

30.0

30

32.768

-

53.0

34.0

163

kHz

Master Clock Duty Cycle 40 - 60 %

Rise Times: Any Digital Input (Note 10)

Any Digital Output

Fall Times: Any Digital Input (Note 10)

Any Digital Output

t

rise

t

fall

-

50

20

-

1.0

-

1.0

-

Start-Up

Power-On Reset Period (Note 11) t

Oscillator Start-up Time XTAL=32.768 kHz (Note 12) t

Wake-up Period (Note 13) t

res

osu

wup

-10-ms

- 500 - ms

- 1800/f

clk

-s

Calibration

CONV Pulse Width (CAL = 1) (Note 14) t

CONV and CAL High to Start of Calibration t

Start of Calibration to End of Calibration t

ccw

scl

cal

100 - - ns

--2/f

- 3246/f

clk

clk+200

-s

Conversion

µ

ns

µ

ns

s

Set Up Time A0, A1 to CONV High t

Hold Time A0, A1 after CONV High t

CONV Pulse Width t

CONV High to Start of Conversion t

Set Up Time BP/UP stable prior to DRDY falling t

Hold Time BP/UP stable after DRDY falls t

Start of Conversion to End of Conversion (Note 15) t

sac

hca

cpw

scn

bus

buh

con

Notes: 10. Specified using 10% and 90% points on waveform of interest.

11. An internal power-on-reset is activated whenever power is applied to the device, or when coming out of a SLEEP state.

12. Oscillator start-up time var ies with the crystal parameters. This specification does not apply when using an external clock source.

13. The wake-up period begins once the oscillator starts; or when using an external f

, after the power-on reset time elapses.

clk

14. Calibration can also be initiated by pulsing CAL high while CONV=1.

15. Conversion time will be 1622/f

if CONV remains high continuously.

clk

50 - - ns

100 - - ns

--2/f

82/f

clk

--s

+200 ns

clk

0--ns

- 1624/f

clk

-s

6 DS59F7

CS5505/6/7/8

DS59F7 7

CS5505/6/7/8

3.3V SWITCHING CHARACTERISTICS

(TA = T

MIN

to T

VA+ = 5V ± 10%;

MAX

VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+ ; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Master Clock Frequency: Internal Oscillator: -A,B

-S

External Clock:

XIN

or

f

clk

30.0

30

32.768

-

53.0

34.0

163

kHz

Master Clock Duty Cycle 40 - 60 %

Rise Times: Any Digital Input (Note 10)

Any Digital Output

Fall Times: Any Digital Input (Note 10)

Any Digital Output

t

rise

t

fall

-

50

20

-

1.0

-

1.0

-

Start-Up

Power-On Reset Period (Note 11) t

Oscillator Start-up Time XTAL=32.768 kHz (Note 12) t

Wake-up Period (Note 13) t

res

osu

wup

-10-ms

- 500 - ms

- 1800/f

clk

-s

Calibration

CONV Pulse Width (CAL = 1) (Note 14) t

CONV and CAL High to Start of Calibration t

Start of Calibration to End of Calibration t

ccw

scl

cal

100 - - ns

--2/f

- 3246/f

clk

200 ns

clk+

-s

Conversion

µ

ns

µ

ns

s

Set Up Time A0, A1 to CONV High t

Hold Time A0, A1 after CONV High t

CONV Pulse Width t

CONV High to Start of Conversion t

Set Up Time BP/UP stable prior to DRDY falling t

Hold Time BP/UP stable after DRDY falls t

Start of Conversion to End of Conversion (Note 15) t

sac

hca

cpw

scn

bus

buh

con

50 - - ns

100 - - ns

--2/f

82/f

clk

--s

+200 ns

clk

0--ns

- 1624/f

clk

-s

DS59F4 7

XIN

CS5505/6/7/8

8 DS59F7

XIN/2

CS5505/6/7/8

CAL

CONV

STATE

XIN

XIN/2

A0, A1

CONV

DRDY

t

ccw

t

scl

t

cal

Calibration StandbyStandby

Figure 1. Calibration Timing (Not to Scale)

t

sac

t

cpw

t

hca

BP/UP

t

STATE

t

scn

t

con

Conversion StandbyStandby

bus

t

buh

Figure 2. Conversion Timing (Not to Scale)

8 DS59F4

CS5505/6/7/8

DS59F7 9

CS5505/6/7/8

5V SWITCHING CHARACTERISTICS

(TA = T

MIN

VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

Parameter Symbol Min Typ Max Units

SSC Mode (M/SLP = VD+)

Access Time: CS Low to SDATA out (DRDY = low)

DRDY falling to MSB (CS = low)

SDATA Delay Time: SCLK falling to next SDATA bit t

SCLK Delay Time SDATA MSB bit to SCLK rising t

Serial Clock (Out) Pulse Width High

Pulse Width Low

Output Float Delay: CS high to output Hi-Z (Note 16)

SCLK rising to SDATA Hi-Z

SEC Mode (M/SLP = DGND)

Serial Clock (In) f

Serial Clock (In) Pulse Width High

Pulse Width Low

Access Time: CS Low to data valid (Note 17) t

Maximum Delay time: (Note 18)

SCLK falling to new SDATA bit t

Output Float Delay: CS high to output Hi-Z (Note 16)

SCLK falling to SDATA Hi-Z

Notes: 16. If

CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the

current data bit and then go to high impedance.

CS is activated asynchronously to DRDY, CS will not be recognized if it occ urs when DRDY is high

17. If for 2 clock cycles. The propagation delay time may be as great as 2 f guarantee proper clocking of SDATA when using asynchronous sooner than 2 f

+ 200 ns after

clk

CS goes low.

18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial port shifting mechanism before falling edges can be recognized.

to T

= 50 pF.) (Note 2)

L

t

csd1

t

dfd

dd1

cd1

t

ph1

t

pl1

t

fd1

t

fd2

sclk

t

ph2

t

pl2

csd2

dd2

t

fd3

t

fd4

VA+, VD+ = 5V ± 10%;

MAX;

-

- 80 250 ns

-1/f

-

0-2.5MHz

200 200

- 60 200 ns

- 150 310 ns

-

CS, SCLK(i) should not be taken high

-

2/f

clk

1/f

clk

1/f

clk

-

1/f

clk

-

60

160

cycles plus 200 ns. T o

clk

2/fclk 3/f

clk

-ns

-

2/f

clk

-

150 300

ns ns

DS59F7 9

CS5505/6/7/8

10 DS59F7

CS5505/6/7/8

3.3V SWITCHING CHARACTERISTICS

(TA = T

MIN

to T

5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

Parameter Symbol Min Typ Max Units

SSC Mode (M/SLP = VD+)

Access Time: CS Low to SDATA out (DRDY = low)

DRDY falling to MSB (CS = low)

SDATA Delay Time: SCLK falling to next SDATA bit t

SCLK Delay Time SDATA MSB bit to SCLK rising t

Serial Clock (Out) Pulse Width High

Pulse Width Low

Output Float Delay: CS high to output Hi-Z (Note 16)

SCLK rising to SDATA Hi-Z

t

csd1

t

dfd

dd1

cd1

t

ph1

t

pl1

t

fd1

t

fd2

SEC Mode (M/SLP = DGND)

Serial Clock (In) f

Serial Clock (In) Pulse Width High

Pulse Width Low

Access Time: CS Low to data valid (Note 17) t

sclk

t

ph2

t

pl2

csd2

Maximum Delay time: (Note 18)

SCLK falling to new SDATA bit t

Output Float Delay: CS high to output Hi-Z (Note 16)

SCLK falling to SDATA Hi-Z

dd2

t

fd3

t

fd4

VA+ = 5V ± 10%; VD+ = 3.3V

MAX

= 50 pF.) (Note 2)

L

-

2/f

-

clk

- 265 400 ns

-1/f

-

1/f 1/f

1/f

clk

clk clk

-

clk

0 - 1.25 MHz

200 200

-

- 100 200 ns

- 400 600 ns

-

70

320

±

2/fclk 3/f

clk

ns ns

-ns

2/f

150 500

-

clk

-

ns ns

10 DS59F4

XIN

CS5505/6/7/8

DS59F7 11

XIN/2

CONV

CS

t

csd1

CS5505/6/7/8

STATE

DRDY

SCLK(o)

SDATA(o)

Hi-Z

STATE (CONV held high)

DRDY

CS

SDATA(o) Hi-Z

SCLK(i)

StandbyStandby Conversion Conversion

t

ph1

t

pl1

Conversion1

t

cd1

MSB MSB-1

Conversion2

t

dd1

Figure 3. Timing Relationships; SSC Mode (Not to Scale)

t

csd2

t

dd2

MSB-1MSB MSB-2

t

fd2

LSB+1 LSB

t

fd3

Hi-Z

DRDY

CS

t

SDATA(o) Hi-Z

SCLK(i)

csd2

t

dd2

MSB-1MSB LSB+2 LSB+1 LSB

t

ph2

t

pl2

t

fd4

Figure 4. Timing Rela tionships; SEC Mode ( Not to Scale)

DS59F4 11

CS5505/6/7/8

12 DS59F7

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19)

Parameter Symbol Min Typ Max Units

CS5505/6/7/8

DC Power Supplies: Positive Digital

(VA+)-(VA-) Positive Analog Negative Analog

Analog Reference Voltage (Note 20) (VREF+)-(VREF-) 1.0 2.5 3.6 V

Analog Input Voltage: (Note 21)

Unipolar Bipolar

Notes: 19. All voltages with r espect to ground.

20. The CS5505/6/7/8 can be operated with a reference voltage as low as 100 mV; but with a corresponding reduction in nois e-free resolution. The common mode voltage of the voltage reference may be any value as long as +V REF and -VREF remain inside the supply values of VA+ and VA-.

21. The CS5505/6/7/8 can acc ept input voltages up to the analog supplies (VA+ and VA-). In unipolar mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ( (AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative than 0 Volts. In bipolar mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative in magnitude than

-((VREF+)-(VREF-)).

VD+ V

diff

VA+

VA-

VAIN VAIN

-((VREF+)-(VREF-))--

3.15

4.75

4.5 0

0

5.0 10

5.0

-5.0

(VREF+)-(VREF-)

+((VREF+)-(VREF-))VV

5.5 11 11

-5.5

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Min Typ Max Units

V V V V

DC Power Supplies: Digital Ground (Note 22)

Positive Digital (Note 23) Positive Analog Negative Analog (VA+)-(VA-) (VA+)-(VD+)

Input Current, Any Pin Except Supplies (Notes 24, 25) I

Analog Input Voltage AIN and VREF pins V

Digital Input Voltage V

Ambient Operating Temperature T

Storage Temperature T

Notes: 22. No pin should go more positive than (VA+)+0.3V.

23. VD+ must always be less than (VA+)+0.3 V,and can never exceed 6.0V.

24. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.

25. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power

supply pin is ± 50 mA.

* WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

DGND

VD+ VA+

VA-

V

diff1

V

diff2

in

INA

IND

A

stg

-0.3

+0.3

-0.3

--

(VA-)-0.3 - (VA+)+0.3 V

-0.3 - (VD+)+0.3 V

-55 - 125

-65 - 150

-

(VD+)-0.3

6.0 or VA+

12.0

-6.0

12.0

±

10

V V V V V V

mA

°

C

°

C

12 DS59F4