Cirrus Logic CS5490 User Manual

Download

CS5490

VDDA

GNDA

RES ET

Calculation

Temperature

Sensor

VREF+

Voltage

Reference

VDDD

VREF-

System

Clock

CS5490

MODE

Clock

Generato r

XIN XOUT

UART

Serial

Interfac e

4th Order 

Modulator

Digital

Filter

HPF

Option

IIN +

IIN-

PGA

Digital

Filter

HPF

Optio n

10x

VIN+

VIN-

4th Order 

Modulator

Configurable

Digital Output

Two Channel Energy Measurement IC

Features

• Superior Analog Performance with Ultra-low Noise Level & High SNR

• Energy Measurement Accuracy of 0.1% over a 4000:1 Dynamic Range

• Two Independent 24-bit, 4 Modulators for Voltage and Current Measurements

• Configurable Digital Output for Energy Pulses, Interrupt, zero-crossing, and Energy Direction

• Supports Shunt Resistor, CT, and Rogowski Coil Current Sensors

• On-chip Measurements/Calculations:

- Active, Reactive, and Apparent Power

- RMS Voltage and Current

- Power Factor and Line Frequency

- Instantaneous Voltage, Current, and Power

• Overcurrent, Voltage Sag, and Voltage Swell Detection

• Ultra-fast On-chip Digital Calibration

• Configurable No-load Threshold for Anti-creep

• Internal Register Protection via Checksum and Write Protection

• UART Serial Interface

• On-chip Temperature Sensor

• On-chip Voltage Reference (25ppm/°C Typ.)

• Single 3.3 V Power Supply

• Ultra-fine Phase Compensation

• Low Power Consumption: <13 mW

• Power Supply Configurations:

- GNDA = 0 V, VDDA: +3.3 V

• Low-cost 16-pin SOIC Package

-order, Delta-Sigma

Description

The CS5490 is a high-accuracy, two-channel, energy measurement analog front end.

The CS5490 incorporates independent 4 alog-to-digital converters for both channels, reference circuitry, and the proven EXL signal processing core to provide active, reactive, and apparent energy measurement. In addition, RMS and power factor calculations are available. Calculations are output via a configurable energy pulse, or direct UART serial access to on-chip registers. Instantaneous current, voltage, and power measurements are also available over the serial port. The two-wire UART minimizes the cost of isolation where required.

A configurable digital output provides energy pulses, zero-crossing, energy direction, or interrupt functions. Interrupts can be generated for a variety of conditions including voltage sag or swell, overcurrent, and more. On-chip register integrity is assured via checksum and write protection. The CS5490 is designed to interface to a variety of voltage and current sensors, including shunt resistors, current transformers, and Rogowski coils.

On-chip functionality makes digital calibration simple and ultra fast to minimize the time required at the end of the customer production line. Performance across temperature is ensured with an on-chip voltage reference with low drift. A single 3.3V power supply is required, and power consumption is low at <13mW. To minimize space requirements, the CS5490 is offered in a low-cost 16-pin SOIC package.

ORDERING INFORMATION

See Page 57.

order Delta-Sigma an-

Cirrus Logic, Inc.

http://www.cirrus.com

MAR’13

DS982F3

CS5490

TABLE OF CONTENTS

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.1 Analog Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.1.1 Voltage Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.1.2 Current Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.1.3 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2.1 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2.2 Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2.3 UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2.3.1 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2.4 MODE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4. Signal Flow Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.1 Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.2 Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3 IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.4 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.5 DC Offset & Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.6 High-pass & Phase Matching Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7 Digital Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.8 Low-rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.8.1 Fixed Number of Samples Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.8.2 Line-cycle Synchronized Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.8.3 RMS Current & Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.8.4 Active Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.8.5 Reactive Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.8.6 Apparent Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.8.7 Peak Voltage & Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.8.8 Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.9 Average Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.10 Average Reactive Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.1 Power-on Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.3 Zero-crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.4 Line Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.5 Energy Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.5.1 Pulse Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5.5.2 Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6 Voltage Sag, Voltage Swell, and Overcurrent Detection . . . . . . . . . . . . . . . . . . . . .21

5.7 Phase Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.8 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2 DS982F3

CS5490

5.9 Anti-creep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.10 Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.10.1 Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.10.2 Register Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6. Host Commands and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1 Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1.1 Memory Access Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1.1.1 Page Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1.1.2 Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1.1.3 Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1.2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1.3 Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.1.4 Serial Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.2 Hardware Registers Summary (Page 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3 Software Registers Summary (Page 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4 Software Registers Summary (Page 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.5 Software Registers Summary (Page 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.6 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.1 Calibration in General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.1.1 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.1.1.1 DC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.1.1.2 AC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.1.2 Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.1.3 Calibration Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.3 Temperature Sensor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

7.3.1 Temperature Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

11. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . . . . 57

12. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

DS982F3 3

CS5490

LIST OF FIGURES

Figure 1. Oscillator Connections................................................................................................... 7

Figure 2. UART Serial Frame Format........................................................................................... 7

Figure 3. Active Energy Load Performance.................................................................................. 8

Figure 4. Reactive Energy Load Performance.............................................................................. 9

Figure 5. IRMS Load Performance ............................................................................................... 9

Figure 6. Signal Flow for V, I, P, and Q Measurements ............................................................. 15

Figure 7. Low-rate Calculations .................................................................................................. 16

Figure 8. Power-on Reset Timing ............................................................................................... 18

Figure 9. Zero-crossing Level and Zero-crossing Output on DO................................................ 19

Figure 10. Energy Pulse Generation and Digital Output Control ................................................ 20

Figure 11. Sag, Swell, & Overcurrent Detect.............................................................................. 21

Figure 12. Phase Sequence A, B, C for Rising Edge Transition ................................................ 22

Figure 13. Phase Sequence C, B, A for Rising Edge Transition ................................................ 23

Figure 14. Byte Sequence for Page Select................................................................................. 24

Figure 15. Byte Sequence for Register Read ............................................................................ 24

Figure 16. Byte Sequence for Register Write ............................................................................. 24

Figure 17. Byte Sequence for Instructions.................................................................................. 24

Figure 18. Byte Sequence for Checksum ................................................................................... 25

Figure 19. Calibration Data Flow ................................................................................................52

Figure 20. T Register vs. Force Temp ........................................................................................ 54

Figure 21. Typical Connection Diagram (Single-phase, Two-wire, Power Meter)...................... 55

LIST OF TABLES

Table 1. POR Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 2. Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 3. Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 DS982F3

CS5490

1. OVERVIEW

The CS5490 is a CMOS power measurement integrated circuit that uses two  analog-to-digital converters to measure line voltage and current. The CS5490 calculates active, reactive, and apparent power as well as RMS voltage and current and peak voltage and current. It handles other system-related functions, such as energy pulse generation, voltage sag and swell, overcurrent and zero-crossing detection, and line frequency measurement. A separate analog-to-digital converter is used for on-chip temperature measurement.

The CS5490 is optimized to interface to current transformers, shunt resistors, or Rogowski coils for current measurement, and to resistive dividers or voltage transformers for voltage measurement. Two full-scale ranges are provided on the current input to accommodate different types of current sensors. The CS5490’s two differential inputs have a common-mode input range from analog ground (GNDA) to the positive analog supply (VDDA).

An on-chip voltage reference (typically 2.4 volts) is generated and provided at analog output, VREF±.

The digital output (DO) provides a variety of output signals and, depending on the mode selected, provides energy pulses, zero-crossings, or other choices.

The CS5490 includes a UART serial host interface to an external microcontroller. The UART signals include serial data input (RX) and serial data output (TX).

DS982F3 5

2. PIN DESCRIPTION

XOUT

VREF-

VIN-

VIN+

IIN+

IIN-

RESET

XIN

VDDD

VREF+

GNDA

VDDA

MODE

Clock Generator

Crystal In Crystal Out

Control Pins and Serial Data I/O

Digital Output 12

Reset 3

Serial Interface 13,14

Operating Mode Select 15

Analog Inputs/Outputs

Voltage Input 6,7

Current Input 5,4

Voltage Reference Input 9,8

Power Supply Connections

Internal Digital Supply 16

Positive Analog Supply 11

Analog Ground 10

2,1

CS5490

XIN, XOUT — Connect to an external quartz crystal. Alternatively, an external clock can be

supplied to the XIN pin to provide the system clock for the device.

DO — Configurable digital output for energy pulses, interrupt, energy direction, and zero-crossings.

RESET — An active-low Schmitt-trigger input used to reset the chip.

TX, RX — UART serial data output/input.

MODE — Connect to VDDA for proper operation.

VIN+, VIN- — Differential analog input for the voltage channel.

IIN+, IIN- — Differential analog input for the current channel.

VREF+, VREF- — The voltage reference output and return.

VDDD — Decoupling pin for the internal digital supply.

VDDA — The positive analog supply.

GNDA — Analog ground.

2.1 Analog Pins

The CS5490 has two differential inputs, one for voltage (VIN) and one for currentIIN). The CS5490 also has two voltage reference pins (VREF) between which a

0.1µ bypass capacitor must be placed.

2.1.1 Voltage Input

The output of the line voltage resistive divider or transformer is connected to the VIN input of the CS5490. The voltage channel is equipped with a 10x, fixed-gain amplifier. The full-scale signal level that can be applied to the voltage channel is ±250 mV. If the input signal is a sine wave, the maximum RMS voltage is 250 mVp / approximately 70.7% of maximum peak voltage.

6 DS982F3

2  176.78mV

, which is

RMS

2.1.2 Current Input

The output of the current-sensing shunt resistor or transformer is connected to the IIN input pins of the CS5490. To accommodate different current-sensing elements, the current channel incorporates a programmable gain amplifier (PGA) with two selectable input gains, as described in the Config0 register description 6.6.1 Configuration 0 (Config0) – Page 0,

Address 0 on page 32. There is a 10x gain setting and

a 50x gain setting. The full-scale signal level for the current channel is ±50mV and ±250 mV for 50x and 10x gain settings, respectively. If the input signal is a sine wave, the maximum RMS voltage is 35.35 mV

176.78mV maximum peak voltage.

, which is approximately 70.7% of

RMS

CS5490

XIN XOUT

C1 = 22pF C2 = 22pF

Figure 1. Oscillator Connections

0 1 2 7IDLE STOP3 4 5 6START

DATA

IDLE

2.1.3 Voltage Reference

The CS5490 generates a stable voltage reference of

2.4V between the VREF pins. The reference system

also requires a filter capacitor of at least 0.1µF between the VREF pins.

The reference system is capable of providing a reference for the CS5490 but has limited ability to drive external circuitry. It is strongly recommended that nothing other than the required filter capacitor is connected to the VREF pins.

2.1.4 Crystal Oscillator

An external, 4.096 MHz quartz crystal can be connected to the XIN and XOUT pins as shown in Figure 1. To reduce system cost, each pin is supplied with an on-chip load capacitor.

Alternatively, an external clock source can be connected to the XIN pin.

2.2 Digital Pins

2.2.1 Reset Input

The active-low RESET pin, when asserted for longer than 120µs, will halt all CS5490 operations and reset internal hardware registers and states. When de-asserted, an initialization sequence begins, setting the default register values. To prevent erroneous, noise-induced resets to the part, an external pull-up resistor and a decoupling capacitor are necessary on the RESET

pin.

2.2.2 Digital Output

The CS5490 provides a configurable digital output (DO). It can be configured to output energy pulses, interrupt, zero-crossings, or energy directions. Refer to the description of the Config1 register in section 6.6

2.2.3 UART Serial Interface

The CS5490 provides two pins, RX and TX, for communication between a host microcontroller and the CS5490.

2.2.3.1 UART

The CS5490 provides a two-wire, asynchronous, full-duplex UART port. The CS5490 UART operates in 8-bit mode, which transmits a total of 10 bits per byte. Data is transmitted and received LSB first, with one start bit, eight data bits, and one stop bit.

Figure 2. UART Serial Frame Format

The baud rate is defined in the SerialCtrl register. After chip reset, the default baud rate is 600, if MCLK is

4.096MHz. The baud rate is based on the contents of bits BR[15:0] in the SerialCtrl register and is calculated as follows:

BR[15:0] = Baud Rate x (524288/MCLK)

Baud Rate = BR[15:0] /(524288/MCLK)

The maximum baud rate is 512K if MCLK is 4.096 MHz.

The UART has two signals: TX and RX. TX is the serial data output from the CS5490; RX is the serial data input to the CS5490.

2.2.4 MODE Pin

The MODE pin must be tied to VDDA for normal operation. The MODE pin is used primarily for factory test procedures.

DS982F3 7

CS5490

-1

-0.5

0.5

0 500 1000 1500 2000 2500 3000 3500 4000 4500

Percent Error (%)

Current Dynamic Range (x : 1

)

Lagging PF = 0.5

Leading PF = 0.5

PF = 1

Figure 3. Active Energy Load Performance

3. CHARACTERISTICS & SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Positive Analog Power Supply VDDA 3.0 3.3 3.6 V Specified Temperature Range T

POWER MEASUREMENT CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Active Energy

(Note 1 & 2) Current Channel Input Signal Dynamic Range 4000:1

Reactive Energy

(Note 1 & 2) Current Channel Input Signal Dynamic Range 4000:1

Apparent Power

(Note 1 & 3) Current Channel Input Signal Dynamic Range 1000:1

Current RMS

(Note 1, 3, & 4) Current Channel Input Signal Dynamic Range 1000:1

Voltage RMS

(Note 1 & 3) Voltage Channel Input Signal Dynamic Range 20:1

Power Factor All Gain Ranges

(Note 1 & 3) Current Channel Input Signal Dynamic Range 1000:1

All Gain Ranges

Avg

S-±0.1-%

RMS

PF - ±0.1 - %

-40 - +85 °C

-±0.1- %

Notes: 1. Specifications guaranteed by design and characterization.

2. Active energy is tested with power factor PF = 1.0. Reactive energy is tested with Sin( level using single energy pulse. Where: 1) One energy pulse = 0.5Wh or 0.5Varh; 2) VDDA = +3.3 V,

3) System is calibrated.

3. Calculated using register values; N

4. I

error calculated using register values. 1) VDDA = +3.3V; TA = 25°C; MCLK = 4.096MHz; 2) AC offset calibration applied.

RMS

≥4000.

) = 1.0. Energy error measured at system

= 25°C, MCLK = 4.096MHz;

TYPICAL LOAD PERFORMANCE

• Energy error measured at system level using single energy pulse; where 1 energy pulse = 0.5Wh or 0.5Varh.

•I

error calculated using register values

RMS

• VDDA = +3.3V; T

= 25°C; MCLK = 4.096MHz

8 DS982F3

CS5490

-1

-0.5

0.5

0 500 1000 1500 2000 2500 3000 3500 4000 4500

Percent Error (%)

Current Dynamic Range (x : 1

)

Lagging sin() = 0.5

Leading sin() = 0.5

sin() = 1

Figure 4. Reactive Energy Load Performance

-1

-0.5

0.5

0 500 1000 1500

Percent Error (%)

Current Dynamic range (x : 1)

IRMS Error

Error

Figure 5. I

RMS

Load Performance

DS982F3 9

RMS

CS5490

ANALOG CHARACTERISTICS

• Min/Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and T

• VDDA = +3.3V ±10%; GNDA = 0V. All voltages with respect to 0V.

• MCLK = 4.096MHz.

Parameter Symbol Min Typ Max Unit

Analog Inputs (Current Channels)

Common Mode Rejection

(DC, 50, 60Hz) CMRR 80 - - dB

Common Mode+Signal -0.25 - VDDA V

Differential Full-scale Input Range

[(IIN+) – (IIN-)] (Gain = 50)

(Gain = 10)

IIN

Total Harmonic Distortion (Gain = 50) THD 90 100 - dB

Signal-to-Noise Ratio (SNR)

Crosstalk from Voltage Inputs at Full Scale

Crosstalk from Current Input at Full Scale

(Gain = 10)

(Gain = 50)

(50, 60Hz) --115-dB

SNR

Input Capacitance IC - 27 - pF Effective Input Impedance EII 30 - - k

Offset Drift (Without the High-pass Filter) OD - 4.0 - µV/ °C

Noise (Referred to Input)

(Gain = 10) (Gain = 50)

Power Supply Rejection Ratio (60Hz)

(Note 7) (Gain = 10)

(Gain = 50)

PSRR 60

Analog Inputs (Voltage Channels)

Common Mode Rejection

(DC, 50, 60Hz) CMRR 80 - - dB

Common Mode+Signal -0.25 - VDDA V

Differential Full-scale Input Range

[(VIN+) – (VIN-)] VIN - 250 - mV

Total Harmonic Distortion THD 80 88 - dB

Signal-to-Noise Ratio (SNR) SNR - 73 - dB

Crosstalk from Current Inputs at Full Scale

(50, 60Hz) --115-dB

Input Capacitance IC - 2.0 - pF Effective Input Impedance EII 2 - - M

Noise (Referred to Input) N

Offset Drift (Without the High-pass Filter) OD - 16.0 - µV/°C

Power Supply Rejection Ratio

(Note 7) (Gain = 10)

(60Hz)

PSRR 60 65 - dB

Temperature

Temperature Accuracy

(Note 6) T-±5-°C

= 25°C.

-40-µV

250

80 80

2.2

65 75

µV µV

mV mV

dB dB

RMS

dB dB

RMS

10 DS982F3

Parameter Symbol Min Typ Max Unit

PSRR 20

150

---------- -

log=

VREF

MAX

VREF

MIN

–

VREF

AVG

------------------------------------------------------------





MAX TAMIN–

----------------------------------------------





1.0 10

=

Power Supplies

Power Supply Currents (Active State)

(VDDA = +3.3V) PSCA - 3.9 - mA

A+

Power Consumption

(Note 5) Active State (VDDA = +3.3V)

Stand-by State

Notes: 5. All outputs unloaded. All inputs CMOS level.

6. Temperature accuracy measured after calibration is performed.

7. Measurement method for PSRR: VDDA = +3.3V, a 150mV (zero-to-peak) (60Hz) sinewave is imposed onto the +3.3V DC supply voltage at the VDDA pin. The “+” and “-” input pins of both input channels are shorted to GNDA. The CS5490 is then commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as V

PSRR is (in dB):

VOLTAGE REFERENCE

Parameter Symbol Min Typ Max Unit

PC -

CS5490

12.9

4.5

mW mW

Reference

(Note 8)

Output Voltage VREF +2.3 +2.4 +2.5 V

Temperature Coefficient

Load Regulation

Notes: 8. It is strongly recommended that no connection other than the required filter capacitor be made to VREF±.

9. The voltage at VREF± is measured across the temperature range. From these measurements the following formula is used to calculate the VREF temperature coefficient:

10. Specified at maximum recommended output of 1µA sourcing. VREF is a very sensitive signal, the output of the VREF circuit has a very high output impedance so that the 0.1µF reference capacitor provides attenuation even to low frequency noise, such as 50Hz noise on the VREF output. As such VREF intended for the CS5490 only and should not be connected to any external circuitry. The output impedance is sufficiently high that standard digital multi-meters can significantly load this voltage. The accuracy of the metrology IC can not be guaranteed when a multimeter or any component other than the 0.1µF capacitor is attached to VREF. If it is desired to measure VREF for any reason other than a very course indicator of VREF functionality, Cirrus recommends a very high input impedance multimeter such as the Keithley Model 2000 Digital Multimeter be used, but still cannot guarantee the accuracy of the metrology with this meter connected to VREF.

(Note 9) TC

(Note 10) V

VREF

-25-ppm/°C

-30-mV

DS982F3 11

CS5490

DIGITAL CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and T

• VDDA = +3.3V ±10%; GNDA = 0V. All voltages with respect to 0V.

• MCLK = 4.096MHz.

Parameter Symbol Min Typ Max Unit

Master Clock Characteristics

XIN Clock Frequency

Internal Gate Oscillator MCLK 2.5 4.096 5 MHz

XIN Clock Duty Cycle 40 - 60 %

Filter Characteristics

Phase Compensation Range

(60Hz, OWR = 4000Hz) -10.79 - +10.79 °

Input Sampling Rate - MCLK/8 - Hz Digital Filter Output Word Rate High-pass Filter Corner Frequency

(Both channels) OWR - MCLK/1024 - Hz

-3dB -2.0-Hz

Input/Output Characteristics

High-level Input Voltage (All Pins) V

Low-level Input Voltage (All Pins) V

High-level Output Voltage

(Note 12) I

DO, I

Low-level Output Voltage

(Note 12) All Other Outputs, I

DO, I

=+10mA

out

=+5mA

out

=-12mA

out

=-5mA

Input Leakage Current I

3-state Leakage Current I

Digital Output Pin Capacitance C

0.6(VDDA) - - V

--0.6V

VDDA-0.3 VDDA-0.3

-±1±10µA

--±10µA

out

-5-pF

= 25°C.

0.5

V V

Notes: 11. All measurements performed under static conditions.

12. XOUT pin used for crystal only. Typical drive current<1 mA.

12 DS982F3

SWITCHING CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and T

• VDDA = +3.3V ± 10%; GNDA = 0V. All voltages with respect to 0 V.

• Logic Levels: Logic 0 = 0V, Logic 1 = VDDA.

Parameter Symbol Min Typ Max Unit

Rise Times

(Note 13) Any Digital Output Except DO

Fall Times

(Note 13) Any Digital Output Except DO

rise

fall

Start-up

Oscillator Start-up Time

Notes: 13. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

14. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.

XTAL = 4.096 MHz (Note 14)

ost

= 25°C.

-60-ms

CS5490

1.0

µs ns

DS982F3 13

CS5490

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Typ Max Unit

DC Power Supplies

Input Current

(Notes 16 and 17)

Input Current for Power Supplies - - - ±50 -

Output Current

Power Dissipation

Input Voltage

Junction-to-Ambient Thermal Impedance

Ambient Operating Temperature

Storage Temperature

Notes: 15. VDDA and GNDA must satisfy [(VDDA) – (GNDA)]  + 4.0 V.

16. Applies to all pins, including continuous overvoltage conditions at the analog input pins.

17. Transient current of up to 100mA will not cause SCR latch-up.

18. Applies to all pins, except VREF±

19. Total power dissipation, including all input currents and output currents.

20. Applies to all pins.

(Note 15) VDDA -0.3 - +4.0 V

(Note 18)

(Note 19)

(Note 20)

2 Layer Board 4 Layer Board

OUT



stg

-- ±10mA

-- 100mA

-- 500mW

- 0.3 - (VDDA) + 0.3 V

140

-40 - 85 °C

-65 - 150 °C

°C/W °C/W

WARNING:

Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

14 DS982F3

MUX

VIN±

SINC

IIN±

SINC

PGA

HPF

4th Order

ΔΣ

Modulator

4th Order

ΔΣ

Modulator

x10

DELAY

CTRL

2

MUX

PMF

HPF

PMF

IIR

Phase

Shift

Config 2

Epsilon

DELAY

CTRL

INT

Registers

SYS

GAIN

... ...

IFLT[1:0]VFLT[1:0]

DCOFF

GAIN

... ...

FPCC[8:0]CPCC[1:0]

...

Figure 6. Signal Flow for V, I, P, and Q Measurements

4. SIGNAL FLOW DESCRIPTION

The signal flow for voltage, current measurement, and the other calculations is shown in Figure 6.

The signal flow consists of a current and a voltage channel. The current and voltage channels have differential input pins.

4.1 Analog-to-Digital Converters

Both input channels use fourth-order delta-sigma modulators to convert the analog inputs to single-bit digital data streams. The converters sample at a rate of MCLK/8. This high sampling provides a wide dynamic range and simplifies anti-alias filter design.

4.2 Decimation Filters

The single-bit modulator output data is widened to 24 bits and down sampled to MCLK/1024 with low-pass decimation filters. These decimation filters are third-order Sinc filters. The filter outputs pass through an IIR "anti-sinc" filter.

4.3 IIR Filter

The IIR filter is used to compensate for the amplitude roll-off of the decimation filters. The droop-correction filter flattens the magnitude response of the channel out to the Nyquist frequency, thus allowing for accurate measurements of up to 2kHz (MCLK = 4.096MHz). By default, the IIR filters are enabled. The IIR filters can be bypassed by setting the IIR_OFF bit in the Config2 register.

4.4 Phase Compensation

Phase compensation changes the phase of voltage relative to current by adding a delay in the decimation filters. The amount of phase shift is set by the PC register bits CPCC[1:0] and FPCC[8:0] for the current channel. For the voltage channel, only bits CPCC[1:0] affect the delay.

Fine phase compensation control bits, FPCC[8:0], provide up to 1/OWR delay in the current channel. Coarse phase compensation control bits, CPCC[1:0], provide an additional 1/ OWR delay in the current channel or up to 2/ OWR delay in the voltage channel. Negative delay in the voltage channel can be implemented by setting longer delay in the current channel than the voltage channel. For a OWR of 4000Hz, the delay range is ±500 µs, a phase shift of ±8.99° at 50Hz and ± 10.79° at 60Hz. The step size is

0.008789° at 50Hz and 0.010547° at 60 Hz. For more information about phase compensation, see section 7.2

Phase Compensation on page 53.

4.5 DC Offset & Gain Correction

The system and CS5490 inherently have component tolerances, gain, and offset errors, which can be removed using the gain and offset registers. Each measurement channel has its own set of gain and offset registers. For every instantaneous voltage and current sample, the offset and gain values are used to correct DC offset and gain errors in the channel (see section 7.

System Calibration on page 52 for more details).

CS5490

DS982F3 15

CS5490



Regi sters

MUX

...

APCM

Config 2

ACOFF



RMS

AVG

OFF



OFF



Inverse

Figure 7. Low-rate Calculations

4.6 High-pass & Phase Matching Filters

Optional high-pass filters (HPF in Figure 6) remove any DC component from the selected signal paths. Each power calculation contains a current and voltage channel. If an HPF is enabled in only one channel, a phase-matching filter (PMF) should be applied to the other channel to match the phase response of the HPF. For AC power measurement, high-pass filters should be enabled on the voltage and current channels. For information about how to enable and disable the HPF or PMF on each channel, refer to Config2 register descriptions in section 6.6 Register Descriptions on page 32.

4.7 Digital Integrators

Optional digital integrators (INT in Figure 6) are implemented on the current channel to compensate for the 90° phase shift and 20dB/decade gain generated by the Rogowski coil current sensor. When a Rogowski coil is used as the current sensor, the integrator (INT) should be enabled on that current channel. For information about how to enable and disable the INT on the current channel, refer to Config2 register descriptions in section 6.6 Register Descriptions on page 32.

4.8 Low-rate Calculations

All the RMS and power results come from low-rate calculations by averaging the output word rate (OWR) instantaneous values over N samples, where N is the value stored in the SampleCount register. The low-rate interval or averaging period is N divided by OWR (4000Hz if MCLK = 4.096MHz). The CS5490 provides

two averaging modes for low-rate calculations: Fixed Number of Sample Averaging mode and Line-cycle Synchronized Averaging mode. By default, the CS5490 averages with the Fixed Number of Samples Averaging mode. By setting the AVG_MODE bit in the Config2 register, the CS5490 will use the Line-cycle Synchronized Averaging mode.

4.8.1 Fixed Number of Samples Averaging

N is the preset value in the SampleCount register and should not be set less than 100. By default, the SampleCount register is 4000. With MCLK = 4.096 MHz, the averaging period is fixed at N/ 4000 = 1 second, regardless of the line frequency.

4.8.2 Line-cycle Synchronized Averaging

When operating in Line-cycle Synchronized Averaging mode, and when line frequency measurement is enabled (see section 5.4 Line Frequency Measurement on page 19), the CS5490 uses the voltage (V) channel zero crossings and measured line frequency to automatically adjust N such that the averaging period will be equal to the number of half line-cycles in the CycleCount register. For example, if the line frequency is 51Hz, and the CycleCount register is set to 100, N will be 4000 conversion. N is self-adjusted according to the line frequency, therefore the averaging period is always close to the whole number of half line-cycles, and the low-rate calculation results will minimize ripple and maximize resolution, especially when the line frequency varies. Before starting a low-rate conversion in the Line-cycle Synchronized Averaging mode, the

(100/2)/ 51 = 3921 during continuous

16 DS982F3

CS5490

RMS

n0=

N1–



------------------- -

= V

RMS

n0=

N1–



----------------------

[Eq. 1]

RMSIRMS

=

[Eq. 2]

AVG

[Eq. 3]

ACTIVE

----------------------

[Eq. 4]

SampleCount register should not be changed from its default value of 4000, and bit AFC of the Config2 register must be set. During continuous conversion, the host processor should not change the SampleCount register.

The APCM bit in the Config2 register controls which method is used for apparent power calculation.

4.8.7 Peak Voltage & Current

Peak current (I

) and peak voltage (V

PEAK

) are cal-

culated over N samples and recorded in the corre-

4.8.3 RMS Current & Voltage

The root mean square (RMS in Figure 7) calculations are performed on N instantaneous voltage and current samples using Equation 1:

sponding channel peak register documented in the register map. This peak value is updated every N samples.

4.8.8 Power Factor

Power factor (PF) is active power divided by apparent power, as shown below. The sign of the power factor is determined by the active power. See Equation 4.

4.9 Average Active Power Offset

The average active power offset register, P used to offset erroneous power sources resident in the system not originating from the power line. Residual

4.8.4 Active Power

The instantaneous voltage and current samples are multiplied to obtain the instantaneous power (P) (see

Figure 6). The product is then averaged over N samples

to compute active power (P

AVG

4.8.5 Reactive Power

Instantaneous reactive power (Q) is the sample rate result obtained by multiplying instantaneous current (I) by instantaneous quadrature voltage (Q). These values are created by phase shifting instantaneous voltage (V) 90° using first-order integrators (see Figure 6). The gain

power offsets are usually caused by crosstalk into the current channel from the voltage channel, or from ripple on the meter’s or chip’s power supply, or from inductance from a nearby transformer.

These offsets can be either positive or negative, indicating crosstalk coupling either in phase or out of phase with the applied voltage input. The power offset register can compensate for either condition.

To use this feature, measure the average power at no load and take the measured result (from the P register), invert (negate) the value, and write it to the associated power offset register, P

OFF

. of these integrators is inversely related to line frequency, so their gain is corrected by the Epsilon register, which is based on line frequency. Reactive power (Q

) is generated by integrating the

AVG

instantaneous quadrature power over N samples.

4.8.6 Apparent Power

By default, the CS5490 calculates the apparent power (S) as the product of RMS voltage and current. See Equation 2:

4.10 Average Reactive Power Offset

The average reactive power offset register, Q be used to offset erroneous power sources resident in the system not originating from the power line. Residual reactive power offsets are usually caused by crosstalk into the current channel from the voltage channel, or from ripple on the meter’s or chip’s power supply, or from inductance from a nearby transformer.

These offsets can be either positive or negative, depending on the phase angle between the crosstalk

The CS5490 also provides an alternate apparent power calculation method. The alternate apparent power method uses real power (P (Q

) to calculate apparent power. See Equation 3.

AVG

DS982F3 17

) and reactive power

AVG

coupling and the applied voltage. The reactive power offset register can compensate for either condition. To use this feature, measure the average reactive power at no load. Take the measured result from the Q register, invert (negate) the value and write it to the reactive power offset register, Q

OFF

, can be

OFF

AVG

, can

AVG

5. FUNCTIONAL DESCRIPTION

VDDA

POR_Rough_VDDA

POR_F ine_VD DA

VDDD

POR_Rough_VDDD

POR_Fine_VDDD

POR_F ine_VD DA POR_Fine_VDDD

Master Reset

130ms

th1

th2

th5

th6

th3

th4

th7

th8

CS5490

5.1 Power-on Reset (POR)

The CS5490 has an internal power supply supervisor circuit that monitors the VDDA and VDDD power supplies and provides the master reset to the chip. If any of these voltages are in the reset range, the master reset is triggered.

Both the analog and the digital supply have their own POR circuit. During power-up, both supplies have to be above the rising threshold for the master reset to be de-asserted.

Each POR is divided into 2 blocks: rough and fine. Rough POR triggers the fine POR. Rough POR depends only on the supply voltage. The trip point for the fine POR is dependent on bandgap voltage for precise control.

The POR circuit also acts as a brownout detect. The fine POR detects supply drops and asserts the master reset.

The rough and fine PORs have hysteresis in their rise and fall thresholds which prevents the reset signal from chattering.

The following plot shows the POR outputs for each of the power supplies. The POR_Fine_VDDA and POR_Fine_VDDD signals are AND-ed to form the actual power-on reset signal to the digital circuity. The digital circuitry, in turn, holds the master reset signal for 130ms and then de-asserts the master reset.

Table 1. POR Thresholds

Typical POR

Threshold

Rough

VDDA

Fine

Rough

VDDD

Fine

Rising Falling

=2.34V V

th1

=2.77V V

th2

=1.20V V

th3

=1.51V V

th4

th6

th5

th8

th7

=2.06V

=2.59V

=1.06V

=1.42V

5.2 Power Saving Modes

Power Saving modes for CS5490 are accessed through the Host Instruction Commands (see 6.1 Host

Commands on page 24).

• Standby: Powers down all the ADCs, rough buffer, and the temperature sensor. Standby mode disables the system time calculations. Use the wake-up command to come out of standby mode.

• Wake-up: Clears the ADC power-down bits and starts the system time calculations.

After any of these commands are completed, the DRDY bit is set in the Status0 register.

5.3 Zero-crossing Detection

Zero-crossing detection logic is implemented in CS5490. A low-pass filter can be enabled by setting ZX_LPF bit in register Config2. The low-pass filter has a cut-off frequency of 80Hz. It is used to eliminate any harmonics and to help the zero-crossing detection on the 50Hz or 60 Hz fundamental component. The zero-crossing level registers are used to set the minimum threshold over which the channel peak has to exceed in order for the zero-crossing detection logic to function. There are two separate zero-crossing level registers: VZX channels, and IZX channels.

is the threshold for the voltage

LEVEL

is the threshold for the current

LEVEL

Figure 8. Power-on Reset Timing

18 DS982F3

CS5490

LEVEL

IZX

LEVEL

If |V

PEAK

| > VZX

LEVEL

, then voltage zero-crossing detection is enabled.

If |I

PEAK

| > IZX

LEVEL

, then current zero-crossing detection is enabled.

Zero-crossing output on DOx pin

Pulse width = 250μs

V(t), I(t)

If |V

PEAK

|  VZX

LEVEL

, then voltage zero-crossing detection is disable

If |I

PEAK

|  IZX

LEVEL

, then current zero-crossing detection is disabled.

Figure 9. Zero-crossing Level and Zero-crossing Output on DO

5.4 Line Frequency Measurement

If the Automatic Frequency Calculation (AFC) bit in the Config2 register is set, the line frequency measurement on the voltage channel will be enabled. The line frequency measurement is based on a number of voltage channel zero crossings. This number is 100 by default and configurable through the ZX (see section 6.6.56 on page 51). The Epsilon register will be updated automatically with the line frequency information. The Frequency Update (FUP) bit in the Status0 interrupt status register is set when the frequency calculation is completed. When the line frequency is 50Hz and the ZX Epsilon register is updated every one second with a resolution of less than 0.1%. A larger zero-crossing number in the ZX frequency measurement resolution and period. Note that the CS5490 line frequency measurement function does not support the line frequency out of the range of 40Hz to 75Hz.

NUM

The Epsilon register is also used to set the gain of the 90° phase shift filter used in the quadrature power calculation. The value in the Epsilon register is the ratio of the line frequency to the output word rate (OWR). For 50Hz line frequency and 4000Hz OWR, Epsilon is 50/4000 (0.0125) (the default). For 60Hz line frequency, it is 60/ 4000 (0.015).

5.5 Energy Pulse Generation

The CS5490 provides an independent energy pulse generation (EPG) block in order to output active, reactive, and apparent energy pulses on the digital output pin (DO). The energy pulse frequency is proportional to the magnitude of the power. The energy pulse output is commonly used as the test output of a power meter. The host microcontroller can also use the energy pulses to easily accumulate the energy. Refer to

Figure 10.

DS982F3 19

CS5490

SUM

Sig n

SUM

Sig n

P Sign

Q Sign

Reserved

V Crossing

I Crossing

DO_OD

(Config1)

(PulseCtrl) EPGIN[3:0]

DOMODE[3:0]

(Config1)

Hi-Z

Interrupt

SUM

AVG

PULSE RATE

EPG_ON (Config1)

MCLK

(PulseWidth) PW[7:0]

(PulseWidth) FREQ_RNG[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

Energy Pulse Generation (EPG)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Digital Output Mux (DO)

Reserved

Figure 10. Energy Pulse Generation and Digital Output Control

After reset, the energy pulse generation block is disabled (DOMODE[3:0] = Hi-Z). To output a desired energy pulse to a DO pin, it is necessary to follow the steps below:

1. Write to register PulseWidth (page 0, address 8) to select the energy pulse width and pulse frequency range.

2. Write to register PulseRate (page 18, address 28) to select the energy pulse rate.

3. Write to register PulseCtrl (page 0, address 9) to select the input to the energy pulse generation block.

4. Write ‘1’ to bit EPG_ON of register Config1 (page 0, address 1) to enable the energy pulse generation block.

5. Wait at least 0.1s.

6. Write bits DOMODE[3:0] of register Config1 to select DO to output pulses from the energy pulse generation block.

7. Send DSP instruction (0xD5) to begin continuous conversion.

20 DS982F3

5.5.1 Pulse Rate

Before configuring the PulseRate register, the full-scale pulse rate needs to be calculated, and the frequency range needs to be specified through FREQ_RNG[3:0] bits in the PulseWidth register. For example, if a meter has the meter constant of 1000imp/kWh, a maximum voltage (U of 100A, the maximum pulse rate is:

Assume the meter is calibrated with U and the Scale register contains the default value of 0.6. After gain calibration, the power register value will be

0.36, which represents 240 x 100 = 24kW or 6.6667Hz pulse output rate. The full-scale pulse rate is:

Refer to section 6.6.6 Pulse Output Width (PulseWidth)

– Page 0, Address 8 on page 36. The FREQ_RNG[3:0]

) of 240V, and a maximum current (I

MAX

[1000x(240 x 100/1000)]/3600 = 6.6667Hz.

out

bits should be set to b[0110].

MAX

= 6.6667/0.36 = 18.5185Hz.

and I

MAX

)

CS5490

Level

Duration

Figure 11. Sag, Swell, & Overcurrent Detect

The CS5490 pulse generation block behaves as follows:

• The pulse rate generated by full-scale (1.0 decimal) power register is

=(PulseRate x 2000)/ 2

OUT

FREQ_RNG

•The PulseRate register value is

PulseRate = (F

OUT

FREQ_RNG

)/2000

= (18.5186 x 64) / 2000

= 0.5925952

= 0x4BDA29

5.5.2 Pulse Width

The PulseWidth register defines the Active-low time of each energy pulse:

Active-low = 250µs + (PulseWidth/64000).

By default, the PulseWidth register value is 1, and the Active-low time of each energy pulse is 265.6µs. Note that the pulse width should never exceed the pulse period.

5.6 Voltage Sag, Voltage Swell, and

Overcurrent Detection

Voltage sag detection is used to determine when the voltage falls below a predetermined level for a specified interval of time (duration). Voltage swell and overcurrent detection determine when the voltage or current rises above a predetermined level for the duration.

The duration is set by the value in the VSag

VSwell

, and IOver

DUR

registers. Setting any of

DUR

these to zero (default) disables the detect feature for the given channel. The value is in output word rate (OWR) samples. The predetermined level is set by the values in the VSag

LEVEL

, VSwell

, and IOver

LEVEL

registers.

For each enabled input channel, the measured value is rectified and compared to the associated level register. Over the duration window, the number of samples above and below the level are counted. If the number of samples below the level exceeds the number of samples above, a Status0 register bit VSAG is set, indicating a sag condition. If the number of samples above the level exceeds the number of samples below, a Status0 register bit VSWELL or IOVER is set, indicating a swell or overcurrent condition (see Figure 11).

LEVEL

DS982F3 21

CS5490

Figure 12. Phase Sequence A, B, C for Rising Edge Transition

-2

Phase A Channel

-2

Phase B Channel

-2

Phase C Channel

Write 0x16 to

PSDC Register

Start on the Falling Edge on the RX Pin

Stop

Phase C Count

Phase B Count

Phase A Count

5.7 Phase Sequence Detection

Polyphase meters using multiple CS5490 devices may be configured to sense the succession of voltage zero-crossings and determine which phase order is in service. The phase sequence detection within CS5490 involves counting the number of OWR samples from a starting point to the next voltage zero-crossing rising edge or falling for each phase. By comparing the count for each phase, the phase sequence can be easily determined: the smallest count is first, and the largest count is last.

The phase sequence detection and control (PSDC) register provides the count control, zero-crossing direction and count results. Writing '0' to bit DONE and '10110' to bits CODE[4:0] of the PSDC register followed by a falling edge on the RX pin will initiate the phase sequence detection circuit. The RX pin must be held low for a minimum of 500ns. When the device is in UART mode, it is recommended that a 0xFF command be written to all parts to start the phase sequence detection. Multiple CS5490 devices in a polyphase meter must receive the register writing and the RX falling edge at the same time so that all CS5490 devices starts to count simultaneously. Bit DIR of PSDC register specifies the direction of the next zero crossing at which the count stops. If bit DIR is '0', the count stops at the next negative-to-positive zero crossing. If bit DIR is '1', the count stops at the next positive-to-negative zero

crossing. When the count stops, the DONE bit will be set by the CS5490, and then the count result of each phase may be read from bits PSCNT[6:0] of the PSDC register.

If the PSCNT[6:0] bits are equal to 0x00, 0x7F or greater than 0x64 (for 50Hz) or 0x50 (for 60Hz), then a measurement error has occurred, and the measurement results should be disregarded. This could happen when the voltage input signal amplitude is lower than the amplitude specified in the VZX

LEVEL

To determine the phase order, the PSCNT[6:0] bit counts from each CS5490 are sorted in ascending order. Figure 12 and Figure 13 illustrate how phase sequence detection is performed.

Phase sequences A, B, and C for the default rising edge transition are illustrated in Figure 12. The PSCNT[6:0] bits from the CS5490 on phase A will have the lowest count, followed by the PSCNT[6:0] bits from the CS5490 on phase B with the middle count, and the PSCNT[6:0] bits from the CS5490 on phase C with the highest count.

Phase sequences C, B, and A for rising edge transition are illustrated in Figure 13. The PSCNT[6:0] bits from the CS5490 on phase C will have the lowest count, followed by the PSCNT[6:0] bits from the CS5490 on phase B with the middle count, and the PSCNT[6:0] bits from the CS5490 on phase A with the highest count.

22 DS982F3

CS5490

-2

Phase A Channel

-2

Phase B Channel

-2

Phase C Channel

Stop

Phase C Count

Phase B Count

Phase A Count

Write 0x16 to

PSDC Regist er

Start on the Falling Edge on the RX Pin

Figure 13. Phase Sequence C, B, A for Rising Edge Transition

5.8 Temperature Measurement

The CS5490 has an internal temperature sensor, which is designed to measure temperature and optionally compensate for temperature drift of the voltage reference. Temperature measurements are stored in the temperature register (T), which, by default, is configured to a range of ±128°C.

The application program can change the scale and range of the temperature (T) register by changing the temperature gain (T offset (T

) register.

OFF

) register and temperature

GAIN

The temperature (T) register updates every 2240 output word rate (OWR) samples. The Status0 register bit TUP indicates when T is updated.

5.9 Anti-creep

The anti-creep (no-load threshold) is used to determine if a no-load condition is detected. The |P are compared to the value in the no-load threshold (Load than this threshold, then P zero. If S then S

5.10 Register Protection

To prevent the critical configuration and calibration registers from unintended changes, the CS5490 provides two enhanced register protection mechanisms: write protection and automatic checksum calculation.

) register. If both |P

Min

is less than the value in Load

Sum

is forced to zero.

Sum

| and |Q

Sum

and Q

Sum

5.10.1 Write Protection

Setting the DSP_LCK[4:0] bits in the RegLock register to 0x16 enables the CS5490 DSP lockable registers to

DS982F3 23

| and |Q

Sum

| are less

Sum

are forced to

Sum

Min

Sum

be write-protected from the calculation engine. Setting the DSP_LCK[4:0] bits to 0x09 disables the write-protection mode.

Setting the HOST_LCK[4:0] bits in the RegLock register to 0x16 enables the CS5490 HOST lockable registers to be write-protected from the serial interface. Setting the HOST_LCK[4:0] bits to 0x09 disables the write-protection mode.

For registers that are DSP lockable, HOST lockable, or both, refer to sections 6.2 Hardware Registers

Summary (Page 0) on page 26, 6.3 Software Registers Summary (Page 16) on page 28, and 6.4 Software Registers Summary (Page 17) on page 30.

5.10.2 Register Checksum

All the configuration and calibration registers are protected by checksum, if enabled. Refer to sections 6.2

Hardware Registers Summary (Page 0) on page 26, 6.3

Software Registers Summary (Page 16) on page 28,

and 6.4 Software Registers Summary (Page 17) on page 30. The checksum for all registers marked with an asterisk symbol (*) is computed at the rate of OWR. The checksum result is stored in the RegChk register. After the CS5490 has been fully configured and loaded with the calibrations, the host microcontroller should keep a copy of the checksum (RegChk_Copy) in its memory. In normal operation, the host microcontroller can read the RegChk register and compare it with the saved copy of the RegChk register. If the two values mismatch, a reload of configurations and calibrations into the CS5490 is necessary.

The automatic checksum computation can be disabled by setting the REG_CSUM_OFF bit in the Config2 register.

6. HOST COMMANDS AND REGISTERS

Page Select C md.

DATA DATA DATA

Read Cmd.

DATA DATA DATA

Write Cmd.

Inst ructio n

CS5490

6.1 Host Commands

The first byte sent to the CS5490 RX pin contains the host command. Four types of host commands are required to read and write registers and instruct the calculation engine. The two most significant bits (MSBs) of the host command defines the function to be performed. The following table depicts the types of commands.

Table 2. Command Format

Function Binary Value Note

Read

Write

Page Select

Instruction

6.1.1 Memory Access Commands

The CS5490 memory has 12-bit addresses and is organized as P 64 pages of 64 addresses each. The higher 6 bits specify the page number. The lower 6 bits specify the address within the selected page.

6.1.1.1 Page Select

A page select command is designated by setting the two MSBs of the command to binary ‘10’. The page select command provides the CS5490 with the page number of the register to access. Register read and write commands access 1 of 64 registers within a specified page. Subsequent register reads and writes can be performed once the page has been selected.

Figure 14. Byte Sequence for Page Select

6.1.1.2 Register Read

A register read is designated by setting the two MSBs of the command to binary ‘00’. The lower 6 bits of the read register command are the lower 6 bits of the 12-bit register address. After the register read command has been received, the CS5490 will send 3 bytes of register data onto the TX pin.

0 0 A

5A4A3A2A1A0

0 1 A

5A4A3A2A1A0

1 0 P

5P4P3P2P1P0

1 1 C

5C4C3C2C1C0

5P4P3P2P1P0A5A4A3A2A1A0

specifies the

[5:0]

specifies the

[5:0]

page.

specifies the

[5:0]

instruction.

6.1.1.3 Register Write

A register write command is designated by setting the two MSBs of the command to binary ‘01’. The lower 6 bits of the register write command are the lower 6 bits of the 12-bit register address. A register write command must be followed by 3 bytes of data.

Figure 16. Byte Sequence for Register Write

6.1.2 Instructions

An instruction command is designated by setting the two MSBs of the command to binary '11'. An instruction command will interrupt any process currently running and initiate a new process in the CS5490.

Figure 17. Byte Sequence for Instructions

These new processes include calibration, power control, and soft reset. The following table depicts the types of instructions. Note that when the CS5490 is in continuous conversion mode, an unexpected or invalid instruction command could cause the device to stop continuous conversion and enter an unexpected operation mode. The host processor should keep monitoring the CS5490 operation status and react accordingly.

Table 3. Instruction Format

Function Binary Value Note

0 C

Controls

Calibration

0 00001 - Software Reset 0 00010 - Standby 0 00011 - Wakeup 0 10100 - Single Conv. 0 10101 - Continuous Conv. 0 11000 - Halt Conv.

1 00 C2C1C0 DC Offset 1 10 C 1 11 C *AC offset calibration valid

only for current channel.

1 C4C3 0 0 1 I 1 C 1 C

4C3C2C1C0

1 C

4C3C2C1C0

2C1C0

4C3C2C1C0

0 1 0 V

4C3

1 1 0 I & V

4C3

AC Offset* Gain

specifies

[5]

the instruction type: 0 = Controls 1 = Calibrations

For calibration, C

specifies

[4:3]

the type of calibration.

For calibration, C

specifies

[2:0]

the channel(s).

Figure 15. Byte Sequence for Register Read

24 DS982F3

6.1.3 Checksum

ChecksumPage Select C md.

CHECKSUM

DATA DATA DATA CHECKSUM

Read Cmd.

DATA DATA DATA CH ECKSUMWrite Cmd.

ChecksumInstructio n

Page Select

Instruction

Read Command

Write Command

To improve the communication reliability on the serial interface, the CS5490 provides a checksum mechanism on transmitted and received signals. Checksum is disabled by default but can be enabled by setting the appropriate bit in the SerialCtrl register. When enabled, both host and CS5490 are expected to send one additional checksum byte after the normal command byte and applicable 3-byte register data have been transmitted.

The checksum is calculated by subtracting each transmit byte from 0xFF. Any overflow is truncated and the result wraps. The CS5490 executes the command only if the checksum transmitted by the host matches the checksum calculated locally. Otherwise, it sets a status bit (RX_CSUM_ERR in Status0 register), ignores the command, and clears the serial interface in preparation for the next transmission.

CS5490

Figure 18. Byte Sequence for Checksum

6.1.4 Serial Time Out

In case a transaction from the host is not completed (for example, a data byte is missing in a register write), a time out circuit will reset the interface after 128ms. This will require that each byte be sent from the host within 128ms of the previous byte.

DS982F3 25

6.2 Hardware Registers Summary (Page 0)

Address2RA[5:0] Name Description

0* 00 0000 Config0 Configuration 0 Y Y 0x C0 2000 1* 00 0001 Config1 Configuration 1 Y Y 0x 00 EEEE 2 00 0010 - Reserved 3* 00 0011 Mask Interrupt Mask Y Y 0x 00 0000 4 00 0100 - Reserved - 5* 00 0101 PC Phase Compensation Control Y Y 0x 00 0000 6 00 0110 - Reserved - 7* 00 0111 SerialCtrl UART Control Y Y 0x 02 004D 8* 00 1000 PulseWidth Energy Pulse Width Y Y 0x 00 0001 9* 00 1001 PulseCtrl Energy Pulse Control Y Y 0x 00 0000 10 00 1010 - Reserved - 11 00 1011 - Reserved - 12 00 1100 - Reserved - 13 00 1101 - Reserved 14 00 1110 - Reserved - 15 00 1111 - Reserved - 16 01 0000 - Reserved - 17 01 0001 - Reserved - 18 01 0010 - Reserved - 19 01 0011 - Reserved - 20 01 0100 - Reserved - 21 01 0101 - Reserved - 22 01 0110 - Reserved - 23 01 0111 Status0 Interrupt Status N N 0x 80 0000 24 01 1000 Status1 Chip Status 1 N N 0x 80 1800 25 01 1001 Status2 Chip Status 2 N N 0x 00 0000 26 01 1010 - Reserved - 27 01 1011 - Reserved - 28 01 1100 - Reserved - 29 01 1101 - Reserved - 30 01 1110 - Reserved - 31 01 1111 - Reserved - 32 10 0000 - Reserved - 33 10 0001 - Reserved - 34* 10 0010 RegLock Register Lock Control N N 0x 00 0000 35 10 0011 - Reserved - 36 10 0100 V 37 10 0101 I 38 10 0110 - Reserved - 39 10 0111 - Reserved - 40 10 1000 - Reserved - 41 10 1001 - Reserved - 42 10 1010 - Reserved - 43 10 1011 - Reserved - 44 10 1100 - Reserved - 45 10 1101 - Reserved - 46 10 1110 - Reserved - 47 10 1111 - Reserved - 48 11 0000 PSDC Phase Sequence Detection & Control N Y 0x 00 0000 49 11 0001 - Reserved - 50 11 0010 - Reserved - 51 11 0011 - Reserved - 52 11 0100 - Reserved - -

PEAK

Peak Voltage N Y 0x 00 0000 Peak Current N Y 0x 00 0000

DSP3HOST3Default

CS5490

26 DS982F3

53 11 0101 - Reserved - 54 11 0110 - Reserved - 55 11 0111 ZX 56 11 1000 - Reserved - 57 11 1001 - Reserved - 58 11 1010 - Reserved - 59 11 1011 - Reserved - 60 11 1100 - Reserved - 61 11 1101 - Reserved - 62 11 1110 - Reserved - 63 11 1111 - Reserved - -

Notes: (1) Warning: Do not write to unpublished or reserved register locations.

(2) * Registers with checksum protection.

(3) Registers that can be set to write protect from DSP and/or HOST.

NUM

Num. Zero Crosses used for Line Freq. Y Y 0x00 0064

CS5490

DS982F3 27

6.3 Software Registers Summary (Page 16)

Address2RA[5:0] Name Description

0* 00 0000 Config2 Configuration 2 Y Y 0x 10 0200 1 00 0001 RegChk Register Checksum N Y 0x 00 0000 2 00 0010 I I Instantaneous Current N Y 0x 00 0000 3 00 0011 V V Instantaneous Voltage N Y 0x 00 0000 4 00 0100 P Instantaneous Power N Y 0x 00 0000 5 00 0101 P 6 00 0110 I 7 00 0111 V

AVG

RMS

Active Power N Y 0x 00 0000 I RMS Current N Y 0x 00 0000

V RMS Voltage N Y 0x 00 0000 8 00 1000 - Reserved 9 00 1001 - Reserved 10 00 1010 - Reserved 11 00 1011 - Reserved 12 00 1100 - Reserved 13 00 1101 - Reserved 14 00 1110 Q

AVG

Reactive Power N Y 0x 00 0000 15 00 1111 Q Instantaneous Reactive Power N Y 0x 00 0000 16 01 0000 - Reserved 17 01 0001 - Reserved 18 01 0010 - Reserved 19 01 0011 - Reserved 20 01 0100 S Apparent Power N Y 0x 00 0000 21 01 0101 PF Power Factor N Y 0x 00 0000 22 01 0110 - Reserved 23 01 0111 - Reserved 24 01 1000 - Reserved 25 01 1001 - Reserved 26 01 1010 - Reserved 27 01 1011 T Temperature N Y 0x 00 0000 28 01 1100 - Reserved 29 01 1101 P 30 01 1110 S 31 01 1111 Q 32* 10 0000 I 33* 10 0001 I 34* 10 0010 V 35* 10 0011 V 36* 10 0100 P 37* 10 0101 I

SUM SUM

SUM DCOFF GAIN

DCOFF GAIN OFF

ACOFF

Total Active Power N Y 0x 00 0000 Total Apparent Power N Y 0x 00 0000 Total Reactive Power N Y 0x 00 0000 I DC Offset Y Y 0x 00 0000 I Gain Y Y 0x 40 0000 V DC Offset Y Y 0x 00 0000 V Gain Y Y 0x 40 0000 Instantaneous Power Offset 0x 00 0000

I AC Offset Y Y 0x 00 0000 38* 10 0110 - Reserved 39* 10 0111 - Reserved 40* 10 1000 - Reserved 41* 10 1001 - Reserved 42* 10 1010 - Reserved 43* 10 1011 - Reserved 44* 10 1100 - Reserved 45* 10 1101 - Reserved 46 10 1110 - Reserved 47 10 1111 - Reserved 48 11 0000 - Reserved 49 11 0001 Epsilon Ratio of Line to Sample Frequency N Y 0x 01 999A 50* 11 0010 - Reserved 51** 11 0011 SampleCount Sample Count N Y 0x 00 0FA0 52 11 0100 - Reserved -

DSP3HOST3Default

CS5490

28 DS982F3

53 11 0101 - Reserved 54* 11 0110 T 55* 11 0111 T

GAIN OFF

Temperature Gain Y Y 0x 06 B716

Temperature Offset Y Y 0x D5 3998 56* 11 1000 - Reserved 57 11 1001 T

SETTLE

58* 11 1010 Load

MIN

Filter Settling Time to Conv. Startup Y Y 0x 00 001E

No Load Threshold Y Y 0x 00 0000 59* 11 1011 - Reserved 60* 11 1100 SYS

GAIN

System Gain N Y 0x 50 0000 61 11 1101 Time System Time (in samples) N Y 0x 00 0000 62 11 1110 - Reserved 63 11 1111 - Reserved -

Notes: (1) Warning: Do not write to unpublished or reserved register locations.

(2) * Registers with checksum protection.

** When setting the AVG_MODE bit (AVG_MODE = ‘1’) in the Config2 register, the device will

use the Line-cycle Synchronized Averaging mode and the CycleCount register will be included in the checksum. Otherwise the SampleCount register will be included.

(3) Registers that can be set to write protect from DSP and/or HOST.

CS5490

DS982F3 29

6.4 Software Registers Summary (Page 17)

Address2RA[5:0] Name Description

0* 00 0000 VSag 1* 00 0001 VSag

DUR Level

V Sag Duration Y Y 0x 00 0000

V Sag Level Y Y 0x 00 0000 2 00 0010 - Reserved 3 00 0011 - Reserved 4* 00 0100 IOver 5* 00 0101 IOver

DUR LEVEL

I Overcurrent Duration Y Y 0x 00 0000

I Overcurrent Level Y Y 0x 7F FFFF 6 00 0110 - Reserved 7 00 0111 - Reserved 8* 00 1000 - Reserved 9* 00 1001 - Reserved 10 00 1010 - Reserved 11 00 1011 - Reserved 12* 00 1100 - Reserved 13* 00 1101 - Reserved 14 00 1110 - Reserved 15 00 1111 - Reserved 16 01 0000 - Reserved 17 01 0001 - Reserved 18 01 0010 - Reserved 19 01 0011 - Reserved 20 01 0100 - Reserved 21 01 0101 - Reserved 22 01 0110 - Reserved 23 01 0111 - Reserved 24 01 1000 - Reserved 25 01 1001 - Reserved 26 01 1010 - Reserved 27 01 1011 - Reserved 28 01 1100 - Reserved 29 01 1101 - Reserved 30 01 1110 - Reserved 31 01 1111 - Reserved -

Notes: (1) Warning: Do not write to unpublished or reserved register locations.

(2) * Registers with checksum protection.

DSP3HOST3Default

CS5490

(3) Registers that can be set to write protect from DSP and/or HOST.

30 DS982F3

6.5 Software Registers Summary (Page 18)

Address2RA[5:0] Name Description

24* 01 1000 IZX

LEVEL

I-channel Zero-crossing Threshold Y Y 0x 10 0000 25 01 1001 - Reserved 26 01 1010 - Reserved 27 01 1011 - Reserved 28* 01 1100 PulseRate Energy Pulse Rate Y Y 0x 80 0000 29 01 1101 - Reserved 30 01 1110 - Reserved 31 01 1111 - Reserved 32 10 0000 - Reserved 33 10 0001 - Reserved 34 10 0010 - Reserved 35 10 0011 - Reserved 36 10 0100 - Reserved 37 10 0101 - Reserved 38 10 0110 - Reserved 39 10 0111 - Reserved 40 10 1000 - Reserved 41 10 1001 - Reserved 42 10 1010 - Reserved 43* 10 1011 INT

GAIN

Rogowski Coil Integrator Gain Y Y 0x 14 3958 44 10 1100 - Reserved 45 10 1101 - Reserved 46* 10 1110 VSwell 47* 10 1111 VSwell

DUR LEVEL

V Swell Duration Y Y 0x 00 0000

V Swell Level Y Y 0x 7F FFFF 48 11 0000 - Reserved 49 11 0001 - Reserved 50* 11 0010 - Reserved 51* 11 0011 - Reserved 52 11 0100 - Reserved 53 11 0101 - Reserved 54 11 0110 - Reserved 55 11 0111 - Reserved 56 11 1000 - Reserved 57 11 1001 - Reserved 58* 11 1010 VZX

LEVEL

V-channel Zero-crossing Threshold Y Y 0x 10 0000 59 11 1011 - Reserved 60 11 1100 - Reserved 61 11 1101 - Reserved 62** 11 1110 CycleCount Line Cycle Count N Y 0x 00 0064 63* 11 1111 Scale Scale Value for I-channel Gain Calibration Y Y 0x 4C CCCC

DSP3HOST3Default

CS5490

Notes: (1) Warning: Do not write to unpublished or reserved register locations.

(2) * Registers with checksum protection.

** When setting the AVG_MODE bit (AVG_MODE = ‘1’) in the Config2 register, the device will

use the Line-cycle Synchronized Averaging mode and the CycleCount register will be included in the checksum. Otherwise the SampleCount register will be included.

(3) Registers that can be set to write protect from DSP and/or HOST.

DS982F3 31

CS5490

6.6 Register Descriptions

21. “Default” = bit states after power-on or reset

22. DO NOT write a “1” to any unpublished register bit or to a bit published as “0”.

23. DO NOT write a “0” to any bit published as “1”.

24. DO NOT write to any unpublished register address.

6.6.1 Configuration 0 (Config0) – Page 0, Address 0

23 22 21 20 19 18 17 16

1100- -- -

15 14 13 12 11 10 9 8

-01- ---INT_POL

76543210

- - IPGA[1] IPGA[0] - NO_OSC 0 0

Default = 0xC0 2000

[23:9] Reserved.

INT_POL Interrupt Polarity.

0 = Active low (Default) 1 = Active high

[7:6] Reserved.

IPGA[1:0] Select PGA gain for I channel.

00 = gain (Default) 10 = 50x gain

[3] Reserved.

NO_OSC Disable crystal oscillator (making XIN a logic-level input).

0 = Crystal oscillator enabled (Default) 1 = Crystal oscillator disabled

32 DS982F3

CS5490

6.6.2 Configuration 1 (Config1) – Page 0, Address 1

23 22 21 20 19 18 17 16

000EPG_ON000DO_OD

15 14 13 12 11 10 9 8

11101110

76543210

1 1 1 0 DOMODE[3] DOMODE[2] DOMODE[1] DOMODE[0]

Default = 0x00 EEEE

[23:21] Reserved.

EPG_ON Enable EPG block.

0 = Disable energy pulse generation block (Default) 1 = Enable energy pulse generation block

[19:17] Reserved.

DO_OD Allow the DO pin to be an open-drain output.

0 = Normal output (Default) 1 = Open-drain output

[15:4] Reserved.

DOMODE[3:0] Output control for DO pin.

0000 = Energy pulse generation (EPG) block output 0001 = Reserved 0010 = Reserved 0011 = Reserved 0100 = P sign 0101 = Reserved 0110 = P

SUM

sign 0111 = Q sign 1000 = Reserved 1001 = Q

SUM

sign 1010 = Reserved 1011 = V zero-crossing 1100 = I zero-crossing 1101 = Reserved 1110 = Hi-Z, pin not driven (Default) 1111 = Interrupt

DS982F3 33

CS5490

6.6.3 Configuration 2 (Config2) – Page 16, Address 0

23 22 21 20 19 18 17 16

-POS- 1 - 0 0-

15 14 13 12 11 10 9 8

- APCM - ZX_LPF AVG_MODE REG_CSUM_OFF AFC 0

76543 2 10

0 0 0 IFLT[1] IFLT[0] VFLT[1] VFLT[0] IIR_OFF

Default = 0x10 0200

[23] Reserved.

POS Positive energy only. Suppress negative values in P

a zero result will be stored. 0 = Positive and negative energy (Default) 1 = Positive energy only

[21:15] Reserved.

APCM Selects the apparent power calculation method.

0 = V 1 = SQRT(P

RMS

x I

RMS

AVG

(Default)

+ Q

AVG

)

[13] Reserved.

ZX_LPF Enable LPF in zero-cross detect.

0 = LPF disabled (Default) 1 = LPF enabled

. If a negative value is calculated,

AVG

AVG_MODE Select averaging mode for low-rate calculations.

0 = Use SampleCount (Default) 1 = Use CycleCount

REG_CSUM_OFFDisable checksum on critical registers.

0 = Enable checksum on critical registers (Default) 1 = Disable checksum on critical registers

AFC Enables automatic line frequency measurement which sets Epsilon every time a new line

frequency measurement completes. Epsilon is used to control the gain of 90° phase shift integrator used in quadrature power calculations. 0 = Disable automatic line frequency measurement 1 = Enable automatic line frequency measurement (Default)

[8:5] Reserved.

IFLT[1:0] Filter enable for current channel.

00 = No filter (Default) 01 = High-pass filter (HPF) on current channel 10 = Phase-matching filter (PMF) on current channel 11 = Rogowski coil integrator (INT) on current channel

VFLT[1:0] Filter enable for voltage channel.

00 = No filter (Default) 01 = High-pass filter (HPF) on voltage channel 10 = Phase-matching filter (PMF) on voltage channel 11 = Reserved

IIR_OFF[0] Bypass IIR filter.

0 = Do not bypass IIR filter (Default) 1 = Bypass IIR filter

34 DS982F3

CS5490

6.6.4 Phase Compensation (PC) – Page 0, Address 5

23 22 21 20 19 18 17 16

- - CPCC[1] CPCC[0] - - - -

15 14 13 12 11 10 9 8

-------FPCC[8]

76543210

FPCC[7] FPCC[6] FPCC[5] FPCC[4] FPCC[3] FPCC[2] FPCC[1] FPCC[0]

Default = 0x00 0000

[23:22] Reserved.

CPCC[1:0] Coarse phase compensation control for I & V.

00 = No extra delay 01 = 1 OWR delay in current channel 10 = 1 OWR delay in voltage channel 11 = 2 OWR delay in voltage channel

[19:9] Reserved.

FPCC[8:0] Fine phase compensation control for I & V.

Sets a delay in current, relative to voltage. Resolution: 0.008789° at 50Hz and 0.010547° at 60Hz (OWR = 4000)

6.6.5 UART Control (SerialCtrl) – Page 0, Address 7

23 22 21 20 19 18 17 16

- - - - - RX_PU_OFF RX_CSUM_OFF -

15 14 13 12 11 10 9 8

BR[15] BR[14] BR[13] BR[12] BR[11] BR[10] BR[9] BR[8]

765432 10

BR[7] BR[6] BR[5] BR[4] BR[3] BR[2] BR[1] BR[0]

Default = 0x02 004D

[23:19] Reserved.

RX_PU_OFF Disable the pull-up resistor on the RX input pin.

0 = Pull-up resistor enabled (Default) 1 = Pull-up resistor disabled

RX_CSUM_OFF Disable the checksum on serial port data.

0 = Enable checksum 1 = Disable checksum (Default)

[16] Reserved.

BR[15:0] Baud rate (serial bit rate).

BR[15:0] = Baud Rate x 524288 / MCLK

DS982F3 35

CS5490

6.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8

23 22 21 20 19 18 17 16

- - - - FREQ_RNG[3] FREQ_RNG[2] FREQ_RNG[1] FREQ_RNG[0]

15 14 13 12 11 10 9 8

PW[15] PW[14] PW[13] PW[12] PW[11] PW[10] PW[9] PW[8]

76543210

PW[7] PW[6] PW[5] PW[4] PW[3] PW[2] PW[1] PW[0]

Default = 0x00 0001 (265.6µs at OWR = 4 kHz)

PulseWidth sets the energy pulse frequency range and the duration of energy pulses.

The actual pulse duration is 250 µs plus the contents of PulseWidth divided by 64,000. PulseWidth is an integer in the range of 1 to 65,535.

[23:20] Reserved.

FREQ_RNG[19:16] Energy pulse (PulseRate) frequency range for 0.1% resolution.

0000 = Freq. range: 2 kHz – 0.238 Hz (Default) 0001 = Freq. range: 1 kHz – 0.1192 Hz 0010 = Freq. range: 500 Hz – 0.0596 Hz 0011 = Freq. range: 250Hz – 0.0298Hz 0100 = Freq. range: 125 Hz – 0.0149 Hz 0101 = Freq. range: 62.5 Hz – 0.00745 Hz 0110 = Freq. range: 31.25 Hz – 0.003725 Hz 0111 = Freq. range: 15.625 Hz – 0.0018626 Hz 1000 = Freq. range: 7.8125 Hz – 0.000931323 Hz 1001 = Freq. range: 3.90625 Hz – 0.000465661 Hz 1010 = Reserved

...

1111 = Reserved

PW[15:0] Energy Pulse Width.

6.6.7 Pulse Output Rate (PulseRate) – Page 18, Address 28

MSB LSB

-(2

)2-12

Default= 0x80 0000

PulseRate sets the full-scale frequency for the energy pulse output.

For a 4 kHz OWR rate, the maximum pulse rate is 2 kHz. It is a two's complement value in the range of

-1  value  1, with the binary point to the left of the MSB.

Refer to section 5.5 Energy Pulse Generation on page 19 for more information.

36 DS982F3

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

-23

CS5490

6.6.8 Pulse Output Control (PulseCtrl) – Page 0, Address 9

23 22 21 20 19 18 17 16

--------

15 14 13 12 11 10 9 8

00000000

76543210

0 0 0 0 EPGIN[3] EPGIN[2] EPGIN[1] EPGIN[0]

Default = 0x00 0000

This register controls the input to the energy pulse generation (EPG) block.

[23:4] Reserved.

EPGIN[3:0] Selects the input to the energy pulse generation (EPG) block.

0000 = P 0001 = Reserved 0010 = P 0011 = Q 0100 = Reserved 0101 = Q 0110 = S 0111 = Reserved 1000 = S 1001 = Unused

...

1111 = Unused

AVG

SUM

AVG

SUM

(Default)

6.6.9 Register Lock Control (RegLock) – Page 0, Address 34

23 22 21 20 19 18 17 16

--------

15 14 13 12 11 10 9 8

- - - DSP_LCK[4] DSP_LCK[3] DSP_LCK[2] DSP_LCK[1] DSP_LCK[0]

76543210

- - - HOST_LCK[4] HOST_LCK[3] HOST_LCK[2] HOST_LCK[1] HOST_LCK[0]

Default = 0x00 0000

[23:13] Reserved.

DSP_LCK[12:8] DSP_LCK[4:0] = 0x16 sets the DSP lockable registers to be write protected from the

CS5490 internal calculation engine. Writing 0x09 unlocks the registers.

[7:5] Reserved.

HOST_LCK[4:0] HOST_LCK[4:0] = 0x16 sets all the registers except RegLock, Status0, Status1, and

Status2 to be write protected from the serial interface. Writing 0x09 unlocks the registers.

DS982F3 37

CS5490

6.6.10 Phase Sequence Detection and Control (PSDC) – Page 0, Address 48

23 22 21 20 19 18 17 16

DONE PSCNT[6] PSCNT[5] PSCNT[4] PSCNT[3] PSCNT[2] PSCNT[1] PSCNT[0]

15 14 13 12 11 10 9 8

------ --

765432 10

- - DIR CODE[4] CODE[3] CODE[2] CODE[1] CODE[0]

Default = 0x00 0000

DONE Indicates valid count values reside in PSCNT[6:0].

0 = Invalid values in PSCNT[6:0]. (Default) 1 = Valid values in PSCNT[6:0].

PSCNT[6:0] Registers the number of OWR samples from the start time to the time when the next

zero crossing is detected.

[15:6] Reserved.

DIR Set the zero-crossing edge direction which will stop PSCNT count.

0 = Stop count at negative to positive zero-crossing - Rising Edge. (Default) 1 = Stop count at positive to negative zero-crossing - Falling Edge.

CODE[4:0] Write 10110 to this location to enable the phase sequence detection.

6.6.11 Checksum of Critical Registers (RegChk) – Page 16, Address 1

MSB LSB

.....

Default = 0x00 0000

This register contains the checksum of critical registers.

38 DS982F3

CS5490

6.6.12 Interrupt Status (Status0) – Page 0, Address 23

23 22 21 20 19 18 17 16

DRDY CRDY WOF - - MIPS - VSWELL

15 14 13 12 11 10 9 8

- POR - IOR - VOR - IOC

76543 2 10

- VSAG TUP FUP IC RX_CSUM_ERR -

Default = 0x 00 0000

The Status0 register indicates a variety of conditions within the chip.

Writing a one to a Status0 register bit will clear that bit. Writing a zero to any bit has no effect.

DRDY Data Ready. During conversion, this bit indicates that low-rate results have been updated.

It indicates completion of other host instruction and the reset sequence.

CRDY Conversion Ready. Indicates that sample rate (output word rate) results have been updat-

ed.

WOF Watchdog timer overflow.

RX_TO

[20:19] Reserved.

MIPS MIPS overflow.

Sets when the calculation engine has not completed processing a sample before the next one arrives.

[17] Reserved.

VSWELL Voltage channel swell event detected.

[15] Reserved.

POR Power out of range. Sets when the measured power would cause the P register to overflow.

[13] Reserved.

IOR Current out of range. Set when the measured current would cause the I register to overflow.

[11] Reserved.

VOR Voltage out of range. Set when the measured voltage would cause the V register to over-

flow.

[7] Reserved.

IOC I Overcurrent.

[9] Reserved.

VSAG Voltage channel sag event detected.

TUP Temperature updated. Indicates when the Temperature register (T) has been updated.

FUP Frequency updated. Indicates the Epsilon register has been updated.

IC Invalid command has been received.

RX_CSUM_ERR Received data checksum error. Sets to one automatically if checksum error is detected on

serial port received data.

RX_TO SDI/RX time out. Sets to one automatically when SDI/RX time out occurs.

DS982F3 39

CS5490

6.6.13 Interrupt Mask (Mask) – Page 0, Address 3

23 22 21 20 19 18 17 16

DRDY CRDY WOF - - MIPS 0 VSWELL

15 14 13 12 11 10 9 8

0 POR 0 IOR 0 VOR 0 IOC

76543 2 10

0 VSAG TUP FUP IC RX_CSUM_ERR -

Default = 0x00 0000

RX_TO

The Mask register is used to control the activation of the INT the corresponding Status0 register bit to activate the INT

pin. Writing a '1' to a Mask register bit will allow

pin when set.

[23:0] Enable/disable (mask) interrupts.

0 = Interrupt disabled (Default) 1 = Interrupt enabled

6.6.14 Chip Status 1 (Status1) – Page 0, Address 24

23 22 21 20 19 18 17 16

------

15 14 13 12 11 10 9 8

LCOM[7] LCOM[6] LCOM[5] LCOM[4] LCOM[3] LCOM[2] LCOM[1] LCOM[0]

76543210

----TODVOD-IOD

Default = 0x00 0000

This register indicates a variety of conditions within the chip.

[23:16] Reserved.

LCOM[15:8] Indicates the value of the last serial command executed.

[7:4] Reserved.

TOD Modulator oscillation has been detected in the temperature ADC.

VOD Modulator oscillation has been detected in the voltage ADC.

[1] Reserved.

IOD Modulator oscillation has been detected in the current ADC.

40 DS982F3

CS5490

6.6.15 Chip Status 2 (Status2) – Page 0, Address 25

23 22 21 20 19 18 17 16

--------

15 14 13 12 11 10 9 8

--------

76543210

- - QSUM_SIGN - Q_SIGN PSUM_SIGN - P_SIGN

Default = 0x00 0000

This register indicates a variety of conditions within the chip.

[23:6] Reserved.

QSUM_SIGN Indicates the sign of the value contained in Q

0 = positive value 1 = negative value

[4] Reserved.

Q_SIGN Indicates the sign of the value contained in Q

0 = positive value 1 = negative value

PSUM_SIGN Indicates the sign of the value contained in P

0 = positive value 1 = negative value

SUM

AVG

SUM

[1] Reserved.

P_SIGN Indicates the sign of the value contained in P

AVG

. 0 = positive value 1 = negative value

6.6.16 Line to Sample Frequency Ratio (Epsilon) – Page 16, Address 49

MSB LSB

-(2

)2-12

Default = 0x01 999A (0.0125 or 50Hz/ 4.0kHz)

Epsilon is the ratio of the input line frequency to the output word rate (OWR).

It can either be written by the application program or calculated automatically from the line frequency (from the voltage channel input) using the AFC bit in the Config2 register. It is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB. Negative values are not used.

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

-23

DS982F3 41

CS5490

6.6.17 No Load Threshold (Load

) – Page 16, Address 58

MIN

MSB LSB

)2-12

-(2

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x00 0000

Load

When the magnitudes of P the magnitude of S

Load

is used to set the no-load threshold for the anti-creep function.

MIN

and Q

SUM

is less than Load

SUM

is a two’s complement value in the range of -1.0  value  1.0, with the binary point to the right of the

MIN

are less than Load

SUM

, S

MIN

is forced to zero.

SUM

MIN

, P

SUM

and Q

are forced to zero. When

SUM

MSB. Negative values are not used.

6.6.18 Sample Count (SampleCount) – Page 16, Address 51

MSB LSB

Default = 0x00 0FA0 (4000)

Determines the number of output word rate (OWR) samples to use in calculating low-rate results. SampleCount (N) is an integer in the range of 100 to 8,388,607. Values less than 100 should not be used.

.....

-23

6.6.19 Cycle Count (CycleCount) – Page 18, Address 62

MSB LSB

Default = 0x00 0064 (100)

Determines the number of half-line cycles to use in calculating low-rate results when the CS5490 is in Line-cycle Synchronized Averaging mode.

CycleCount is an integer in the range of 1 to 8,388,607. Zero should not be used.

6.6.20 Filter Settling Time for Conversion Startup (T

MSB LSB

Default = 0x00 001E (30)

Sets the number of output word rate (OWR) samples that will be used to allow filters to settle at the beginning of Conversion and Calibration commands.

This is an integer in the range of 0 to 16,777,215 samples.

.....

SETTLE

.....

) – Page 16, Address 57

42 DS982F3

CS5490

6.6.21 System Gain (Sys

) – Page 16, Address 60

GAIN

MSB LSB

-(21)202

-1

-2

-3

-4

-5

-6

.....

-16

-17

-18

-19

-20

-21

Default = 0x50 0000 (1.25)

System Gain (Sys

By default, Sys

GAIN

) is applied to all channels.

GAIN

= 1.25, but can be finely adjusted to compensate for voltage reference error. It is a two's

complement value in the range of -2.0  value  2.0, with the binary point to the right of the second MSB. Values should be kept within 5% of 1.25.

6.6.22 Rogowski Coil Integrator Gain (Int

MSB LSB

-(20)2-12

-2

-3

-4

-5

) – Page 18, Address 43

GAIN

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x14 3958

Gain for the Rogowski coil integrator. This must be programmed accordingly for 50Hz and 60Hz (0.158 for 50Hz, 0.1875 for 60 Hz).

This is a two’s complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB. Negative values are not used.

-22

-23

6.6.23 System Time (Time) – Page 16, Address 61

MSB LSB

6.6.24 Voltage Sag Duration (VSag

MSB LSB

.....

Default = 0x00 0000

System Time (Time) is measured in output word rate (OWR) samples.

This is an unsigned integer in the range of 0 to 16,777,215 samples. At OWR = 4.0 kHz, OWR will overflow every 1 hour, 9 minutes, 54 seconds. Time can be used by the application to manage real-time events.

) – Page 17, Address 0

DUR

.....

Default = 0x00 0000

Voltage sag duration, VSag

, determines the count of output word rate (OWR) samples utilized to deter-

DUR

mine a sag event.

These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature.

DS982F3 43

CS5490

6.6.25 Voltage Sag Level (VSag

) – Page 17, Address 1

LEVEL

MSB LSB

-(20)2-12

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x00 0000

Voltage sag level, VSag

, establishes an input level below which a sag event is triggered.

LEVEL

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.26 Current Overcurrent Duration (IOver

MSB LSB

) – Page 17, Address 4

DUR

.....

Default = 0x00 0000

Overcurrent duration, IOver

, determines the count of output word rate (OWR) samples utilized to deter-

DUR

mine an overcurrent event.

These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature.

-23

6.6.27 Current Overcurrent Level (IOver

) – Page 17, Address 5

LEVEL

MSB LSB

-(20)2-12

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x7F FFFF

Overcurrent level, IOver

, establishes an input level above which an overcurrent event is triggered.

LEVEL

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.28 Voltage Swell Duration (VSwell

MSB LSB

) – Page 18, Address 46

DUR

.....

Default = 0x00 0000

Voltage swell duration, VSwell

, determines the count of output word rate (OWR) samples used to deter-

DUR

mine a swell event.

These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature.

-23

44 DS982F3

CS5490

6.6.29 Voltage Swell Level (VSwell

LEVEL

) – Page 18, Address 47

MSB LSB

-(20)2-12

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x7F FFFF

Voltage swell level, VSwell

, establishes an input level above which a swell event is triggered.

LEVEL

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.30 Instantaneous Current (I) – Page 16, Address 2

MSB LSB

)2-12

-(2

Default = 0x00 0000

I contains instantaneous current measurements for current channel.

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

-23

6.6.31 Instantaneous Voltage (V) – Page 16, Address 3

MSB LSB

-(20)2-12

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x00 0000

V contains instantaneous voltage measurements for voltage channel.

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

6.6.32 Instantaneous Active Power (P) – Page 16, Address 4

MSB LSB

-(20)2-12

-2

Default = 0x00 0000

P contains instantaneous power measurements for current and voltage channels.

Values in registers I and V are multiplied to generate this value. This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

-23

DS982F3 45

CS5490

6.6.33 Active Power (P

) – Page 16, Address 5

AVG

MSB LSB

-(20)2-12

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x00 0000

Instantaneous power is averaged over each low-rate interval (SampleCount samples) and then added with power offset (P

) to compute active power (P

OFF

AVG

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

6.6.34 RMS Current (I

MSB LSB

-1

-2

-3

) – Page 16, Address 6

RMS

-4

-5

-6

-7

-8

.....

-18

-19

-20

-21

-22

-23

Default = 0x00 0000

contains the root mean square (RMS) values of I, calculated during each low-rate interval.

RMS

This is an unsigned value in the range of 0 value1.0, with the binary point to the left of the MSB.

-23

-24

6.6.35 RMS Voltage (V

) – Page 16, Address 7

RMS

MSB LSB

-1

-2

-3

-4

-5

-6

-7

-8

.....

-18

-19

-20

-21

-22

-23

Default = 0x00 0000

contains the root mean square (RMS) value of V, calculated during each low-rate interval.

RMS

This is an unsigned value in the range of 0 value1.0, with the binary point to the left of the MSB.

6.6.36 Reactive Power (Q

MSB LSB

-(20)2-12

-2

-3

) – Page 16, Address 14

Avg

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x00 0000

Reactive power (Q

OFF

) is Q averaged over each low-rate interval (SampleCount samples) and corrected by

AVG

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

-24

-23

46 DS982F3

CS5490

6.6.37 Instantaneous Quadrature Power (Q) – Page 16, Address 15

MSB LSB

-(20)2-12

-2

Default = 0x00 0000

Instantaneous quadrature power, Q, the product of V shifted 90° and I.

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

-23

6.6.38 Peak Current (I

) – Page 0, Address 37

PEAK

MSB LSB

)2-12

-(2

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x00 0000

Peak current (I

) contains the value of the instantaneous current 1 sample with the greatest magnitude

PEAK

detected during the last low-rate interval.

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

6.6.39 Peak Voltage (V

MSB LSB

-(20)2-12

-2

-3

) – Page 0, Address 36

PEAK

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x00 0000

Peak voltage (V

) contains the value of the instantaneous voltage sample with the greatest magnitude

PEAK

detected during the last low-rate interval.

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

-23

6.6.40 Apparent Power (S) – Page 16, Address 20

MSB LSB

-1

Default = 0x00 0000

Apparent power 1 (S) is the product of V

This is an unsigned value in the range of 0  value  1.0, with the binary point to the right of the MSB.

DS982F3 47

-2

-3

-4

-5

-6

RMS

-7

and I

.....

or SQRT(P

RMS

-17

-18

AVG

+ Q

-19

AVG

-20

-21

-22

-23

CS5490

6.6.41 Power Factor (PF) – Page 16, Address 21

MSB LSB

-(20)2-12

Default = 0x00 0000

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

-23

Power factor (PF) is calculated by dividing active power (P

The sign is determined by the active power (P

AVG

) sign.

) by apparent power (S).

AVG

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

6.6.42 Temperature (T) – Page 16, Address 27

MSB LSB

-(2

)262

Default = 0

T contains results from the on-chip temperature measurement.

By default, T uses the Celsius scale and is a two's complement value in the range of -128.0  value  128.0 (°C), with the binary point to the right of bit 16.

T can be rescaled by the application using the T

6.6.43 Total Active Power (P

MSB LSB

-(20)2-12

-2

-3

SUM

-4

) – Page 16, Address 29

-5

-6

GAIN

-7

.....

and T

.....

-10

registers.

OFF

-17

-11

-18

-12

-19

-13

-20

-14

-21

-15

-22

-16

-23

Default = 0

SUM=PAVG

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

6.6.44 Total Apparent Power (S

MSB LSB

-1

-2

-3

-4

) – Page 16, Address 30

SUM

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

-23

Default = 0

SUM

This is an unsigned value in the range of 0 value1.0, with the binary point to the right of the MSB.

48 DS982F3

CS5490

6.6.45 Total Reactive Power (Q

) – Page 16, Address 31

SUM

MSB LSB

-(20)2-12

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0

SUM=QAVG

This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

6.6.46 DC Offset for Current (I

DCOFF

MSB LSB

)2-12

-(2

-2

-3

-4

) – Page 16, Address 32

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0

DC offset registers I

are initialized to zero on reset. During DC offset calibration, selected registers are

DCOFF

written with the inverse of the DC offset measured. The application program can also write the DC offset register values. This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

6.6.47 DC Offset for Voltage (V

DCOFF

) – Page 16, Address 34

-23

MSB LSB

-(20)2-12

-2

-3

-4

-5

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0

DC offset registers V

are initialized to zero on reset. During DC offset calibration, selected registers are

DCOFF

written with the inverse of the DC offset measured. The application program can also write the DC offset register values. It is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

6.6.48 Gain for Current (I

MSB LSB

-1

-2

) – Page 16, Address 33

GAIN

-3

-4

-5

-6

.....

-16

-17

-18

-19

-20

-21

Default = 1.0

Gain register I

is initialized to 1.0 on reset. During gain calibration, the I

GAIN

multiplicative inverse of the gain measured. This is an unsigned fixed-point value in the range of 0  value  4.0, with the binary point to the right of the second MSB.

-23

-22

DS982F3 49

CS5490

6.6.49 Gain for Voltage (V

) – Page 16, Address 35

GAIN

MSB LSB

-1

-2

-3

-4

-5

-6

.....

-16

-17

-18

-19

-20

-21

Default = 1.0

Gain register V

is initialized to 1.0 on reset. During gain calibration, the V

GAIN

multiplicative inverse of the gain measured. This is an unsigned fixed-point value in the range of 0  value  4.0, with the binary point to the right of the second MSB.

6.6.50 Average Active Power Offset (P

MSB LSB

-(2

)2-12

-2

-3

-4

-5

) – Page 16, Address 36

OFF

-6

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0

Average Active Power Offset (P

) is added to the averaged active power to yield P

OFF

AVG

can be used to reduce systematic energy errors. This is a two's complement value in the range of

-1.0  value  1.0, with the binary point to the right of the MSB.

6.6.51 Average Reactive Power Offset (Q

MSB LSB

-(20)2-12

-2

-3

-4

-5

) – Page 16, Address 38

OFF

-6

-7

.....

-17

-18

-19

-20

-21

-22

-23

Default = 0x00 0000

Average Reactive Power Offset (Q

) is added to the averaged active power to yield Q

OFF

AVG

It can be used to reduce systematic energy errors. It is a two's complement value in the range of

-1.0 value 1.0, with the binary point to the right of the MSB.

6.6.52 AC Offset for Current (I

MSB LSB

-1

-2

-3

-4

-5

ACOFF

) – Page 16, Address 37

-6

-7

-8

.....

-18

-19

-20

-21

-22

-23

Default = 0

AC offset register I

is initialized to zero on reset. It is used to reduce systematic errors in the RMS re-

ACOFF

sults. This is an unsigned value in the range of 0  value  1.0, with the binary point to the left of the MSB.

6.6.53 Temperature Gain (T

MSB LSB

) – Page 16, Address 54

GAIN

.....

-10

-11

-12

-13

-14

-15

Default = 0x 06 B716

is used to scale the Temperature register (T), and is an unsigned fixed-point value in the range

GAIN

of 0.0value256.0, with the binary point to the right of bit 16.

-24

-16

GAIN

and T

registers. Refer to section 7.3 Tem-

OFF

perature Sensor Calibration on page 54 for more information.

50 DS982F3

CS5490

6.6.54 Temperature Offset (T

) – Page 16, Address 55

OFF

MSB LSB

-(27)262

.....

-10

-11

-12

-13

-14

-15

Default = 0xD5 3998

is used to offset the Temperature register (T), and is a two's complement value in the range of

OFF

-128.0value128.0 (°C), with the binary point to the right of bit 16.

GAIN

and T

registers. Refer to section 7.3 Tem-

OFF

perature Sensor Calibration on page 54 for more information.

6.6.55 Calibration Scale (Scale) – Page18, Address 63

MSB LSB

-(20)2-12

-2

Default = 0x4C CCCC (0.6)

The Scale register is used in the gain calibration to set the level of calibrated results of I-channel RMS. During gain calibration, the I register. It is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.56 Zero-crossing Number (ZX

-3

-4

results register is divided into the Scale register. The quotient is put into the I

RMS

-5

NUM

-6

-7

) – Page 0, Address 55

.....

-17

-18

-19

-20

-21

-22

-16

-23

GAIN

MSB LSB

.....

Default = 0x00 0064 (100)

is the number of zero crossings used for line frequency measurement. It is an integer in the range of

NUM

1 to 8,388,607. Zero should not be used.

6.6.57 V-channel Zero-crossing Threshold (VZX

MSB LSB

-(2

)2-12

-2

-3

-4

-5

-6

) – Page 18, Address 58

LEVEL

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x10 0000 (0.125)

VZX function. This is a two's complement value in the range of -1.0

is the level that the peak instantaneous voltage must exceed for the zero-crossing detection to

LEVEL

value<1.0, with the binary point to the right of

the MSB. Negative values are not used.

6.6.58 I-channel Zero-crossing Threshold (IZX

MSB LSB

-(20)2-12

-2

-3

-4

-5

-6

) – Page 18, Address 24

LEVEL

-7

.....

-17

-18

-19

-20

-21

-22

Default = 0x10 0000 (0.125)

-23

IZX tion. This is a two's complement value in the range of -1.0

is the level that the peak instantaneous current must exceed for the zero-crossing detection to func-

LEVEL

value<1.0, with the binary point to the right of the

MSB. Negative values are not used.

DS982F3 51

7. SYSTEM CALIBRATION

RMS

, I

RMS

Registers

Modulator Filter



* Denotes readable/writable register

Applies only to the current path (I1, I2)

N



-1



RMS

-1

RMS

0.6 ( Scale

)

V*, I*, P*, Q

Registers

GAIN

, V

GAIN

Registers

DCOFF

, V

DCOFF

Registers

ACOFF

Figure 19. Calibration Data Flow

Component tolerances, residual ADC offset, and system noise require a meter that needs to be calibrated before it meets a specific accuracy requirement. The CS5490 provides an on-chip calibration algorithm to operate the system calibration quickly and easily. Benefiting from the excellent linearity and low noise level of the CS5490, a CS5490 meter normally only needs one calibration at a single load point to achieve accurate measurements over the full load range.

7.1 Calibration in General

The CS5490 provides DC offset and gain calibration that can be applied to the instantaneous voltage and current measurements and AC offset calibration, which can only be applied to the current RMS calculation.

Since the voltage and current channels have independent offset and gain registers, offset and gain calibration can be performed on any channel independently.

The data flow of the calibration is shown in Figure 19.

Note that in Figure 19 the AC offset registers and gain registers affect the output results differently than the DC offset registers. The DC offset and gain values are applied to the voltage/current signals early in the signal path; the DC offset register and gain register values affect all CS5490 results. This is not true for the AC offset correction. The AC offset registers only affect the results of the RMS current calculation.

The CS5490 must be operating in its active state and ready to accept valid commands. Refer to section 6.1.2

Instructions on page 24 for different calibration

commands. The value in the SampleCount register determines the number (N) of output word rate (OWR)

CS5490

samples that are averaged during a calibration. The calibration procedure takes the time of N + T OWR samples. As N is increased, the calibration takes more time, but the accuracy of the calibration results tends to increase.

The DRDY bit in the Status0 register will be set at the completion of calibration commands. If an overflow occurs during calibration, other Status0 bits may be set as well.

7.1.1 Offset Calibration

During offset calibrations, no line voltage or current should be applied to the meter; the differential signal on voltage inputs VIN± or current inputs IIN± of the CS5490 should be 0 volts.

7.1.1.1 DC Offset Calibration

The DC offset calibration command measures and averages DC values read on specified voltage or current channels at zero input and stores the inverse result in the associated offset registers. This DC offset will be added to instantaneous measurements in subsequent conversions, removing the offset.

The gain register for the channel being calibrated should be set to 1.0 prior to performing DC offset calibration.

DC offset calibration is not required if the high-pass filter is enabled on that channel because the DC component will be removed by the high-pass filter.

7.1.1.2 AC Offset Calibration

The AC offset calibration applies only to the current channel. It measures the residual RMS values on the current channel at zero input and stores the squared

SETTLE

52 DS982F3

CS5490

0xFFFFFF

result in the AC offset register. This AC offset will be subtracted from RMS measurements in subsequent conversions, removing the AC offset on the current channel.

The AC offset register for the channel being calibrated should first be cleared prior to performing the calibration. The high-pass filter should be enabled if AC offset calibration is used. It is recommended that

SETTLE

be set to 2000ms before performing an AC offset calibration. Note that the AC offset register holds the square of the RMS value measured during calibration. Therefore, it can hold a maximum RMS noise of . This is the maximum RMS noise that AC offset correction can remove.

7.1.2 Gain Calibration

Prior to executing the gain calibration command, gain registers for any path to be calibrated (V should be set to ‘1.0,’ and T

SETTLE

should be set to 2000 ms. For gain calibration, a reference signal must be applied to the meter. During gain calibration, the voltage RMS result register (V and the current RMS result register (I

) is divided into ‘0.6,’

RMS

) is divided into

RMS

the Scale register. The quotient is put into the associated gain register. The gain calibration algorithm attempts to adjust the gain register (V that the voltage RMS result register (V and the current RMS result register (I

GAIN

RMS

Scale register.

Note that for the gain calibration, there are limitations on choosing the reference level and the Scale register value. Using a reference or a scale that is too large or too small can cause register overflow during calibration or later during normal operation. Either condition can set Status register bits IOR and VOR. The maximum value that the gain register can attain is ‘4.’ Using inappropriate reference levels or scale values may also cause the CS5490 to attempt to set the gain register higher than ‘4.’ Therefore, the gain calibration result will be invalid.

The Scale register is ‘0.6’ by default. The maximum voltage (U

Volts) and current (I

MAX

Amps) of the

MAX

meter should be used as the reference signal level if the

Scale register is ‘0.6.’ After gain calibration, ‘0.6’ of the V

RMS

) registers represents U

RMS

MAX

Amps) for the line voltage (load current); ‘0.36’ of the

AVG

, Q

, or S register represents U

AVG

Watts, Vars, or VAs for the active, reactive, or apparent power.

, I

GAIN

, I

) such

GAIN

) equals ‘0.6,’

) equals the

Volts (I

MAX×IMAX

MAX

If the calibration is performed with U Amps and I

CAL<IMAX

scaled down to 0.6 × I

, the Scale register needs to be

CAL/IMAX

before performing gain

Volts and I

MAX

calibration. After gain calibration, ‘0.6’ of the V register represents U

RMS

CAL/IMAX

MAXxICAL

of the P

Watts, Vars, or VAs.

AVG

MAX

, Q

Volts, 0.6 x I

CAL

, or S register represents

AVG

CAL/IMAX

Amps, and 0.36 x

7.1.3 Calibration Order

1) If the HPF option is enabled, then any DC component that may be present in the selected signal channel will be removed, and a DC offset calibration is not required. However, if the HPF option is disabled, the DC offset calibration should be performed.

When using high-pass filters, it is recommended that

the DC offset register for the corresponding channel

)

be set to 0. Before performing DC offset calibration, the DC offset register should be set to 0, and the corresponding gain register should be set to 1.

2) If there is an AC offset in the I

calculation, the AC

RMS

offset calibration should be performed on the current channel. Before performing AC offset calibration, the AC offset register should be set to 0.

3) Perform the gain calibration.

4) If an AC offset calibration was performed (step 2),

then the AC offset may need to be adjusted to compensate for the change in gain (step 3). This can be accomplished by restoring zero to the AC offset register and then performing an AC offset calibration. The adjustment could also be done by multiplying the AC offset register value that was calculated in step 2 by the gain calculated in step 3 and updating the AC offset register with the product.

7.2 Phase Compensation

A phase compensation mechanism is provided to adjust for meter-to-meter variation in signal path delays. Phase offset between a voltage channel and its corresponding current channel can be calculated by using the power factor (PF) register after a conversion.

1) Apply a reference voltage and current with a lagging

power factor to the meter. The reference current waveform should lag the voltage with a 60° phase shift.

2) Start continuous conversion.

3) Accumulate multiple readings of the PF register.

4) Calculate the average power factor, PF

5) Calculate phase offset = arccos (PF

avg

) - 60°.

CAL

RMS

of the

DS982F3 53

CS5490

ymxb+=

Force Temperature (

T Register Value

Y = m • x + b

OFF

-----

GAIN

6) If the phase offset is negative, then the delay should be added only to the current channel. Otherwise, add more delay to the voltage channel than to the current channel to compensate for a positive phase offset.

Once the phase offset is known, the CPCC and FPCC bits for that channel are calculated and programmed in the PC register.

CPCC bits are used if either

• The phase offset is more than 1 output word rate

(OWR) sample.

• More delay is needed on the voltage channel.

The compensation resolution is 0.008789° at 50Hz and

0.010547° at 60Hz at an OWR of 4000Hz.

7.3 Temperature Sensor Calibration

Temperature sensor calibration involves the adjustment of two parameters: temperature gain (T temperature offset (T must be set to 1.0 (0x 01 0000), and T

). Before calibration, T

OFF

to 0.0 (0x 00 0000).

) and

GAIN

must be set

7.3.1 Temperature Offset and Gain Calibration

To obtain the optimal temperature offset (T value and temperature (T

) register value, it is

GAIN

necessary to measure the temperature (T) register at a minimum of two points (T1 and T2) across the meter operating temperature range. The two temperature points must be far enough apart to yield reasonable accuracy, for example 25

°C and 85°C. Obtain a linear

fit of these points ( ), where the slope (m) and intercept (b) can be obtained.

OFF

) register

Figure 20. T Register vs. Force Temp

OFF

and T

are calculated using the equations

GAIN

below:

54 DS982F3

8. BASIC APPLICATION CIRCUITS

CS5490

LineN

VIN-

VIN+

IIN+

IIN-

Application

Processor

RESET

GND A

VDD A

+3.3V

0.1µF 0.1µF

+3.3V

VDD D

+3.3V

VREF -

VREF +

0.1µF

4.096 MHz

XIN

XOUT

MODE

5 x250K

LOAD

0.1 µF

10K

+3 .3V

27nF

½ R

BURDEN

½ R

BURDEN

27nF

Figure 21. Typical Connection Diagram (Single-phase, Two-wire, Power Meter)

The CS5490 is configured to measure power in a single-phase, two-wire single voltage and current system, as illustrated in Figure 21. In this diagram, a

CS5490

current transformer (CT) is used to sense the line load current, and a resistive voltage divider is used to sense the line voltage.

DS982F3 55

9. PACKAGE DIMENSIONS

16 SOIC (150 MIL BODY) PACKAGE DRAWING

CS5490

mm inch

Dimension MIN NOM MAX MIN NOM MAX

A - - - - 1.75 - - - - 0.069

A1 0.10 - - 0.25 0.004 - - 0.010

b 0.31 - - 0.51 0.012 - - 0.020

c 0.10 - - 0.25 0.004 - - 0.010 D 9.90 BSC 0.390 BSC E 6.00 BSC 0.236 BSC

E1 3.90 BSC 0.154 BSC

e 1.27 BSC 0.05 BSC

L 0.40 - - 1.27 0.016 - - 0.050 Θ 0° - - 8° 0° - - 8°

aaa 0.10 0.004 bbb 0.25 0.010 ddd 0.25 0.010

Notes:

1. Controlling dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5 M.

3. This drawing conforms to JEDEC outline MS-012, variation AC for standard 16 SOIC narrow body.

4. Recommended reflow profile is per JEDEC/IPC J-STD-020.

56 DS982F3

10. ORDERING INFORMATION

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, EXL Core, and the EXL Core logo design are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

Ordering Number Container Temperature Package

CS5490-ISZ Bulk

-40 to +85 °C 16-pin SOIC, Lead (Pb) Free

CS5490-ISZR Tape & Reel

11. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

Part Number Peak Reflow Temp MSL Rating* Max Floor Life

CS5490-ISZ

260 °C 3 7 Days

* MSL (Moisture Sensitivity Level) as specified by IPC/ JEDEC J-STD-020.

12. REVISION HISTORY

Revision Date Changes

PP1 APR 2012

F1 APR 2012

F2 JUN 2012 Updated ordering information.

F3 MAR 2013 Clarified context.

Preliminary release.

Edited for content and clarity.

CS5490

DS982F3 57

Cirrus Logic CS5490 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CS5490

Two Channel Energy Measurement IC

Features

Description

1. OVERVIEW

2. PIN DESCRIPTION

Clock Generator

Control Pins and Serial Data I/O

Analog Inputs/Outputs

Power Supply Connections

2.1 Analog Pins

2.1.1 Voltage Input

2.1.2 Current Input

Figure 1. Oscillator Connections

2.1.3 Voltage Reference

2.1.4 Crystal Oscillator

2.2 Digital Pins

2.2.1 Reset Input

2.2.2 Digital Output

2.2.3 UART Serial Interface

2.2.3.1 UART

Figure 2. UART Serial Frame Format

2.2.4 MODE Pin

Figure 3. Active Energy Load Performance

3. CHARACTERISTICS & SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

POWER MEASUREMENT CHARACTERISTICS

TYPICAL LOAD PERFORMANCE

Figure 4. Reactive Energy Load Performance

Figure 5. I RMS Load Performance

ANALOG CHARACTERISTICS

Analog Inputs (Current Channels)

Analog Inputs (Voltage Channels)

Temperature

Power Supplies

VOLTAGE REFERENCE

DIGITAL CHARACTERISTICS

Master Clock Characteristics

Filter Characteristics

Input/Output Characteristics

SWITCHING CHARACTERISTICS

Start-up

ABSOLUTE MAXIMUM RATINGS

Figure 6. Signal Flow for V, I, P, and Q Measurements

4. SIGNAL FLOW DESCRIPTION

4.1 Analog-to-Digital Converters

4.2 Decimation Filters

4.3 IIR Filter

4.4 Phase Compensation

4.5 DC Offset & Gain Correction

Figure 7. Low-rate Calculations

4.6 High-pass & Phase Matching Filters

4.7 Digital Integrators

4.8 Low-rate Calculations

4.8.1 Fixed Number of Samples Averaging

4.8.2 Line-cycle Synchronized Averaging

4.8.7 Peak Voltage & Current

4.8.3 RMS Current & Voltage

4.8.8 Power Factor

4.9 Average Active Power Offset

4.8.4 Active Power

4.8.5 Reactive Power

4.8.6 Apparent Power

4.10 Average Reactive Power Offset

5. FUNCTIONAL DESCRIPTION

5.1 Power-on Reset (POR)

Table 1. POR Thresholds

5.2 Power Saving Modes

5.3 Zero-crossing Detection

Figure 8. Power-on Reset Timing

Figure 9. Zero-crossing Level and Zero-crossing Output on DO

5.4 Line Frequency Measurement

5.5 Energy Pulse Generation

Figure 10. Energy Pulse Generation and Digital Output Control

5.5.1 Pulse Rate

Figure 11. Sag, Swell, & Overcurrent Detect

Figure 5. I

RMS

Load Performance