Cirrus Logic CS5484 User Manual

CS5484

VDDA

TX / SDO

RX / SDI

UART/SPI

Serial

Interface

Conf igurable

Digital

Outputs

RESET

Calculation

4th Order 

Modulat or

HPF

Option

DO1

DO2

HPF

Option

VREF+

VDDD

VREF-

Syst em

Clock

IIN2+

IIN2-

PGA

IIN1+

IIN1-

PGA

10x

CS5484

CS

SCLK

SSEL

DO3

VIN1+

VIN1-

10x

VIN2+

VIN2-

Digital

Filter

Digital

Filter

DO4

MODE

HPF

Option

Digital

Filter

HPF

Option

Digital

Filter

M
U
X

4th Order 

Modulat or

4th Order 

Modulat or

4th Order 

Modulat or

GNDA GNDD

Voltage

Reference

Temperat ure

Sensor

XIN XOUT

CPUCLK

Clock

Generator

Four Channel Energy Measurement IC

Features & Description

• Superior Analog Performance with Ultra-low Noise Level
and High SNR

• Energy Measurement Accuracy of 0.1% over 4000:1
Dynamic Range

• Current RMS Measurement Accuracy of 0.1% over 1000:1
Dynamic Range

• 4 Independent 24-bit, 4
for Voltage and Current Measurements

• 4 Configurable Digital Outputs for Energy Pulses,
Zero-crossing, or Energy Direction

• Supports Shunt Resistor, CT, and Rogowski Coil Current
Sensors

• On-chip Measurements/Calculations:

- Active, Reactive, and Apparent Power

- RMS Voltage and Current

- Power Factor and Line Frequency

- Instantaneous Voltage, Current, and Power

• Overcurrent, Voltage Sag, and Voltage Swell Detection

• Ultra-fast On-chip Digital Calibration

• Internal Register Protection via Checksum and Write
Protection

• UART/SPI™ Serial Interface

• On-chip Temperature Sensor

• On-chip Voltage Reference (25ppm/°C Typ.)

• Single 3.3V Power Supply

• Ultra-fine Phase Compensation

• Low Power Consumption: <13mW

• Power Supply Configurations

- GNDA = GNDD = 0V, VDDA = +3.3V

• 5mmx5mm 28-pin QFN Package

ORDERING INFORMATION

See Page 68.

th

-order, Delta-Sigma Modulators

Description

The CS5484 is a high-accuracy, four-channel, energy
measurement analog front end.

The CS5484 incorporates independent 4th order Delta-Sigma
analog-to-digital converters for every channel, reference
circuitry, and the proven EXL signal processing core to provide
active, reactive, and apparent energy measurement. In
addition, RMS and power factor calculations are available.
Calculations are output through a configurable energy pulse,
or direct UART/SPI™ serial access to on-chip registers.
Instantaneous current, voltage, and power measurements are
also available over the serial port. Multiple serial options are
offered to allow customer flexibility. The SPI provides higher
speed, and the 2-wire UART minimizes the cost of isolation
where required.

Four configurable digital outputs provide energy pulses,
zero-crossing, energy direction, and interrupt functions.
Interrupts can be generated for a variety of conditions
including voltage sag or swell, overcurrent, and more. On-chip
register integrity is assured via checksum and write protection.
The CS5484 is designed to interface to a variety of voltage and
current sensors including shunt resistors, current
transformers, and Rogowski coils.

On-chip functionality makes digital calibration simple and
ultra-fast, minimizing the time required at the end of the
customer production line. Performance across temperature is
ensured with an on-chip voltage reference with low drift. A
single 3.3V power supply is required, and power consumption
is low at <13mW. To minimize space requirements, the
CS5484 is offered in a low-cost, 5mm x5mm 28-pin QFN
package.

Cirrus Logic, Inc.

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2013

(All Rights Reserved)

MAR’13

DS981F3

CS5484

TABLE OF CONTENTS

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.1 Analog Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.1.1 Voltage Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.1.2 Current Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.1.3 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.1.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2.1 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2.2 CPU Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.3 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2.4 UART/SPI™ Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.5 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.2.6 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.2.7 MODE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4. Signal Flow Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.1 Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.2 Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.3 IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.4 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.5 DC Offset and Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.6 High-pass and Phase Matching Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.7 Digital Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.8 Low-rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.8.1 Fixed Number of Samples Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.8.2 Line-cycle Synchronized Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.8.3 RMS Current and Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.8.4 Active Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.8.5 Reactive Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.8.6 Apparent Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.8.7 Peak Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.8.8 Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.9 Average Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.10 Average Reactive Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.3 Zero-crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.4 Line Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.5 Energy Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.5.1 Pulse Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5.5.2 Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.6 Voltage Sag, Voltage Swell, and Overcurrent Detection . . . . . . . . . . . . . . . . . . . . .24

2 DS981F3

CS5484

5.7 Phase Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.8 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.9 Anti-creep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.10 Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.10.1 Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.10.2 Register Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6. Host Commands and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.1 Memory Access Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.1.1 Page Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.1.2 Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.1.3 Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.3 Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1.4 Serial Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2 Hardware Registers Summary (Page 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3 Software Registers Summary (Page 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.4 Software Registers Summary (Page 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.5 Software Registers Summary (Page 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.6 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.1 Calibration in General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.1.1 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.1.1.1 DC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.1.1.2 AC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.1.2 Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.1.3 Calibration Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.3 Temperature Sensor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

7.3.1 Temperature Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

11. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . 68

12. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

DS981F3 3

CS5484

LIST OF FIGURES

Figure 1. Oscillator Connections................................................................................................... 7

Figure 2. Multi-device UART Connections.................................................................................... 8

Figure 3. UART Serial Frame Format........................................................................................... 8

Figure 4. Active Energy Load Performance.................................................................................. 9

Figure 5. Reactive Energy Load Performance............................................................................ 10

Figure 6. IRMS Load Performance ............................................................................................. 10

Figure 7. SPI Data and Clock Timing ......................................................................................... 15

Figure 8. Multi-Device UART Timing .......................................................................................... 15

Figure 9. Signal Flow for V1, I1, P1, and Q1 Measurements ..................................................... 17

Figure 10. Signal Flow for V2, I2, P2, and Q2 Measurements ................................................... 17

Figure 11. Low-rate Calculations ................................................................................................18

Figure 12. Power-on Reset Timing ............................................................................................. 21

Figure 13. Zero-crossing Level and Zero-crossing Output on DOx ............................................ 22

Figure 14. Energy Pulse Generation and Digital Output Control ................................................ 23

Figure 15. Sag, Swell, and Overcurrent Detect .......................................................................... 24

Figure 16. Phase Sequence A, B, C for Rising Edge Transition ................................................ 25

Figure 17. Phase Sequence C, B, A for Rising Edge Transition ................................................ 26

Figure 18. Byte Sequence for Page Select................................................................................. 27

Figure 19. Byte Sequence for Register Read ............................................................................ 27

Figure 20. Byte Sequence for Register Write ............................................................................. 27

Figure 21. Byte Sequence for Instructions.................................................................................. 27

Figure 22. Byte Sequence for Checksum ................................................................................... 28

Figure 23. Calibration Data Flow ................................................................................................62

Figure 24. T Register vs. Force Temp ........................................................................................ 65

Figure 25. Typical Connection (Single-phase, 3-wire, 12S Electricity Meter)............................. 66

LIST OF TABLES

Table 1. POR Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 2. Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 3. Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4 DS981F3

CS5484

1. OVERVIEW

The CS5484 is a CMOS power measurement integrated circuit using four  analog-to-digital converters
to measure two line voltages and two currents. Optionally, voltage2 channel can be used for temperature
measurement. It calculates active, reactive, and apparent power as well as RMS voltage and current and
peak voltage and current. It handles other system-related functions, such as energy pulse generation,
voltage sag and swell, overcurrent and zero-crossing detection, and line frequency measurement.

The CS5484 is optimized to interface to current transformers, shunt resistors, or Rogowski coils for
current measurement and to resistive dividers or voltage transformers for voltage measurement. Two
full-scale ranges are provided on the current inputs to accommodate different types of current sensors.
The CS5484’s four differential inputs have a common-mode input range from analog ground (GNDA) to
the positive analog supply (VDDA).

An on-chip voltage reference (typically 2.4 volts) is generated and provided at analog output, VREF±.

Four digital outputs (DO1, DO2, DO3, and DO4) provide a variety of output signals, and depending on the
mode selected, provide energy pulses, zero-crossings, or other choices.

The CS5484 includes a UART/SPI™ serial host interface to an external microcontroller. The serial select
(SSEL) pin is used to configure the serial port to be a SPI or UART. SPI signals include serial data input
(SDI), serial data output (SDO), and serial clock (SCLK). UART signals include serial data input (RX) and
serial data output (TX). A chip select (CS
interface with the microcontroller.

) signal allows multiple CS5484s to share the same serial

DS981F3 5

2. PIN DESCRIPTIONS

98

7

6

5

4

3

2

1

10

11

12 13 14

15

16

17

18

19

20

21

222324

25

262728

Top-Down View

28-pin QFN Pack age

Thermal Pad

XOUT

VDDD

GNDD

CPUCLK

MODE

SSEL

CS

VIN1-

IIN2-

IIN2+

VREF-

VREF+

GNDA

VDDA

XIN

RESET

IIN1-

IIN1+

VIN2-

VIN2+

VIN1+

SCLK

RX/SDI

TX/SDO

DO4

DO3

DO2

DO1

Do Not Connect

CS5484

Digital Pins and Serial Data I/O

Digital Outputs 15,16,

17,18

Reset 2

Serial Data I/O 19,20

Serial Clock Input 21

Chip Select 22

Serial Mode Select 23

Operating Mode Select 24

DO1, DO2, DO3, DO4 — Configurable digital outputs for energy pulses, interrupt, energy

direction, and zero-crossings.

RESET — An active-low Schmitt-trigger input used to reset the chip.

TX/ SDO, RX/SDI — UART /SPI serial data output/input.

SCLK — Serial clock for the SPI.

CS — Chip select for the UART/SPI.

SSEL — Selects the type of serial interface, UART or SPI™. Logic level one - UART

selected. Logic level zero - SPI selected.

MODE — Connect to VDDA for proper operation.

Analog Inputs/ Outputs

Voltage Inputs 7,8,6,5

Current Inputs 4,3,10,9

Voltage Reference Input 12,11

VIN1+, VIN1-, VIN2+, VIN2- — Differential analog inputs for the voltage channels.

IIN1+, IIN1-, IIN2+, IIN2- — Differential analog inputs for the current channels.

VREF+, VREF- — The internal voltage reference. A 0.1µF bypass capacitor is required

between these two pins.

Power Supply Connections

Internal Digital Supply 27

Digital Ground 26

Positive Analog Supply 14

Analog Ground 13

Clock Generator

Crystal In
Crystal Out

CPU Clock Output 25

Thermal Pad

6 DS981F3

1,28

VDDD — Decoupling pin for the internal 1.8 V digital supply. A 0.1µF bypass capacitor is
required between this pin and GNDD.

GNDD — Digital ground.

VDDA — The positive 3.3V analog supply.

GNDA — Analog ground.

XIN, XOUT — Connect to an external quartz crystal. Alternatively, an external clock can be

supplied to the XIN pin to provide the system clock for the device.

CPUCLK — Output of on-chip oscillator which can drive one standard CMOS load.

No Electrical Connection.

-

2.1 Analog Pins

XIN XOUT

C1 = 22pF C2 = 22pF

Figure 1. Oscillator Connections

The CS5484 has two differential inputs (VIN1VIN2)
for voltage input and two differential inputsIIN1 IIN2)
for current1 and current2 inputs. The CS5484 also has
two voltage reference pins (VREF) between which a
bypass capacitor should be placed.

2.1.1 Voltage Inputs

The output of the line voltage resistive divider or
transformer is connected to the VIN1 or VIN2 input
pins of the CS5484. The voltage channel is equipped
with a 10x, fixed-gain amplifier. The full-scale signal
level that can be applied to the voltage channel is
±250mV. If the input signal is a sine wave, the maximum
RMS voltage is 250mVp /
approximately 70.7% of maximum peak voltage.

2.1.2 Current Inputs

The output of the current-sensing shunt resistor,
transformer, or Rogowski coil is connected to the
IIN1 or IIN2  input pins of the CS5484. To
accommodate different current-sensing elements, the
current channel incorporates a programmable gain
amplifier (PGA) with two selectable input gains, as
described in the Config0 register description (see
section 6.6.1 Configuration 0 (Config0) – Page 0,

Address 0 on page 35.) There is a 10x gain setting and

a 50x gain setting. The full-scale signal level for current
channels is ±50mV and ±250 mV for 50x and 10x gain
settings, respectively. If the input signal is a sine wave,
the maximum RMS voltage is 35.35mV

176.78mV

maximum peak voltage.

which is approximately 70.7% of

RMS,

2.1.3 Voltage Reference

The CS5484 generates a stable voltage reference of

2.4V between the VREF pins. The reference system

also requires a filter capacitor of at least 0.1µF between
the VREF pins.

The reference system is capable of providing a
reference for the CS5484 but has limited ability to drive
external circuitry. It is strongly recommended that
nothing other than the required filter capacitor be
connected to the VREF pins.

2.1.4 Crystal Oscillator

An external, 4.096 MHz quartz crystal can be connected
to the XIN and XOUT pins, as shown in Figure 1. To re­duce system cost, each pin is supplied with an on-chip
load capacitor.

2  176.78mV

RMS

, which is

or

RMS

CS5484

Alternatively, an external clock source can be
connected to the XIN pin.

2.2 Digital Pins

2.2.1 Reset Input

The active-low RESET pin, when asserted for longer
than 120µs, will halt all CS5484 operations and reset
internal hardware registers and states. When
de-asserted, an initialization sequence begins, setting
default register values. To prevent erroneous
noise-induced resets to the CS5484, an external pull-up
resistor and a decoupling capacitor are necessary on
the RESET

2.2.2 CPU Clock Output

A logic-level clock output (CPUCLK) is provided at the
crystal frequency to drive another CS5484 IC or
external microcontroller. Writing ‘1’ to bit CPUCLK_ON
of the Config0 register enables the CPU clock output.
After the CPU clock output is enabled, it can be disabled
only by a power-on reset (POR) or by writing ‘0’ to the
CPUCLK_ON bit. A hardware reset through pin/RESET
or a software reset instruction through the serial
interface will not disable the CPU clock output. Two
phase choices are available on the CPUCLK pin
through bit iCPUCLK of the Config0 register. Different
from the CPUCLK_ON bit, the iCPUCLK bit can be
cleared by a POR, a hardware reset, a software reset
instruction, or a register write.

2.2.3 Digital Outputs

The CS5484 provides four configurable digital outputs
(DO1-DO4). They can be configured to output energy
pulses, interrupt, zero-crossings, or energy directions.
Refer to section 6.6.2 Configuration 1 (Config1) – Page

0, Address 1 on page 36 for more details.

pin.

DS981F3 7

CS5484

UART

MASTER

SLAVE 0

SLAVE 1

SLAVE N

CS
RX
TX

CS
RX
TX

CS
RX
TX

CS0

CS1

CSN

RX

TX

0 1 2 7IDLE STOP3 4 5 6START

DATA

IDLE

2.2.4 UART/SPI™ Serial Interface

The CS5484 provides five pins—SSEL, RX/SDI,
TX/SDO, CS

, and SCLK—for communication between

a host microcontroller and the CS5484.

SSEL is an input that, when low, indicates to the
CS5484 to use the SPI port as the serial interface to
communicate with the host microcontroller. The SSEL
pin has an internal weak pull-up. When the SSEL pin is
left unconnected or pulled high externally, the UART
port is used as the serial interface.

2.2.5 SPI

The CS5484 provides a Serial Peripheral Interface
(SPI) that operates as a slave device in 4-wire mode
and supports multiple slaves on the SPI bus. The 4-wire
SPI includes CS

CS

is the chip select input for the CS5484 SPI port. A

, SCLK, SDI, and SDO signals.

high logic level de-asserts it, tri-stating the SDO pin and
clearing the SPI interface. A low logic level enables the
SPI port. Although the CS

pin may be tied low for
systems that do not require multiple SDO drivers, using
the CS

signal is strongly recommended to achieve more

reliable SPI communications.

SCLK is the serial clock input for the CS5484 SPI port.
Serial data changes as a result of the falling edge of
SCLK and is valid at the rising edge. The SCLK pin is a
Schmitt-trigger input.

SDI is the serial data input to the CS5484.

SDO is the serial data output from the CS5484.

The CS5484 SPI transmits and receives data MSB first.
Refer to Switching Characteristics on page 14 and

Figure 7 on page 15 for more detailed information about

SPI timing.

2.2.6 UART

The CS5484 device contains an asynchronous,
full-duplex UART. The UART may be used in either
standard 2-wire communication mode (RX/TX) for
connecting a single device or 3-wire communication
mode (RX/TX/
When connecting a single CS5484 device, CS
be held low to enable the UART. Multiple CS5484
devices can communicate to the same master UART in
the 3-wire mode by pulling a slave CS
data transmissions. Common RX and TX signals are
provided to all the slave devices, and each slave device

CS) for connecting multiple devices.

should

pin low during

requires a separate CS

signal for enabling
communication to that slave. The multi-device UART
mode connections are shown in Figure 2.

Figure 2. Multi-device UART Connections

The multi-device UART mode timing diagram provides
the timing requirements for the CS

control (see Figure

8. Multi-Device UART Timing on Page 15).

The CS5484 UART operates in 8-bit mode, which
transmits a total of 10 bits per byte. Data is transmitted
and received LSB first, with one start bit, eight data bits,
and one stop bit.

Figure 3. UART Serial Frame Format

The baud rate is defined in the SerialCtrl register. After
chip reset, the default baud rate is 600, if MCLK is

4.096MHz. The baud rate is based on the contents of
bits BR[15:0] in the SerialCtrl register and is calculated
as follows:

BR[15:0] = Baud Rate x (524288/MCLK)

or

Baud Rate = BR[15:0] /(524288 / MCLK)

The maximum baud rate is 512K if MCLK is 4.096 MHz.

2.2.7 MODE Pin

The MODE pin must be tied to VDDA for normal
operation. The MODE pin is used primarily for factory
test procedures.

8 DS981F3

CS5484

-1

-0.5

0

0.5

1

0 500 1000 1500 2000 2500 3000 3500 40 00 4500

Percent Error (%)

Current Dynamic Range (x : 1

)

Lagging PF = 0.5

Leading PF = 0.5

PF = 1

Figure 4. Active Energy Load Performance

3. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Positive Analog Power Supply VDDA 3.0 3.3 3.6 V
Specified Temperature Range T

POWER MEASUREMENT CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Active Energy

(Note 1 and 2) Current Channel Input Signal Dynamic Range 4000:1

Reactive Energy

(Note 1 and 2) Current Channel Input Signal Dynamic Range 4000:1

Apparent Power

(Note 1 and 3) Current Channel Input Signal Dynamic Range 1000:1

Current RMS

(Note 1, 3, and 4) Current Channel Input Signal Dynamic Range 1000:1

Voltage RMS

(Note 1 and 3) Voltage Channel Input Signal Dynamic Range 20:1

Power Factor All Gain Ranges

(Note 1 and 3) Current Channel Input Signal Dynamic Range 1000:1

Notes: 1. Specifications guaranteed by design and characterization.

2. Active energy is tested with power factor (PF) = 1.0. Reactive energy is tested with Sin(
system level using a single energy pulse. Where: 1) One energy pulse = 0.5Wh or 0.5 Varh; 2) VDDA = +3.3V, T
= 4.096MHz; 3) System is calibrated.

3. Calculated using register values; N

4. I

error calculated using register values. 1) VDDA = +3.3V; TA = 25°C; MCLK = 4.096MHz; 2) AC offset calibration applied.

RMS

≥4000.

All Gain Ranges

All Gain Ranges

All Gain Ranges

All Gain Ranges

A

P

Avg

Q

Avg

S-±0.1-%

I

RMS

V

RMS

PF - ±0.1 - %

-40 - +85 °C

-±0.1- %

-±0.1- %

-±0.1- %

-±0.1- %

) = 1.0. Energy error measured at

= 25°C, MCLK

A

TYPICAL LOAD PERFORMANCE

• Energy error measured at system level using single energy pulse; where one energy pulse = 0.5Wh or 0.5Varh

•I

error calculated using register values

RMS

• VDDA = +3.3V; T

= 25°C; MCLK = 4.096MHz

A

DS981F3 9

CS5484

-1

-0.5

0

0.5

1

0 500 1000 1500 2000 2500 3000 3500 4000 4500

Percent Error (%)

Current Dynamic Range (x : 1

)

Lagging sin() = 0.5

Leading sin() = 0.5

sin() = 1

Figure 5. Reactive Energy Load Performance

-1

-0.5

0

0.5

1

0 500 1000 15 00

Percent Error (%)

Current Dynamic range (x : 1)

IRMS Error

I

Error

Figure 6. I

RMS

Load Performance

10 DS981F3

RMS

ANALOG CHARACTERISTICS

CS5484

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and T

• VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V.

• MCLK = 4.096MHz.

= 25°C.

A

Parameter Symbol Min Typ Max Unit

Analog Inputs (Current Channels)

Common Mode Rejection

(DC, 50, 60Hz) CMRR 80 - - dB

Common Mode+Signal -0.25 - VDDA V

Differential Full-scale Input Range

[(IIN+) – (IIN-)] (Gain = 50)

(Gain = 10)

IIN

-

-

250

50

-

-

mV
mV

P

P

Total Harmonic Distortion (Gain = 50) THD 90 100 - dB

Signal-to-Noise Ratio (SNR)

Crosstalk from Voltage Inputs at Full Scale

Crosstalk from Current Input at Full Scale

(Gain = 10)

(Gain = 50)

(50, 60Hz) --115-dB

(50, 60Hz) --115-dB

SNR

-

-

80
80

-

-

dB
dB

Input Capacitance IC - 27 - pF
Effective Input Impedance EII 30 - - k

Offset Drift (Without the High-pass Filter) OD - 4.0 - µV/°C

Noise (Referred to Input)

(Gain = 10)
(Gain = 50)

N

I

-

-

15

3.5

-

µV
µV

RMS

RMS

-

Power Supply Rejection Ratio (60Hz)

(Note 7) (Gain = 10)

(Gain = 50)

PSRR 60

68

65
75

-

-

dB
dB

Analog Inputs (Voltage Channels)

Common Mode Rejection

(DC, 50, 60Hz) CMRR 80 - - dB

Common Mode+Signal -0.25 - VDDA V

Differential Full-scale Input Range

[(VIN+) – (VIN-)] VIN - 250 - mV

P

Total Harmonic Distortion THD 80 88 - dB

Signal-to-Noise Ratio (SNR) SNR - 73 - dB

Crosstalk from Current Inputs at Full Scale

(50, 60Hz) --115-dB

Input Capacitance IC - 2.0 - pF
Effective Input Impedance EII 2 - - M

Noise (Referred to Input) N

V

-40-µV

RMS

Offset Drift (Without the High-pass Filter) OD - 16.0 - µV/°C

Power Supply Rejection Ratio

(Note 7) (Gain = 10)

(60Hz)

PSRR 60 65 - dB

Temperature

Temperature Accuracy

(Note 6) T-±5-°C

DS981F3 11

Parameter Symbol Min Typ Max Unit

PSRR 20

150

V

eq

---------- -

log=

TC

VREF

VREF

MAX

VREF

MIN

–

VREF

AVG

------------------------------------------------------------





1

T

A

MAX TAMIN–

----------------------------------------------





1.0 10

6

=

Power Supplies

Power Supply Currents (Active State)

Power Consumption

(Note 5) Active State (VDDA = +3.3V)

Notes: 5. All outputs unloaded. All inputs CMOS level.

6. Temperature accuracy measured after calibration is performed.

7. Measurement method for PSRR: VDDA = +3.3V, a 150 mV (zero-to-peak) (60 Hz) sine wave is imposed onto the +3.3V DC
supply voltage at the VDDA pin. The “+” and “-” input pins of both input channels are shorted to GNDA. The CS5484 is then
commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The
(zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value
of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs in order to cause the same digital
sinusoidal output. This voltage is then defined as V

I

(VDDA = +3.3V) PSCA - 3.9 - mA

A+

Stand-by State

PSRR is (in dB):

eq

VOLTAGE REFERENCE

Parameter Symbol Min Typ Max Unit

PC -

CS5484

12.9

-

4.5

-

-

mW
mW

Reference

(Note 8)

Output Voltage VREF +2.3 +2.4 +2.5 V

Temperature Coefficient

Load Regulation

Notes: 8. It is strongly recommended that no connection other than the required filter capacitor be made to VREF±.

9. The voltage at VREF± is measured across the temperature range. From these measurements the following formula is used to
calculate the VREF temperature coefficient:

10. Specified at maximum recommended output of 1µA sourcing. VREF is a sensitive signal; the output of the VREF circuit has a
high output impedance so that the 0.1µF reference capacitor provides attenuation even to low-frequency noise, such as 50 Hz
noise on the VREF output. Therefore VREF intended for the CS5484 only and should not be connected to any external circuitry.
The output impedance is sufficiently high that standard digital multi-meters can significantly load this voltage. The accuracy of the
metrology IC cannot be guaranteed when a multimeter or any component other than the 0.1µF capacitor is attached to VREF. If
it is desired to measure VREF for any reason other than a very course indicator of VREF functionality, Cirrus recommends a very
high input impedance multimeter such as the Keithley Model 2000 Digital Multimeter be used. Cirrus cannot guarantee the
accuracy of the metrology with this meter connected to VREF.

(Note 9) TC

(Note 10) V

VREF

R

-25-ppm/°C

-30-mV

12 DS981F3

CS5484

DIGITAL CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and T

• VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0 V.

• MCLK = 4.096MHz.

Parameter Symbol Min Typ Max Unit

Master Clock Characteristics

XIN Clock Frequency

Internal Gate Oscillator MCLK 2.5 4.096 5 MHz

Filter Characteristics

Phase Compensation Range

(60Hz, OWR = 4000Hz) -10.79 - +10.79 °

Input Sampling Rate - MCLK/8 - Hz
Digital Filter Output Word Rate
High-pass Filter Corner Frequency

(Both channels) OWR - MCLK/1024 - Hz

-3dB -2.0-Hz

Input/Output Characteristics

High-level Input Voltage (All Pins) V

Low-level Input Voltage (All Pins) V

High-level Output Voltage

(Note 12) All Other Outputs, I

Low-level Output Voltage

(Note 12) All Other Outputs, I

DO1-DO4, I

DO1-DO4, I

=+10mA

out

=+5mA

out

=-12mA

out

out

=-5mA

V

V

Input Leakage Current I

3-state Leakage Current I

Digital Output Pin Capacitance C

OZ

0.6(VDDA) - - V

IH

IL

OH

OL

in

--0.6V

VDDA-0.3
VDDA-0.3

-

-

-±1±10µA

--±10µA

out

-5-pF

= 25°C.

A

-

-

-

-

-

-

0.5

0.5

V
V

V
V

Notes: 11. All measurements performed under static conditions.

12. XOUT pin used for crystal only. Typical drive current< 1mA.

DS981F3 13

CS5484

SWITCHING CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and T

• VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V.

• Logic Levels: Logic 0 = 0 V, Logic 1 = VDDA.

Parameter Symbol Min Typ Max Unit

Rise Times

(Note 13) Any Digital Output Except DO1-DO4

Fall Times

(Note 13) Any Digital Output Except DO1-DO4

DO1-DO4

DO1-DO4

t

rise

t

fall

Start-up

Oscillator Start-up Time

XTAL = 4.096MHz (Note 14) t

ost

SPI Timing

Serial Clock Frequency (Note 15) SCLK - - 2 MHz

Serial Clock

Enable to SCLK Falling t

CS

Data Set-up Time prior to SCLK Rising t

Data Hold Time After SCLK Rising t

SCLK Rising Prior to CS

Disable t

SCLK Falling to New Data Bit t

Rising to SDO Hi-Z t

CS

Pulse Width High

Pulse Width Low

t

1

t

2

3

4

5

6

7

8

200
200

50 - - ns

50 - - ns

100 - - ns

UART Timing

Enable to RX START bit t

CS

STOP bit to CS

Disable to TX IDLE Hold Time t

CS

Notes: 13. Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF.

14. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.

15. The maximum SCLK is 2MHz during a byte transaction. The minimum 1 µs idle time is required on the SCLK between two

Disable

consecutive bytes.

9

t

10

11

= 25°C.

A

-

-

-

-

50

50

-

-

1.0

-

1.0

-

µs
ns

µs
ns

-60-ms

-

-

-

-

ns
ns

1--µs

--150ns

--250ns

5--ns

1--µs

--250ns

14 DS981F3

CS5484

SDO

SDI

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

CS

SCLK

MSB

MSB

MSB-1

MSB-1

INTERMED IAT E B ITS

INTERMED IAT E B ITS

LSB

LSB

Figure 7. SPI Data and Clock Timing

TX

RX

t

9

t

11

CS

START LSB

LSB

DATA MSB STOP

START DATA MS B

STOP

STOP

IDLE

OPTIONAL OVERLAP INSTRUCTION *

IDL E

t

10

IDLE

* Reading registers during the optional overlap instruction requires
the start to occur during the last byte transmitted by the part

Figure 8. Multi-Device UART Timing

DS981F3 15

CS5484

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Typ Max Unit

DC Power Supplies

Input Current

Input Current for Power Supplies - - - ±50 -

Output Current

Power Dissipation

Input Voltage

Junction-to-Ambient Thermal Impedance

Ambient Operating Temperature T

Storage Temperature T

Notes: 16. VDDA and GNDA must satisfy [(VDDA) – (GNDA)]  + 4.0V.

17. Applies to all pins, including continuous overvoltage conditions at the analog input pins.

18. Transient current of up to 100mA will not cause SCR latch-up.

19. Applies to all pins, except VREF±

20. Total power dissipation, including all input currents and output currents.

21. Applies to all pins.

.

(Note 16) VDDA -0.3 - +4.0 V

(Notes 17 and 18)

(Note 19)

(Note 20) PD -- 500mW

(Note 21) V

2 Layer Board
4 Layer Board

I

I

OUT



IN

IN

JA

A

stg

-- ±10mA

-- 100mA

- 0.3 - (VDDA) + 0.3 V

-

-

53
43

-

-

-40 - 85 °C

-65 - 150 °C

°C/W
°C/W

WARNING:

Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

16 DS981F3

4. SIGNAL FLOW DESCRIPTION

MUX

VIN1±

SINC

3

+

X

IIN1±

SINC

3

+

X

PGA

+

+



HPF

4th Order

ΔΣ

Modulator

4th Order

ΔΣ

Modulator

x10

X

DELAY

CTRL

X

X

X

2

MUX

X

PMF

HPF

PMF

IIR

IIR

Phase

Shift

Config 2

X

Eps ilon

DELAY

CTRL

INT



Registers

Q1

V1

P1

I1

SYS

GAIN

... ...

I1FLT[1:0]V1FLT[ 1:0]

V1

DCOFF

I1

DCOFF

I1

GAIN

V1

GAIN

PC

... ...

FPCC1[8:0]CPCC1[1:0]

...

Figure 9. Signal Flow for V1, I1, P1, and Q1 Measurements

MUX

VIN2±

SINC

3

+

X

IIN2±

SINC

3

+

X

PGA

+

+

 HPF

4th Order

ΔΣ

Modulator

4th Order

ΔΣ

Modulator

x10

X

DELAY

CTRL

X

X

X

2

MUX

X

PMF

HPF

PMF

IIR

IIR

Phase

Shift

X

Epsilon

DELAY

CTRL

INT



Regi ster s

Q2

V2

P2

I2

SYS

GAIN

V2

DCOFF

I2

DCOFF

I2

GAIN

V2

GAIN

PC

Config 2

... ...

I2FLT[1:0]

V2FLT[ 1:0]

... ...

FPCC2[8:0]CPCC2[1:0]

...

Figure 10. Signal Flow for V2, I2, P2, and Q2 Measurements

The signal flow for voltage measurement, current
measurement, and the other calculations is shown in

Figures 9, 10, and 11.

The signal flow consists of two current channels and two
voltage channels. The current and voltage channels
have differential input pins.

4.1 Analog-to-Digital Converters

All four input channels use fourth-order delta-sigma
modulators to convert the analog inputs to single-bit
digital data streams. The converters sample at a rate of
MCLK/8. This high sampling provides a wide dynamic
range and simplifies anti-alias filter design.

4.2 Decimation Filters

The single-bit modulator output data is widened to 24
bits and down sampled to MCLK/1024 with low-pass
decimation filters. These decimation filters are

CS5484

third-order Sinc filters. The filter outputs pass through
an IIR "anti-sinc" filter.

4.3 IIR Filters

The IIR filters are used to compensate for the amplitude
roll-off of the decimation filters. The droop-correction
filter flattens the magnitude response of the channel out
to the Nyquist frequency, thus allowing for accurate
measurements of up to 2 kHz (MCLK = 4.096 MHz). By
default, the IIR filters are enabled. The IIR filters can be
bypassed by setting the IIR_OFF bit in the Config2
register.

4.4 Phase Compensation

Phase compensation changes the phase of voltage
relative to current by adding a delay in the decimation
filters.

The amount of phase shift is set by the PC register
bits CPCCx[1:0] and FPCCx[8:0] for current channels.
Bits CPCCx[1:0] set the delay for the voltage channels.

DS981F3 17

CS5484



N

÷

N



N

÷

N



N

÷

N





N

÷

N





Regi ster s

MUX

...

...

APCM

Config 2

V1(V2)

I1 (I2)

P1 (P2)

Q1 (Q 2)

I1

ACOFF

(I2

ACOFF

)

S1 (S2)





PF1 (PF2)

X

I1

RMS

(I2

RMS

)

V1

RMS

(V2

RMS

)

Q1

AVG

(Q2

AVG

)

P1

AVG

(P2

AVG

)

-

+

Q1

OFF

(Q2

OFF

)



+

+

P1

OFF

(P2

OFF

)



+

+

X

X

+

+

Inverse

Figure 11. Low-rate Calculations

Fine phase compensation control bits, FPCCx[8:0],
provide up to 1/OWR delay in the current channel.
Coarse phase compensation control bits, CPCCx[1:0],
provide an additional 1/OWR delay in the current
channels or up to 2/OWR delay in the voltage channel.
Negative delay in the voltage channel can be
implemented by setting longer delay in the current
channel than the voltage channel. For a OWR of
4000Hz, the delay range is ±500 µs, a phase shift of
±8.99° at 50Hz and ±10.79° at 60 Hz. The step size is

0.008789° at 50 Hz and 0.010547° at 60Hz.

4.5 DC Offset and Gain Correction

The system and CS5484 inherently have component
tolerances, gain, and offset errors, which can be
removed using the gain and offset registers. Each
measurement channel has its own set of gain and offset
registers. For every instantaneous voltage and current
sample, the offset and gain values are used to correct
DC offset and gain errors in the channel (see section 7.

System Calibration on page 62 for more details).

4.6 High-pass and Phase Matching Filters

Optional high-pass filters (HPF in Figures 9 and 10)
remove any DC component from the selected signal
paths. Each power calculation contains a current and
voltage channel. If an HPF is enabled in only one
channel, a phase-matching filter (PMF) should be
applied to the other channel to match the phase
response of the HPF. For AC power measurement,
high-pass filters should be enabled on the voltage and
current channels. For information about how to enable
and disable the HPF or PMF on each channel, refer to
section 6.6.3 Configuration 2 (Config2) – Page 16,

Address 0 on page 38.

4.7 Digital Integrators

Optional digital integrators (INT in Figures 9 and 10) are
implemented on both current channels (I1, I2) to
compensate for the 90º phase shift and 20dB/decade
gain generated by the Rogowski coil current sensor.
When a Rogowski coil is used as the current sensor, the
integrator (INT) should be enabled on that current
channel. For information about how to enable and
disable the INT on each current channel, refer to section

6.6.3 Configuration 2 (Config2) – Page 16, Address 0 on

page 38.

4.8 Low-rate Calculations

All the RMS and power results come from low-rate cal­culations by averaging the output word rate (OWR) in­stantaneous values over N samples, where N is the
value stored in the SampleCount register. The low-rate
interval or averaging period is N divided by OWR
(4000Hz if MCLK = 4.096MHz).

The CS5484 provides two averaging modes for low-rate
calculations: Fixed Number of Samples Averaging
mode and Line-cycle Synchronized Averaging mode.
By default, the CS5484 averages with the Fixed Num­ber of Samples Averaging mode. By setting the
AVG_MODE bit in the Config2 register, the CS5484 will
use the Line-cycle Synchronized Averaging mode.

4.8.1 Fixed Number of Samples Averaging

N is the preset value in the SampleCount register and
should not be set less than 100. By default, the
SampleCount is 4000. With MCLK = 4.096MHz, the
averaging period is fixed at N/ 4000 = 1 second,
regardless of the line frequency.

18 DS981F3

CS5484

RMS

I

n

2

n0=

N1–



N

------------------- -

= V

RMS

V

n

2

n0=

N1–



N

----------------------

=

[Eq: 1]

SV

RMSIRMS

=

[Eq: 2]

SQ

AVG

2

P

AVG

2

+=

[Eq: 3]

PF

P

ACTIVE

S

----------------------

=

[Eq: 4]

4.8.2 Line-cycle Synchronized Averaging

When operating in Line-cycle Synchronized Averaging
mode, and when line frequency measurement is
enabled (see section 5.4 Line Frequency Measurement
on page 22), the CS5484 uses the voltage (V) channel
zero crossings and measured line frequency to
automatically adjust N such that the averaging period
will be equal to the number of half line-cycles in the
CycleCount register. For example, if the line frequency
is 51Hz, and the CycleCount register is set to 100, N will
be 4000

(100/2)/51 = 3921 during continuous

conversion. N is self-adjusted according to the line
frequency, therefore the averaging period is always
close to the whole number of half line-cycles, and the
low-rate calculation results will minimize ripple and
maximize resolution, especially when the line frequency
varies. Before starting a low-rate conversion in the
Line-cycle Synchronized Averaging mode, the
SampleCount register should not be changed from its
default value of 4000, and bit AFC of the Config2
register must be set. During continuous conversion, the
host processor should not change the SampleCount
register.

4.8.3 RMS Current and Voltage

The root mean square (RMS in Figure 11) calculations
are performed on N instantaneous current and voltage
samples using Equation 1:

4.8.5 Reactive Power

Instantaneous reactive power (Q1, Q2) are sample rate
results obtained by multiplying instantaneous current
(I1, I2) by instantaneous quadrature voltage (V1Q,
V2Q), which are created by phase shifting
instantaneous voltage (V1, V2) 90 degrees using
first-order integrators (see Figures 9 and 10). The gain
of these integrators is inversely related to line
frequency, so their gain is corrected by the Epsilon
register, which is based on line frequency. Reactive
power (Q1

AVG

, Q2

) is generated by integrating the

AVG

instantaneous quadrature power over N samples.

4.8.6 Apparent Power

By default, the CS5484 calculates the apparent power
(S1, S2) as the product of RMS voltage and current, as
shown in Equation 2:

The CS5484 also provides an alternate apparent power
calculation method. The alternate apparent power
method uses real power (P1
power (Q1

AVG

, Q2

) to calculate apparent power.

AVG

See Equation 3:

The APCM bit in the Config2 register controls which
method is used for apparent power calculation.

AVG

, P2

) and reactive

AVG

4.8.7 Peak Voltage and Current

Peak current (I1
(V1

PEAK, V2PEAK

recorded in the corresponding channel peak register

4.8.4 Active Power

The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (P1, P2)
(see Figures 9 and 10). The product is then averaged
over N samples to compute active power (P1AVG,
P2AVG).

DS981F3 19

documented in the register map. This peak value is up­dated every N samples.

4.8.8 Power Factor

Power factor (PF1, PF2) is active power divided by ap­parent power. The sign of the power factor is deter­mined by the active power. See Equation 4:

PEAK

, I2

) and peak voltage

PEAK

) are calculated over N samples and

CS5484

4.9 Average Active Power Offset

The average active power offset registers, P1
(P2

), can be used to offset erroneous power sources

OFF

resident in the system not originating from the power
line. Residual power offsets are usually caused by
crosstalk into current channels from voltage channels,
or from ripple on the meter’s or chip’s power supply, or
from inductance from a nearby transformer.

These offsets can be either positive or negative,
indicating crosstalk coupling either in phase or out of
phase with the applied voltage input. The power offset
registers can compensate for either condition.

To use this feature, measure the average power at no
load. Take the measured result (from the P1
(P2

) register), invert (negate) the value, and write it

AVG

to the associated average active power offset register,

P1

OFF

(P2

OFF

).

OFF

AVG

4.10 Average Reactive Power Offset

The average reactive power offset registers, Q1
(Q2

), can be used to offset erroneous power

OFF

sources resident in the system not originating from the
power line. Residual reactive power offsets are usually
caused by crosstalk into current channels from voltage
channels, or from ripple on the meter’s or chip’s power
supply, or from inductance from a nearby transformer.

These offsets can be either positive or negative,
depending on the phase angle between the crosstalk
coupling and the applied voltage. The reactive power
offset registers can compensate for either condition. To
use this feature, measure the average reactive power at
no load. Take the measured result from the

Q1

AVG

(Q2

) register, invert (negate) the value and

AVG

write it to the associated reactive power offset register,

Q1

OFF

(Q2

OFF

).

OFF

20 DS981F3

5. FUNCTIONAL DESCRIPTION

VDDA

POR_Rough_VDDA

POR_ Fine _VDDA

VDDD

POR_Rough_VDDD

POR_Fine_VDDD

POR_ Fine _VDDA

POR_Fine_VDDD

Master Reset

130ms

V

th1

V

th2

V

th5

V

th6

V

th3

V

th4

V

th7

V

th8

Figure 12. Power-on Reset Timing

CS5484

5.1 Power-on Reset

The CS5484 has an internal power supply supervisor
circuit that monitors the VDDA and VDDD power
supplies and provides the master reset to the chip. If
any of these voltages are in the reset range, the master
reset is triggered.

The CS5484 has dedicated power-on reset (POR)
circuits for the analog supply and digital supply. During
power-up, both supplies have to be above the rising
threshold for the master reset to be de-asserted.

Each POR is divided into two blocks: rough and fine.
Rough POR triggers the fine POR. Rough POR
depends only on the supply voltage. The trip point for
the fine POR is dependent on bandgap voltage for
precise control. The POR circuit also acts as a
brownout detect. The fine POR detects supply drops
and asserts the master reset. The rough and fine PORs
have hysteresis in their rise and fall thresholds, which
prevents the reset signal from chattering.

Figure 12 shows the POR outputs for each of the power

supplies. The POR_Fine_VDDA and POR_Fine_VDDD
signals are AND-ed to form the actual power-on reset
signal to the digital circuity. The digital circuitry, in turn,
holds the master reset signal for 130ms and then
de-asserts the master reset.

Table 1. POR Thresholds

Typ i cal P O R

Threshold

Rough

VDDA

Fine

Rough

VDDD

Fine

Rising Falling

V

=2.34V V

th1

=2.77V V

V

th2

V

=1.20V V

th3

=1.51V V

V

th4

th6

th5

th8

th7

=2.06V

=2.59V

=1.06V

=1.42V

5.2 Power Saving Modes

Power Saving modes for the CS5484 are accessed
through the Host Commands (see section 6.1 Host

Commands on page 27).

• Standby: Powers down all the ADCs, rough buffer,
and the temperature sensor. Standby mode disables
the system time calculations. Use the wake-up
command to come out of standby mode.

• Wake-up: Clears the ADC power-down bits and
starts the system time calculations.

After any of these commands are completed, the DRDY
bit is set in the Status0 register.

5.3 Zero-crossing Detection

Zero-crossing detection logic is implemented in the
CS5484. One current and one voltage channel can be
selected for zero-crossing detection. The IZX_CH and
VZX_CH control bits in the Config0 register are used to
select the zero-crossing channel. A low-pass filter can
be enabled by setting the ZX_LPF bit in register
Config2. The low-pass filter has a cut-off frequency of
80Hz. It is used to eliminate any harmonics and help the
zero-crossing detection on the 50 Hz or 60Hz
fundamental component. The zero-crossing level
registers are used to set the minimum threshold over
which the channel peak must exceed in order for the
zero-crossing detection logic to function. There are two
separate zero-crossing level registers: VZX
threshold for the voltage channels, and IZX
threshold for the current channels.

LEVEL

LEVEL

is the
is the

DS981F3 21