CIRRUS LOGIC CS5461A Service Manual

CS5461A

Single Phase, Bi-directional Power/Energy IC

Features

• Energy Data Linearity: ±0.1% of Reading over
1000:1 Dynamic Range

• On-chip Functions:

- Instantaneous Voltage, Current, and Power

- I

and V

RMS

- Energy-to-pulse Conversion for Mechanical
Counter/Stepper Motor Drive

- System Calibrations and Phase Compensation

- Temperature Sensor

- Voltage Sag Detect

• Meets Accuracy Spec for IEC, ANSI, & JIS.

• Low Power Consumption

• Current Input Optimized for Sense Resistor.

• GND-referenced Signals with Single Supply

• On-chip 2.5 V Reference (25 ppm/°C typ)

• Power Supply Monitor

• Simple Three-wire Digital Serial Interface

• “Auto-boot” Mode from Serial E

• Power Supply Configurations:

VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V

, Apparent and Active (Real) Power

RMS

2

PROM.

Description

The CS5461A is an integrated power measure­ment device which combines two ∆Σ
analog-to-digital converters, power calculation
engine, energy-to-frequency converter, and a
serial interface on a single chip. It is designed to
accurately measure instantaneous current and
voltage, and calculate V
neous power, apparent power, and active power
for single-phase, 2- or 3-wire power metering
applications.

The CS5461A is optimized to interface to shunt
resistors or current transformers for current mea­surement, and to resistive dividers or potential
transformers for voltage measurement.

The CS5461A features a bi-directional serial in­terface for communication with a processor, and
a programmable energy-to-pulse output func­tion. Additional features include on-chip
functionality to facilitate system-level calibration,
temperature sensor, voltage sag detection, and
phase compensation.

ORDERING INFORMATION:

See Page 41.

RMS

, I

, instanta-

RMS

VREFOUT

http://www.cirrus.com

IIN+

IIN-

VREFIN

VIN+

VIN-

VA+ VD+

PGA

x1

x10

Voltage

Reference

AGND

4th Order ∆Σ

Modulator

2nd Order ∆Σ

Modulator

Power

Monitor

PFMON

Copyright © Cirrus Logic, Inc. 2005

RESET

Digital

Filter

Temperature

Sensor

Digital

Filter

System

Clock

(All Rights Reserved)

HPF

Option

HPF

Option

Clock

/K

Generator

XIN XOUT CPUCLK DGND

Power

Calculation

Engine

Calibration

Serial

Interface

E-to-F

MODE

CS

SDI

SDO

SCLK

INT

E1
E2
E3

AUG ‘05

DS661F1

CS5461A

TABLE OF CONTENTS

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 Linearity Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.1 Voltage Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.2 Current Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4 Energy Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4.1 Normal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4.2 Alternate Pulse Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.4.3 Mechanical Counter Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.4.4 Stepper Motor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.4.5 Pulse Output E3

5.4.6 Anti-creep for the Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.4.7 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5 Voltage Sag-detect Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.6 On-chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.7 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.8 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.9 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.10 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.11 Event Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.11.1 Typical Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.12 Serial Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.12.1 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.13 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 DS661F1

CS5461A

6. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.2 Current and Voltage DC Offset Register ( I

6.3 Current and Voltage Gain Register ( Ign ,Vgn ) . . . . . . . . . . . . . . . . . . . . . . 26

6.4 Cycle Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.5 PulseRateE

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1,2

6.6 Instantaneous Current, Voltage and Power Registers ( I , V , P ) . . . . . . . . 27

6.7 Active (Real) Power Registers ( P

6.8 I

6.9 Power Offset Register ( P

RMS

and V

Registers ( I

RMS

, V

RMS

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

off

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Active

) . . . . . . . . . . . . . . . . . . . . . . . . . . 27

RMS

6.10 Status Register and Mask Register ( Status , Mask ) . . . . . . . . . . . . . . . . 28

6.11 Current and Voltage AC Offset Register ( V

6.12 PulseRateE

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3

6.13 Temperature Register ( T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.14 System Gain Register ( SYS

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Gain

6.15 Pulsewidth Register ( PW ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.16 Voltage Sag Duration Register ( VSAG

6.17 Voltage Sag Level Register ( VSAG

Duration

) . . . . . . . . . . . . . . . . . . . . . . . . 30

Level

6.18 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.19 Temperature Gain Register ( T

6.20 Temperature Offset Register ( T

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Gain

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

off

6.21 Apparent Power Register ( S ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DCoff

ACoff

,V

) . . . . . . . . . . . . . . 26

DCoff

, I

) . . . . . . . . . . . . . 29

ACoff

) . . . . . . . . . . . . . . . . . . . . 30

7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 Channel Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1.1 Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1.1.1 Duration of Calibration Sequence . . . . . . . . . . . . . . . . . . . . . 33

7.1.2 Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1.2.1 DC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . 33

7.1.2.2 AC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . 34

7.1.3 Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1.3.1 AC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . 34

7.1.3.2 DC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . 35

7.1.4 Order of Calibration Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.3 Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2

8. Auto-boot Mode Using E

PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.1 Auto-Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.2 Auto-Boot Data for E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.3 Suggested E2PROM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . 41

13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DS661F1 3

CS5461A

LIST OF FIGURES

Figure 1. CS5461A Read and Write Timing Diagrams ............................................................... 11

Figure 2. Data Flow..................................................................................................................... 13

Figure 3. Normal Format on pulse outputs

Figure 4. Alternate Pulse Format on

Figure 5. Mechanical Counter Format on

Figure 6. Stepper Motor Format on

Figure 7. Voltage Sag Detect...................................................................................................... 19

Figure 8. Oscillator Connection................................................................................................... 20

Figure 9. Calibration Data Flow .................................................................................................. 33

Figure 10. System Calibration of Offset. ..................................................................................... 33

Figure 11. System Calibration of Gain ........................................................................................ 34

Figure 12. Example of AC Gain Calibration ................................................................................ 34

Figure 13. Another Example of AC Gain Calibration .................................................................. 34

Figure 14. Typical Interface of E

Figure 15. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line)37

Figure 16. Typical Connection Diagram (Single-phase, 2-wire – Isolated from Power Line)...... 38

Figure 17. Typical Connection Diagram (Single-phase, 3-wire).................................................. 38

Figure 18. Typical Connection Diagram (Single-phase, 3-wire – No Neutral Available)............. 39

E1 and E2............................................................................ 18

2

PROM to CS5461A ................................................................ 36

E1 and E2 ................................................................ 16

E1 and E2 .......................................................................... 17

E1 and E2 .................................................................. 17

LIST OF TABLES

Table 1. Current Channel PGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. E1

Table 3. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 DS661F1

and E2 Pulse Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CS5461A

1. OVERVIEW

The CS5461A is a CMOS monolithic power measurement device with a computation engine and an en­ergy-to-frequency pulse output. The CS5461A combines a programmable-gain amplifier, two ∆Σ ana­log-to-digital converters (ADCs), system calibration and a computation engine on a single chip.

The CS5461A is designed for power measurement applications and is optimized to interface to a cur­rent-sense resistor or transformer for current measurement, and to a resistive divider or potential trans­former for voltage measurement. The voltage and current channels provide programmable gains to
accommodate various input levels from a wide variety of sensing elements. With single +5 V supply on
VA+/AGND, both of the CS5461A’s input channels can accommodate common mode as well as signal
levels between (AGND - 0.25 V) and VA+.

Additionally, the CS5461A is equipped with a computation engine that calculates I
power and active (real) power. To facilitate communication to a microprocessor, the CS5461A includes a
simple three-wire serial interface which is SPI™ and Microwire™ compatible. The CS5461A provides
three outputs for energy registration. E1
stepper motor, or interface to a microprocessor. The pulse output E3
ibration.

and E2 are designed to directly drive a mechanical counter or

is designed to assist with meter cal-

RMS

, V

, apparent

RMS

DS661F1 5

2. PIN DESCRIPTION

CS5461A

Clock Generator

Crystal Out

1,24

Crystal In

CPU Clock Output 2

Control Pins and Serial Data I/O

Serial Clock Input 5

Serial Data Output 6

Chip Select 7

Mode Select 8

High Frequency Energy

18

Output

Reset 19

Interrupt 20

Energy Output 21,22

Serial Data Input 23

Analog Inputs/Outputs

Differential Voltage Inputs 9,10

Differential Current Inputs 15,16

Voltage Reference Output 11

Voltage Reference Input 12

Power Supply Connections

Positive Digital Supply 3

Digital Ground 4

Positive Analog Supply 14

Analog Ground 13

Power Fail Monitor

17

XOUT 1Crystal Out

CPUCLK 2CPU Clock Output

VD+ 3Positive Digital Supply

DGND 4Digital Ground

SCLK 5Serial Clock

SDO 6Serial Data Ouput

CS 7Chip Select

MODE 8Mode Select

VIN+ 9Differential Voltage Input

VIN- 10Differential Voltage Input

VREFOUT 11Voltage Reference Output

VREFIN 12Voltage Reference Input

XOUT, XIN - The output and input of an inverting amplifier. Oscillation occurs when connected to

a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to
the XIN pin to provide the system clock for the device.

CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.

SCLK - A Schmitt Trigger input pin. Clocks data from the SDI pin into the receive buffer and out of

the transmit buffer onto the SDO pin when CS

SDO -Serial port data output pin.SDO is forced into a high impedance state when CS is high.

CS - Low, activates the serial port interface.

MODE - High, enables the “auto-boot” mode. The mode pin is pulled low by an internal resistor.

E3 - Active low pulses with an output frequency proportional to the active power. Used to assist in

system calibration.

RESET - A Schmitt Trigger input pin. Low activates Reset, all internal registers (some of which
drive output pins) are set to their default states.

INT - Low, indicates that an enabled event has occurred.

E1, E2 - Active low pulses with an output frequency proportional to the active power. Indicates if

the measured energy is negative.

SDI - Serial port data input pin. Data will be input at a rate determined by SCLK.

VIN+, VIN- - Differential analog input pins for the voltage channel.

IIN+, IIN- - Differential analog input pins for the current channel.

VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magni-

tude of 2.5 V and is referenced to the AGND pin on the converter.

VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.

VD+ - The positive digital supply.

DGND - Digital Ground.

VA+ - The positive analog supply.

AGND - Analog ground.

PFMON - The power fail monitor pin monitors the analog supply. If PFMON’s voltage threshold is

not met, a Low-Supply Detect (LSD) bit is set in the status register.

XIN24 Crystal In
SDI23 Serial Data Input

22

E2

Energy Output 2

E121 Energy Output 1
INT20 Interrupt
RESET19 Reset
E318 High Frequency Energy Output
PFMON17 Power Fail Monitor
IIN+16 Differential Current Input
IIN-15 Differential Current Input
VA+14 Positive Analog Supply
AGND13 Analog Ground

is low.

6 DS661F1

CS5461A

3. CHARACTERISTICS & SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Positive Digital Power Supply VD+ 3.135 5.0 5.25 V
Positive Analog Power Supply VA+ 4.75 5.0 5.25 V
Voltage Reference VREFIN - 2.5 - V
Specified Temperature Range T

A

ANALOG CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.

• MCLK = 4.096 MHz.

Parameter Symbol Min Typ Max Unit

Linearity Performance

Active Power Accuracy All Gain Ranges
(Note 1) Input Range 0.1% - 100%

Current RMS Accuracy All Gain Ranges
(Note 1) Input Range 1.0% - 100%

Input Range 0.3% - 1.0%
Input Range 0.1% - 0.3%

Voltage RMS Accuracy All Gain Ranges
(Note 1) Input Range 5% - 100%

Analog Inputs (Both Channels)

Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB
Common Mode + Signal All Gain Ranges -0.25 - VA+ V

Analog Inputs (Current Channel)

Differential Input Range (Gain = 10)
[(IIN+) - (IIN-)] (Gain = 50)

Total Harmonic Distortion (Gain = 50) THD 80 94 - dB
Crosstalk with Voltage Channel at Full Scale (50, 60 Hz) - -115 - dB
Input Capacitance (Gain = 10)

(Gain = 50)

Effective Input Impedance EII 30 - - kΩ
Noise (Referred to Input) (Gain = 10)

(Gain = 50)

Offset Drift (Without the high-pass filter) OD - 4.0 - µV/°C
Gain Error (Note 2) GE - ±0.4 %

Analog Inputs (Voltage Channel)

Differential Input Range {(VIN+) - (VIN-)} VIN - 500 - mV

Total Harmonic Distortion THD 65 75 - dB
Crosstalk with Current Channel at Full Scale (50, 60 Hz) - -70 - dB
Input Capacitance All Gain Ranges IC - 0.2 - pF
Effective Input Impedance EII 2 - - MΩ
Noise (Referred to Input) N

Offset Drift (Without the high-pass Filter) OD - 16.0 - µV/°C
Gain Error (Note 2) GE - ±3.0 %

P

Active

I

RMS

V

RMS

IIN -

IC -

N

I

V

-40 - +85 °C

-±0.1- %
%

-

-

-

±0.1
±0.2
±3.0

-

-

-

%
%
%

-±0.1- %

500

-

100

32

-

-

-

52

-

-

--140µV

-

-

-

-

22.5

4.5

mV
mV

µV
µV

P-P

P-P

pF
pF

rms

rms

P-P

rms

DS661F1 7

CS5461A

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Unit

Temperature Channel

Temperature Accuracy T - ±5 - °C

Power Supplies

Power Supply Currents (Active State) I

I

(VA+ = VD+ = 5 V)

D+

I

(VA+ = 5 V, VD+ = 3.3 V)

D+

Power Consumption Active State (VA+ = VD+ = 5 V)
(Note 3) Active State (VA+ = 5 V, VD+ = 3.3 V)

Stand-By State

Sleep State

Power Supply Rejection Ratio (DC, 50 and 60 Hz)
(Note 4) Voltage Channel

Current Channel
PFMON Low-voltage Trigger Threshold (Note 5) PMLO 2.3 2.45 - V
PFMON High-voltage Power-On Trip Point (Note 6) PMHI - 2.55 2.7 V

1. Applies when the HPF option is enabled.

2. Applies before system calibration.

3. All outputs unloaded. All inputs CMOS level.

4. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz)
sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input
channels are shorted to AGND. Then the CS5461A is commanded to continuous conversion acquisition mode, and
digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output
signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured
in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output.
This voltage is then defined as Veq. PSRR is then (in dB)

PSRR 20

5. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.

6. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at
which the LSD bit can be permanently reset back to 0.

PSCA

A+

PSCD
PSCD

PC -

PSRR 45

⎧⎫

150

----------

log⋅=

⎨⎬

V

⎩⎭

-

-

-

-

-

-

70

:

eq

1.3

2.9

1.7

21
12

8

10

65
75

-

-

-

28

16.5

-

-

-

-

mA
mA
mA

mW
mW
mW

µW

dB
dB

VOLTAGE REFERENCE

Parameter Symbol Min Typ Max Unit

Reference Output

Output Voltage VREFOUT +2.4 +2.5 +2.6 V

Temperature Coefficient (Note 7) TC
Load Regulation (Note 8) ∆V

Reference Input

VREF

R

Input Voltage Range VREFIN +2.4 +2.5 +2.6 V

Input Capacitance - 4 - pF

Input CVF Current - 25 - nA

Notes: 7. The voltage at VREFOUT is measured across the temperature range. From these measurements the following

formula is used to calculate the VREFOUT Temperature Coefficient:.

TC

VREF

8. Specified at maximum recommended output of 1 µA, source or sink.

(VREFOUTMAX - VREFOUTMIN)

=

(

VREFOUT

AVG

(

1

(

T

MAX

- T

A

8 DS661F1

A

- 25 60 ppm/°C

-610mV

MIN

(

1.0 x 10

(

(

6

CS5461A

DIGITAL CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• MCLK = 4.096 MHz.

Parameter Symbol Min Typ Max Unit

Master Clock Characteristics

Master Clock Frequency Internal Gate Oscillator (Note 10) MCLK 2.5 4.096 20 MHz

Master Clock Duty Cycle 40 - 60 %

CPUCLK Duty Cycle (Note 11 and 12) 40 60 %

Filter Characteristics

Phase Compensation Range (Voltage Channel, 60 Hz) -2.8 - +2.8 °

Input Sampling Rate DCLK = MCLK/K - DCLK/8 - Hz

Digital Filter Output Word Rate (Both Channels) OWR - DCLK/1024 - Hz

High-pass Filter Corner Frequency -3 dB - 0.5 - Hz

Full Scale Calibration Range (

Channel-to-channel Time-shift Error (Note 14) 1.0 µs

Input/Output Characteristics

High-level Input Voltage

All Pins Except XIN and SCLK and RESET

Low-level Input Voltage (VD = 5 V)

All Pins Except XIN and SCLK and RESET

Low-level Input Voltage (VD = 3.3 V)

All Pins Except XIN and SCLK and RESET

High-level Output Voltage I

Low-level Output Voltage I

Input Leakage Current (Note 15) I

3-state Leakage Current I

Digital Output Pin Capacitance C

Referred to Input) (Note 13) FSCR 25 - 100 %F.S.

V

XIN

SCLK and RESET

XIN

SCLK and RESET

XIN

SCLK and RESET

= +5 mA V

out

= -5 mA V

out

IH

V

V

OH

OL

in

OZ

out

0.6 VD+

(VD+) - 0.5

0.8 VD+

IL

-

-

-

IL

-

-

-

-

-

-

-

-

-

0.2 VD+

-

-

-

0.2 VD+

(VD+) - 1.0 - - V

--0.4V

-±1±10µA

--±10µA

-5-pF

-

-

-

0.8

1.5

0.48

0.3

V
V
V

V
V
V

V
V
V

Notes: 9. All measurements performed under static conditions.

10. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used,
XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz.

11. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.

12. The frequency of CPUCLK is equal to MCLK.

13. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the
full-scale signal applied to the channel input.

14. Configuration Register bits PC[6:0] are set to “0000000”.

15. The MODE pin is pulled low by an internal resistor.

DS661F1 9

CS5461A

SWITCHING CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.

Parameter Symbol Min Typ Max Unit

Rise Times Any Digital Input Except SCLK
(Note 16) SCLK

Any Digital Output

Fall Times Any Digital Input Except SCLK
(Note 16) SCLK

Any Digital Output

Start-up

Oscillator Start-Up Time XTAL = 4.096 MHz (Note 17) t

Serial Port Timing

Serial Clock Frequency SCLK - - 2 MHz

Serial Clock Pulse Width High

Pulse Width Low

SDI Timing

CS Falling to SCLK Rising t

Data Set-up Time Prior to SCLK Rising t

Data Hold Time After SCLK Rising t

SDO Timing

CS Falling to SDO Driving t

SCLK Falling to New Data Bit (hold time) t

Rising to SDO Hi-Z t

CS

Auto-Boot Timing

Serial Clock Pulse Width Low

Pulse Width High

MODE setup time to RESET

RESET

CS

SCLK falling to CS

CS

rising to CS falling t

falling to SCLK rising t

rising t

rising to driving MODE low (to end auto-boot sequence). t

Rising t

SDO guaranteed setup time to SCLK rising t

Notes: 16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external
clock source.

t

rise

t

fall

ost

t
t

t

t

10

11

12

13

14

15

16

-

-

-

-

-

-

50

50

-

-

-

-

1.0

100

-

1.0

100

-

µs
µs
ns

µs
µs
ns

-60-ms

1

2

3

4

5

6

7

8

9

200
200

50 - - ns

50 - - ns

100 - - ns

-2050ns

-2050ns

-2050ns

-

-

8
8

-

-

ns
ns

MCLK
MCLK

50 ns

48 MCLK

100 8 MCLK

16 MCLK

50 ns

100 ns

10 DS661F1

CS

CS5461A

t

3

SCLK

SDI

CS

SDO

SCLK

SDI

MSB

MSB-1

t

1

t

2

t

4

LSB

MSB

MSB-1

t

5

LSB

MSB

MSB-1

LSB

MSB

MSB-1

Com m and Time 8 SCLKs High Byte Mid B yte Low Byte

SDI Write Timing (Not to Scale)

t

6

UNKNOW N

t

1

MSB

MSB-1

Com m and T ime 8 SC LKs

t

2

LSB

High Byte Mid Byte Low Byte

MSB

MSB-1

t

7

SYNC0 or SYNC1

Com m and

LSB

MSB

MSB-1

SYNC0 or SYNC1

Com m and

LSB

MSB

MSB-1

SYNC0 or SYNC1

Com m and

LSB

t

8

LSB

MODE

(INPUT)

RESET

(INPUT)

CS

(O UT P U T)

SCLK

(O UT P U T)

SDO

(O UT P U T)

SDI

(INPUT)

SDO Read Timing (Not to Scale)

t

11

t

12

t

t

13

t

10

7

t

16

t

9

t

4

t

5

D a ta fro m EE P R O M

STOP bit

Last 8

Bits

t

15

t

14

Auto-Boot Sequence Timing (Not to Scale)

Figure 1. CS5461A Read and Write Timing Diagrams

DS661F1 11

ABSOLUTE MAXIMUM RATINGS

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Notes 18 and 19)

Positive Digital

Positive Analog

Input Current, Any Pin Except Supplies (Notes 20, 21, 22) I

Output Current, Any Pin Except VREFOUT I

Power Dissipation (Note 23) P

Analog Input Voltage All Analog Pins V

Digital Input Voltage All Digital Pins V

Ambient Operating Temperature T

Storage Temperature T

Notes: 18. VA+ and AGND must satisfy {(VA+) - (AGND)} ≤ + 6.0 V.

19. VD+ and AGND must satisfy {(VD+) - (AGND)}

20. Applies to all pins including continuous over-voltage conditions at the analog input pins.

21. Transient current of up to 100 mA will not cause SCR latch-up.

22. Maximum DC input current for a power supply pin is ±50 mA.

23. Total power dissipation, including all input currents and output currents.

≤ + 6.0 V.

.

VD+

VA+

IN

OUT

D --500mW

INA

IND

A

stg

-0.3

-0.3

-

-

--±10mA

--100mA

- 0.3 - (VA+) + 0.3 V

-0.3 - (VD+) + 0.3 V

-40 - 85 °C

-65 - 150 °C

CS5461A

+6.0
+6.0

V
V

12 DS661F1

VOLTAGE

x10

2nd Order

∆Σ

Modulator

DELAY

REG

Digital Filter

3

SINC

CS5461A

V*

V

*

gn

DCoff

+

+

HPF

IIR

X

Option

Σ

*

V

X

N

X

Σ

÷

N

V

*

ACoff

+

+

Σ

√

V*

RMS

6

*

CURRENT

PGA

4th Order

Modulator

*

DENOTES REGISTER NAME.

PC6 PC5 PC4 PC3

Configuration Register *

∆Σ

SINC

PC2

PC1 PC0

3

DELAY

REG

Digital Filter

SYS

Gain

IIR

X

Figure 2. Data Flow.

4. THEORY OF OPERATION

The CS5461A is a dual-channel analog-to-digital con­verter (ADC) followed by a computation engine that per­forms power calculations and energy-to-pulse
conversion. The flow diagram for the two data paths is
depicted in Figure 2. The analog inputs are structured
with two dedicated channels, voltage and current, then
optimized to simplify interfacing to sensing elements.

The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is sub­ject to a gain of 10x. A second-order, delta-sigma mod­ulator samples the amplified signal for digitization.

Simultaneously, the current-sensing element introduces
a voltage waveform on the current channel input IIN±
and is subject to the two selectable gains of the pro­grammable gain amplifier (PGA). The amplified signal is
sampled by a fourth-order, delta-sigma modulator for
digitization. Both converters sample at a rate of
MCLK/8, the over-sampling provides a wide dynamic
range and simplified anti-alias filter design.

4.1 Digital Filters

The decimating digital filters on both channels are Sinc
filters followed by 4th-order, IIR filters. The single-bit
data is passed to the low-pass decimation filter and out­put at a fixed word rate. The output word is passed to
the IIR filter to compensate for the magnitude roll-off of
the low-pass filtering operation.

An optional digital High-pass Filter (HPF in Figure 2) re­moves any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled, the DC component will be removed
from the calculated V
ent power.

RMS

and I

as well as the appar-

RMS

HPF

Option

*

P

PulseRateE

off

+

X

Σ

+

*

PulseRateE

P

+

I

Σ

DCoff

X

+

I*

*

gn

X

*

I

Σ

*

1,2

*

3

N

X

N

Σ

÷

N

Energy-to-pulseX

÷

Energy-to-pulse

√

P

Active

N

+

I

ACoff

4.2 Voltage and Current Measurements

The digital filter output word is then subject to a DC off­set adjustment and a gain calibration (See Section 7.

System Calibration on page 33). The calibrated mea-

surement is available to the user by reading the instan­taneous voltage and current registers.

The Root Mean Square (RMS) calculations are per­formed on N instantaneous voltage and current sam­ples, V

n and In respectively (where N is the cycle count),

using the formula:

N1–

I

∑

n0=

--------------------

N

n

RMS

and V

and likewise for V

I

RMS

, using Vn. I

RMS

=

cessible by register reads, which are updated once ev­ery cycle count (referred to as a computational cycle).

3

4.3 Power Measurements

The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Fig-

ure 2). The product is then averaged over N conver-

sions to compute active power and used to drive energy
pulse outputs E1
form pulse stream that is proportional to the active pow­er and is designed for system calibration.

To generate a value for the accumulated active energy
over the last computation cycle, the active power can be
multiplied by the time duration of the computation cycle.

, E2 and E3. Output E3 provides a uni-

E3

E1
E2

Σ

+

RMS

*

*

X

S

I*

RMS

are ac-

*

DS661F1 13