• Energy Data Linearity: ±0.1% of Reading over
1000:1 Dynamic Range
• On-chip Functions:
- Instantaneous Voltage, Current, and Power
- I
and V
RMS
- Energy-to-pulse Conversion for Mechanical
Counter/Stepper Motor Drive
- System Calibrations and Phase Compensation
- Temperature Sensor
- Voltage Sag Detect
• Meets Accuracy Spec for IEC, ANSI, & JIS.
• Low Power Consumption
• Current Input Optimized for Sense Resistor.
• GND-referenced Signals with Single Supply
• On-chip 2.5 V Reference (25 ppm/°C typ)
• Power Supply Monitor
• Simple Three-wire Digital Serial Interface
• “Auto-boot” Mode from Serial E
• Power Supply Configurations:
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
, Apparent and Active (Real) Power
RMS
2
PROM.
Description
The CS5461A is an integrated power measurement device which combines two
analog-to-digital converters, power calculation
engine, energy-to-frequency converter, and a
serial interface on a single chip. It is designed to
accurately measure instantaneous current and
voltage, and calculate V
neous power, apparent power, and active power
for single-phase, 2- or 3-wire power metering
applications.
The CS5461A is optimized to interface to shunt
resistors or current transformers for current measurement, and to resistive dividers or potential
transformers for voltage measurement.
The CS5461A features a bi-directional serial interface for communication with a processo r, an d
a programmable energy-to-pulse output function. Additional features include on-chip
functionality to facilitate system-level calibration,
temperature sensor, voltage sag detection, and
phase compensation.
Figure 1. CS5461A Read and Write Timing Diagrams ........................................................................... 11
Figure 2. Data Flow.................................................................................................................................13
Figure 3. Normal Format on pulse outputs E1
Figure 4. Alternate Pulse Format on E1
Figure 5. Mechanical Counter Format on E1
Figure 6. Stepper Motor Format on E1
Figure 7. Voltage Sag Detect..................................................................................................................19
The CS5461A is a CMOS monolithic power measurement device with a computation engine and an energy-to-frequency pulse output. The CS5461A combines a programmable-gain amplifier, two analog-to-digital converters (ADCs), system calibration and a computation engine on a single chip.
The CS5461A is designed for power measurement applications and is optimized to interface to a current-sense resistor or transformer for current measurement, and to a resistive divider or potential transformer for voltage measurement. The voltage and current channels provide programmable gains to
accommodate various input levels from a wide variety of sensing elements. With single +5 V supply on
VA+/AGND, both of the CS5461A’s input channels can accommodate common mode as well as signal
levels between (AGND - 0.25 V) and VA+.
Additionally, the CS5461A is equipped with a computation engine that calculates I
power and active (real) power. To facilitate communication to a microprocessor, the CS5461A includes a
simple three-wire serial interface which is SPI™ and Microwire™ compatible. The CS5461A provides
three outputs for energy registration. E1
stepper motor, or interface to a microprocessor. The pulse output E3
ibration.
and E2 are designed to directly drive a mechanical counter or
is designed to assist with meter cal-
RMS
, V
, apparent
RMS
DS661F35
CS5461A
VREFIN12Voltage Reference Input
VREFOUT11Voltage Reference Output
VIN-10Differential Voltage Input
VIN+9Differential Voltage Input
MODE8Mode Select
CS7Chip S e le c t
SDO6Serial D a ta Ouput
SCLK5Serial Clock
DGND4Digital Ground
VD+3Positiv e Digital Supply
CPUCLK2CPU Clock Output
XOUT1Crystal Out
AGND13Analog Ground
VA+14Positive Analog Supply
IIN-15Differential Current Input
IIN+16Differential Current Input
PFMON17Power Fail Monito r
E318High Frequency Energ y O utput
RESET19Reset
INT20Interr up t
E121Energy Output 1
22
SDI23Serial Data Input
XIN24Crystal In
E2
Energy Output 2
2. PIN DESCRIPTION
Clock Generator
Crystal Out
Crystal In
CPU Clock Output2
Control Pins and Serial Data I/O
Serial Clock Input5
Serial Data Output6
Chip Select7
Mode Select8
High Frequency Energy
Output
Reset19
Interrupt20
Energy Output21,22
Serial Data Input23
Analog Inputs/Outputs
Differential V ol tage Inputs9,10
Differential Current Inputs15,16
Voltag e Reference Output11
Voltage Reference Input12
Power Supply Connections
Positive Digital Supply3
Digital Ground4
Positive Analog Supply14
Analog Ground13
Power Fail Monitor
6DS661F3
XOUT, XIN - The output and input of an inverting amplifier. Oscillation occurs when connected to
1,24
a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to
the XIN pin to provide the system clock for the device.
CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
SCLK - A Schmitt Trigger input pin. Clocks data from the SDI pin into the receive buffer and out of
the transmit buffer onto the SDO pin when CS
SDO -Serial port data output pin.SDO is forced into a high impedance state when CS is high.
CS - Low, activates the serial port interface.
MODE - High, enables the “auto-boot” mode. The mode pin is pulled low by an internal resistor.
18
E3 - Active low pulses with an output frequency proportional to the active power. Used to assist
in system calibration.
RESET - A Schmitt Trigger input pin. Low activates Reset, all internal registers (some of which
drive output pins) are set to their default states.
INT - Low, indicates that an enabled event has occurred.
is low.
E1, E2 - Active low pulses with an output frequency proportional to the active power. Indicates if
the measured energy is negative.
SDI - Serial port data input pin. Data will be input at a rate determined by SCLK.
VIN+, VIN- - Differential analog input pins for the voltage channel.
IIN+, IIN- - Differential analog input pins for the current channel.
VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magni-
tude of 2.5 V and is referenced to the AGND pin on the converter.
VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.
VD+ - The positive digital supply.
DGND - Digital Ground.
VA+ - The positive analog supply.
AGND - Analog ground.
PFMON - The power fail monitor pin monitors the analog supply. If PFMON’s voltage threshold is
17
not met, a Low-Supply Detect (LSD) bit is set in the status register.
CS5461A
3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ParameterSymbol Min TypMaxUnit
Positive Digital Power SupplyVD+3.1355.05.25V
Positive Analog Power SupplyVA+4.755.05.25V
Voltage ReferenceVREFIN-2.5-V
Specified Temperature RangeT
A
ANALOG CHARACTERISTICS
•Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
•Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
•VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.
•MCLK = 4.096 MHz.
ParameterSymbol Min TypMaxUnit
Linearity Performance
Active Power Accuracy (All Gain Ranges)
(Note 1)Input Range 0.1% - 100%
Current RMS Accuracy (All Gain Ranges)
(Note 1)Input Range 0.2% - 100%
Input Range 0.1% - 0.2%
Voltage RMS Accuracy (All Gain Ranges)
(Note 1)Input Range 5% - 100%
Analog Inputs (Both Channels)
Common Mode Rejection(DC, 50, 60 Hz)CMRR80--dB
Common Mode + Signal (All Gain Ranges)-0.25-VA+V
(Gain = 50)
Offset Drift (Without the high-pass filter)OD-4.0-µV/°C
Gain Error(Note 2)GE-±0.4%
Analog Inputs (Voltage Channel)
Differential Input Range{(VIN+) - (VIN-)}
Total Harmonic DistortionTHD6575-dB
Crosstalk with Current Channel at Full Scale(50, 60 Hz)--70-dB
Input CapacitanceAll Gain RangesIC-0.2-pF
Effective Input ImpedanceEII2--M
Noise (Referred to Input)N
Offset Drift (Without the high-pass Filter)OD-16.0-µV/°C
Gain Error(Note 2)GE-±3.0%
P
Active
I
RMS
V
IIN
VIN
RMS
IC
N
I
V
-40-+85°C
-±0.1-%
-
-
±0.2
±1.5
-
-
%
%
-±0.1-%
-
-
-
-
-
-
-500-mV
-140-µV
500
100
32
52
22.5
4.5
-
-
-
-
-
-
mV
mV
µV
µV
P-P
P-P
pF
pF
rms
rms
P-P
rms
DS661F37
CS5461A
PSRR20
150
V
eq
--------- -
log=
(VREFOUTMAX - VREFOUTMIN)
VREFOUT
AVG
(
(
1
T
A
MAX
- T
A
MIN
(
(
1.0 x 10
(
(
6
TC
VREF
=
ANALOG CHARACTERISTICS (Continued)
ParameterSymbol Min TypMaxUnit
Temperature Channel
Temperature AccuracyT-±5-°C
Power Supplies
Power Supply Currents (Active State)I
I
(VA+ = VD+ = 5 V)
D+
I
(VA+ = 5 V, VD+ = 3.3 V)
D+
A+
PSCA
PSCD
PSCD
Power Consumption Active State (VA+ = VD+ = 5 V)
(Note 3) Active State (VA+ = 5 V, VD+ = 3.3 V)
Stand-By State
PC
Sleep State
Power Supply Rejection Ratio(DC, 50 and 60 Hz)
(Note 4)Voltage Channel
4. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz)
sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input
channels are shorted to AGND. Then the CS5461A is commanded to continuous conversion acquisition mode, and
digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output
signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured
in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output.
This voltage is then defined as Veq. PSRR is then (in dB)
:
45
70
-
-
-
-
-
-
-
1.1
2.9
1.7
21
12
8
10
65
75
-
-
-
28
16.5
-
-
-
-
mA
mA
mA
mW
mW
mW
µW
dB
dB
5. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.
6. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at
which the LSD bit can be permanently reset back to 0.
VOLTAGE REFERENCE
ParameterSymbol Min TypMaxUnit
Reference Output
Output VoltageVREFOUT+2.4+2.5+2.6V
Temperature Coefficient(Note 7)TC
Load Regulation(Note 8)V
Reference Input
VREF
R
Input Voltage RangeVREFIN+2.4+2.5+2.6V
Input Capacitance-4-pF
Input CVF Current-25-nA
Notes: 7. The voltage at VREFOUT is measured across the temperature range. From these measurements the follo wing
formula is used to calculate the VREFOUT Temperature Coefficient:.
8. Specified at maximum recommended output of 1 µA, source or sink.
-2560ppm/°C
-610mV
8DS661F3
CS5461A
DIGITAL CHARACTERISTICS
•Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
•Typical characteristics and specifications are measured at nominal supply volt ages and TA = 25 °C.
•VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
Notes: 9. All measurements performed under static conditions.
10. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used,
XIN frequency range is 2.5 M Hz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz.
11. If external MCLK is used, then the duty cycl e must be between 45% and 55% to maintain this specific ation.
12. The frequency of CPUCLK is equal to MCLK.
13. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the
full-scale signal applied to the channel input.
14. Configuration Register bits PC[6:0] are set to “0000000”.
15. The MODE pin is pulled low by an internal resistor.
DS661F39
CS5461A
SWITCHING CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
•Typical characteristics and specifications are measured at nominal supply volt ages and TA = 25 °C.
•VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
•Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
ParameterSymbol Min TypMaxUnit
Rise TimesAny Digital Input Except SCLK
(Note 16)SCLK
Any Digital Output
Fall TimesAny Digital Input Except SCLK
(Note 16)SCLK
Serial Clock FrequencySCLK--2MHz
Serial ClockPulse Width High
Pulse Width Low
SDI Timing
CS Falling to SCLK Risingt
Data Set-up Time Prior to SCLK Risingt
Data Hold Time After SCLK Risingt
SDO Timing
CS Falling to SDO Drivingt
SCLK Falling to New Data Bit (hold time)t
Rising to SDO Hi-Zt
CS
Auto-Boot Timing
Serial ClockPulse Width Low
Pulse Width High
MODE setup time to RESET
RESET
CS
SCLK falling to CS
CS
rising to CS fallingt
falling to SCLK risingt
risingt
rising to driving MODE low (to end auto-boot sequence).t
Risingt
SDO guaranteed setup time to SCLK risingt
Notes: 16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external
clock source.
t
rise
t
t
fall
ost
t
t
t
10
11
12
13
14
15
16
-
-
-
-
-
-
50
50
-
-
-
-
1.0
100
-
1.0
100
-
µs
µs
ns
µs
µs
ns
-60-ms
1
2
3
4
5
6
7
8
9
200
200
50--ns
50--ns
100--ns
-2050ns
-2050ns
-2050ns
-
-
8
8
-
-
ns
ns
MCLK
MCLK
50ns
48MCLK
1008MCLK
16MCLK
50ns
100ns
10DS661F3
t
1
t
2
t
3
t
4
t
5
MSB
MSB-1
LSB
MSB
MSB-1
LSB
MSB
MSB-1
LSB
MSB
MSB-1
LSB
Com m and Time 8 S CLKsHigh ByteMid ByteLow B yte
CS
SCLK
SDI
t
10
t
9
RESET
SDO
SCLK
CS
Last 8
Bits
SDI
MODE
STOP bit
D a ta fro m E E P R O M
t
16
t
4
t
5
t
14
t
15
t
7
t
13
t
12
t
11
(INPUT)
(INPUT)
(O UT P U T )
(O UT P U T )
(O UT P U T )
(INPUT)
SDI Write Timing (Not to Scale)
SDO Read Timing (Not to Scale)
Figure 1. CS5461A Read and Write Timing Diagrams
Auto-Boot Sequence Timing (Not to Scale)
t
1
t
2
MSB
MSB-1
LSB
Com m and Time 8 SC LKs
SYNC0 or SYNC1
Command
SYN C 0 or SYN C1
Command
MSB
MSB-1
LSB
MSB
MSB-1
LSB
MSB
MSB-1
LSB
H igh B y teM id B y teLo w B y te
CS
SDO
SDI
t
6
t
7
t
8
SYN C 0 or SYN C1
Command
UNKNOWN
CS5461A
DS661F311
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes
ParameterSymbol Min TypMaxUnit
DC Power Supplies(Notes 18 and 19)
Positive Digital
Positive Analog
Input Current, Any Pin Except Supplies(Notes 20, 21, 22)I
Output Current, Any Pin Except VREFOUTI
Power Dissipation(Note 23)P
Analog Input VoltageAll Analog PinsV
Digital Input VoltageAll Digital PinsV
Ambient Operating TemperatureT
Storage TemperatureT
Notes: 18. VA+ and AGND must satisfy {(VA+) - (AGND)} + 6.0 V.
19. VD+ and AGND must satisfy {(VD+) - (AGND)}
20. Applies to all pins including cont inuous over-voltage conditions at the analog input pins.
21. Transient current of up to 100 mA will not cause SCR latch-up.
22. Maximum DC input current for a power supply pin is ±50 mA.
23. Total power dissipation, including all input currents and output currents.
+ 6.0 V.
.
VD+
VA+
IN
OUT
D--500mW
INA
IND
A
stg
-0.3
-0.3
-
-
--±10mA
--100mA
- 0.3-(VA+) + 0.3V
-0.3-(VD+) + 0.3V
-40-85°C
-65-150°C
CS5461A
+6.0
+6.0
V
V
12DS661F3
4. THEORY OF OPERATION
VOLTAGE
SINC
3
+
X
V*
gn
X
V
*
CURRENT
SINC
3
+
X
I*
gn
DELAY
REG
DELAY
REG
HPF
Option
X
I*
RMS
V*
RMS
E1
IIR
I
*
I
DCoff
*
V
DCoff
*
PGA
IIR
X
+
+
Energy-to-pulseX
E3
+
X
+
Configuration Register *
Digital Filter
Digital Filter
HPF
Option
X
S
*
2nd Order
Modulator
4th Order
Modulator
x10
+
I
ACoff
*
+
+
V
ACoff
*
+
E2
N
÷
N
N
÷
N
P
*
Active
N
÷
N
P
off
*
P
*
X
X
SYS
Gain
*
PC6 PC5 PC4 PC3
PC2
PC1 PC0
6
PulseRateE
1,2
*
PulseRateE
3
*
Energy-to-pulse
*
DENOTES REGISTER NAME.
APF
Option
APF
Option
Figure 2. Data Flow.
I
RMS
I
n
n0=
N1–
N
--------------------
=
The CS5461A is a dual-channel analog-to-digital converter (ADC) followed by a computation engine that performs power calculations and energy-to-pulse
conversion. The flow diagram for the tw o data paths is
depicted in Figure 2. The analog inputs are structured
with two dedicated channels, voltage and current, then
optimized to simplify interfacing to sensing elements.
The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is subject to a gain of 10x. A second-order, delta-sigma modulator samples the amplified signal for digitization.
Simultaneously, the current-sensing element introduces
a voltage waveform on the current channel input IIN±
and is subject to the two selectable gains of the programmable gain amplifier (PGA). The amplified signal is
sampled by a fourth-order, delta-sigma modulator for
digitization. Both converters sample at a rate of
MCLK /8, the over-sampling provides a wide dynamic
range and simplified anti-alias filter design.
CS5461A
When the HPF option is used in only one channel, the
APF (all pass filter) option can be applied to the other
channel to preserve the phase match between the two
channels.
4.2 Voltage and Current Measurements
The digital filter output word is then subject to a DC offset adjustment and a gain calibration (See Section 7.
System Calibration on page 35). The calibrated me a-
surement is available to the user by reading the instantaneous voltage and current registers.
The Root Mean Square (RMS) calculations are performed on N instantaneous voltage and current samples, V
n and In respectively (where N is the cycle count),
using the formula:
4.1 Digital Filters
The decimating digital filters on both channels a re Sinc
filters followed by 4th-order, IIR filters. The single-bit
data is passed to the low-pass decimation filter and output at a fixed word rate. The o utput word is passed to
the IIR filter to compensate for the magnitude roll-off of
the low-pass filtering operation.
An optional digital High-pass Filter (HPF in Figure 2) removes any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled, the DC component will be removed
from the calculated V
ent power.
DS661F313
RMS
and I
as well as the appar-
RMS
3
and likewise for V
, using Vn. I
RMS
RMS
and V
RMS
cessible by register reads, which are updated once every cycle count (referred to as a computational cycle).
4.3 Power Measurements
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Fig-
ure 2). The product is then averaged over N conver-
provides a uni-
sions to compute active power and used to drive energy
pulse outputs E1, E2 and E3. Output E3
form pulse stream that is proportional to the active power and is designed for system calibration.
are ac-
CS5461A
SV
RMSIRMS
=
To generate a value for the accumulated active energy
over the last computation cycle, the active power can be
multiplied by the time duration of the computation cycle.
The apparent power is the combination of the active
power and reactive power, without reference to an impedance phase angle, and is calculated by the
CS5461A using the following formula:
The apparent power is registered on ce eve ry co mpu tation cycle.
4.4 Linearity Performance
The linearity of the V
surements (before calibration) will be within ±0.1% of
RMS
, I
, and active power mea-
RMS
reading over the ranges specified, with respect to the input voltage levels required to cause full-scale readings
in the I
RMS
and V
registers. Refer to Linearity Per-
RMS
formance Specifications on page 7.
Until the CS5461A is calibrated, the accuracy of the
CS5461A (with respect to a reference line-voltage and
line-current level on the power mains) is not guaranteed
to within ±0.1%. See Section 7. System Calibration on
page 35. The accuracy of the internal calculations can
often be improved by selecting a value for the CycleCount Register that will cause the time duration of one
computation cycle to be equal to (or very close to) a
whole-number of power-line cycles (and N must be
greater than or equal to 4000).
14DS661F3
5. FUNCTIONAL DESCRIPTION
250mV
P
2
---------------------
176.78mV
RMS
OWR
MCLK K
1024
-----------------------------
=
Computation Cycle
OWR
N
---------------
=
2231–
2
23
------------------------
0.99999988
=
CS5461A
5.1 Analog Inputs
The CS5461A is equipped with two fully differential input channels. The inputs VIN and IIN are designated
as the voltage and current channel inputs, respectively.
The full-scale differential input voltage for the current
and voltage channel is 250 mV
.
P
5.1.1 Voltage Channel
The output of the line-voltage resistive divider or transformer is connected to the VIN+ and VIN- input pins of
the CS5461A. The voltage channel is equipped with a
10x, fixed-gain amplifier. The full-scale signal level that
can be applied to the voltage channel is 250 mV. If the
input signal is a sine wave the maximum RMS voltage
at a gain 10x is:
which is approximately 70.7% of maximum peak voltage. The voltage channel is also equipped with a Volt-age Gain Register, allowing for an additional
programmable gain of up to 4x.
5.1.2 Current Channel
The output of the current-sense resistor or transformer
is connected to the IIN+ and IIN- input pins of the
CS5461A. To accommodate different current-sensing
elements, the current channel incorporates a Programmable Gain Amplifier (PGA) with two programmable input gains. Configuration Register bit Igain (See Table 1)
defines the two gain selections and corresponding maximum input-signal level.
IgainMaximum Input Range
0±250mV10x
1±50 mV50x
Table 1. Current Channel PGA Configuration
For example, if Igain=0, the current channel’s PGA gain
is set to 10x. If the input signals are pure sinusoids with
zero phase shift, the maximum peak differential signal
on the current or voltage channel is 250 mV
put-signal levels are approximately 70.7% of maximum
peak voltage producing a full-scale energy pulse registration equal to 50% of absolute maximum energy pulse
registration. This will be discussed further in Section 5.4
Energy Pulse Output on page 16.
The Current Gain Register also allows for an additional
programmable gain of up to 4x. If an ad ditional gain is
. The in-
P
applied to the voltage and/or current channel, the maximum input range should be adjusted accordingly.
5.2 High-pass Filters
By removing the offset from either channel, no error
component will be generated at DC when computing the
active power. By removing the offset from both channels, no error component will be generated at DC when
computing V
RMS
, I
, and apparent power. Configura-
RMS
tion Register bits VHPF and IHPF activate the HPF in
the voltage and current channel respectively.
5.3 Performing Measurements
The CS5461A performs measurements of instantaneous voltage (V
stantaneous power (P
of
where K is the clock divider setting in the ConfigurationRegister.
The RMS voltage (V
tive power (P
neous samples of V
the value in the Cycle Count Register (N) and is referred
to as a “computation cycle”. The apparent power (S) is
the product of V
derived from the master clock (MCLK), with frequency:
Under default conditions & with K = 1, N = 4000, and
MCLK = 4.096 MHz – the OWR = 4000 Hz and the
ComputationCycle= 1Hz.
All measurements are available as a percentage of full
scale. The format for signed registers is a two’s complement, normalized value between -1 and +1. The format
for unsigned registers is a normalized value between 0
and 1. A register value of
represents the maximum possible value.
At each instantaneous measurement, the CRDY bit will
be set (logic 1) in the Status Register, and the INT
will become active if the CRDY bit is unmasked in the
Mask Register. At the end of each computation cycle,
the DRDY bit will be set in the Status Register, and the
) and current (In), and calculates in-
n
) at an Output Word Rate (OWR)
n
), RMS current (I
RMS
) are computed using N instanta-
Active
, In and Pn respectively, where N is
n
RMS
and I
. A computation cycle is
RMS
RMS
), and ac-
pin
DS661F315
INT pin will become active if the DRDY bit is unmasked
FREQE = Average frequency of E1 and E2 pulses [Hz]
VIN = rms voltage across VIN+ and VIN- [V]
VGAIN = Voltage channel gain
IIN = rms voltage across IIN+ and IIN- [V]
IGAIN = Current channel gain
PF = Power Factor
PulseRateE
Figure 3. Normal Format on pulse outputs E1 and E2
in the Mask Register. When these bits are set, they
must be cleared (logic 0) by the user before they can b e
asserted again.
If the Cycle Count Register (N) is set to 1, all output calculations are instantaneous, and DRDY, like CRDY, will
indicate when instantaneous measurements are finished. Some calculations are inhibited when the cycle
count is less than 2.
5.4 Energy Pulse Output
The CS5461A provides three output pins fo r energy registration. The E1
which energy can be registered. These pins are designed to directly connect to a stepper motor or electromechanical counter. E1
of four pulse output formats, Normal, Alternate, Steppe r
Motor, or Mechanical Counter. Table 2 defines the
pulse output format, which is controlled by bits ALT in
the Configuration Register, and MECH and STEP in the
Control Register.
ALTSTEPMECHFORMAT
000Normal
0X1Mechanical Counter
010Stepper Motor
1X1Alternate Pulse
Table 2. E1 and E2 Pulse Output Format
The E3
pin is designated for system calibration, the
pulse rate can be selected to reach a frequency of
512 kHz.
The pulse output frequency of E1
portional to the active power calculated from the input
signals. To calculate the output frequency on E1
E2
, the following transfer function can be utilized:
and E2 pins provide a simple interface
and E2 pins can be set to one
and E2 is directly pro-
and
CS5461A
With MCLK = 4.096 MHz, PF = 1, and default settings,
the pulses will have an average frequency equal to the
frequency setting in the PulseRateE
the input signals applied to the voltage and current
channels cause full-scale readings in the instantaneo us
voltage and current registers. When MCLK/K is not
equal to 4.096 MHz, the user should scale the
PulseRateE
Register by a factor of
1,2
4.096 MHz/ (MCLK / K) to get the actual pulse rate output.
5.4.1 Normal Format
The Normal format is the default. Figure 3 illustrates the
output format on pins E1
tive-low pulses with a frequency proportional to the active power. The E2
Positive energy is represented by a pulse on the E1
while the E2
pin remains high. Negative energy is represented by synchronous pulses on both the E1
the E2
pin.
The PulseRateE
1,2
quency on output pin E1
are applied to the voltage and current channels. The
maximum pulse frequency from the E1
and E2. The E1 pin outputs ac-
pin is the energy direction indicator.
Register defines the average fre-
, when full-scale input signals
Register when
1,2
pin and
pin
pin
16DS661F3
CS5461A
t
dur
sec
1
PulseRateE
12,
8
--------------------------------------------
1
(MCLK/K)/16 8
-----------------------------------
t
dur
sec
1
(MCLK/K)/1024 8
---------------------------------------- -
Figure 4. Alternate Pulse Format on E1 and E2
E1
...
...
E2
......
...
t
PW
FREQ
E
tPWms
PW
(MCLK/K)/1024
-----------------------------------------
=
PulseRateE
12,
1
t
PW
----------- -
t
PW
E1
Positive Energy
Negative Energy
...
...
...
...
E2
FREQ
E
Figure 5. Mechanical Counter Format on E1 and E2
is ( MCLK /K) /16. The pulse duration (t
) is an integer
dur
multiple of MCLK cycles, approximately equal to:
The maximum pulse duration (t
) is determined by the
dur
sampling rate and the minimum is defined by the maximum pulse frequency. The t
limits are:
dur
The Pulse Width Register (PW) does not affect the normal format.
5.4.2 Alternate Pulse Format
Setting bits MECH = 1 and STEP = 0 in the Control
Register and ALT = 1 in the Configuration Register con-
figures the E1
output (see Figure 4). Each pin produces alternating ac tive-low pulses with a pulse duration (t
the Pulse Width Register (PW):
If MCLK = 4.096 MHz, K = 1, and PW = 1 then
t
= 0.25 m s. To ensure that pulses occur on the E1
PW
and E2 pins for alternating pulse format
) defined by
PW
and E2 output pins when full-scale input signals are applied to the voltage and current channels, then:
The pulse frequency (FREQ
PulseRateE
Register and can be calculated using the
1,2
) is determined by the
E
transfer function. The energy direction is not d efined in
the alternate pulse format.
5.4.3 Mechanical Counter Format
Setting bits MECH = 1 and STEP = 0 in the Control
Register and bit ALT = 0 in the Configuration Register
enables E1
and E2 for mechanical counters and similar
discrete counting instruments. When energy is negative, pulses appear on E2
is positive, the pulses appear on E1
(see Figure 5). When energy
. The pulse width is
defined by the Pulsewidth Register and will limit the output pulse frequency (FREQ
). By default, PW = 512
E
samples, if MCLK = 4.096 MHz and K = 1 then
t
= 128 ms. To ensure that pulses will occur, the
PW
PulseRateE
Register must be set to an appropr iate
1,2
value.
5.4.4 Stepper Motor Format
Setting bits STEP = 1 and MECH = 0 in the Control
Register and bit ALT = 0 in the Configuration Register
configures the E1
When the accumulated active power equals the defined
energy level, the energy output pins (E1 and E2) alternate changing states (see Figure 6). The duration
(t
) between the alternating states is defined by the
edge
transfer function:
The direction the motor will rotate is determined by the
order of the state changes. When energy is positive, E1
will lead E2. When energy is negative, E2 will lead E1.
The Pulse Width Register (PW) does not affect the step-
per motor format.
5.4.5 Pulse Output E3
The pulse output E3
ibration. The pulse-output frequency of E3
proportional to the active power calculated from the input signals. E3
ular transfer function as E1
PulseRateE
The E3
3
pin outputs negative and positive energy, but
has no energy direction indicator.
The pulse width of E3
register defines the pulse width of E3
or:
The default value is 0.
is designed to assist with meter cal-
is directly
pulse frequency is derived using a sim-
, but is set by the value in the
Register.
is configurable. The PulseWidth
in units of 1/OWR
alternating polarity occurs during the accumulation period (e.g. random noise at zero power levels), the accuracy of the registered energy will be maintained.
For high-frequency pulse output formats (i.e. normal
and alternate pulse formats), the active power is accumulated over time until a 8x buffer is defined. Then,
when the designated energy level is reached, a pulse is
generated on E1
and/or E2. For pulse outputs with high
frequencies and power levels close to zero, the extended buffer prevents random noise from being registered
as active energy.
5.4.7 Design Examples
EXAMPLE #1:
The maximum rated levels for a power line meter are
250 V rms and 20 A rms. The required number of pulses per second on E1
when the levels on the power line are 220 V rms and
15 A rms.
With a 10x gain on the voltage and current channel the
maximum input signal is 250 mV
alog Inputs on page 15). To prevent over-driving the
channel inputs, the maximum rated rms input levels will
register 0.6 in V
voltage level at the channel inputs will be 150 mV rms
when the maximum rated levels on the power lines are
250 V rms and 20 A rms.
Solving for PulseRateE
is 100 pulses per second (100 Hz),
(see Section 5.1 An-
P
RMS
and I
by design. Therefore the
RMS
using the transfer function:
1,2
5.4.6 Anti-creep for the Pulse Outputs
Anti-creep allows the measurement element to maintain
an energy level, such that when the magnitude of the
accumulated active power is below this level, no energy
pulses are output. Anti-creep is enabled by setting bit
FAC in the Control Register for E3
Control Register for E1
For low-frequency pulse output formats (i.e. mechanical
counter and stepper motor formats), the active power is
accumulated over time. When a designated energy level is reached (determined by the transfer function) a
pulse is generated on E1
18DS661F3
and E2.
and/or E2. If active power with
and bit EAC in the
Therefore with PF = 1 and
the PulseRateE
Register is set to:
1,2
CS5461A
12,
500pulses
kWHr
------------------------------
1Hr
3600s
----------------
1kW
1000W
-------------------
250mV
150mV
250V
-------------------
-------------------------
250mV
150mV
20A
-------------------
-------------------------
=
Vgn or Ign
PulseRateE
1.929
-----------------------------------
1.00441 0x404830==
4.096MHz
(MCLK/K)
----------------------------
PulseRateE
12,
PulseRateE
12,
4.096
3.05856
---------------------
1.929Hz2.583Hz=
Level
Duration
Figure 7. Voltage Sag Detect
2240 samples
(MCLK/K)/1024
-----------------------------------------
0.56 sec
=
EXAMPLE #2:
The required number of pulses per unit energy present
on E1
is specified to be 500 pulses per kWhr, given that
the line voltage is 250 Vrms and the line current is
20 Arms. In such a situation, the stated line voltage an d
current do not determine the appropriate PulseRateE
1,2
setting. To achieve full-scale readings in the instantaneous voltage and current registers, a 250 mV, DC-level signal is applied to the channel inputs.
As in example #1, the voltage and current channel gains
are 10x, and the voltage level at the channel inputs will
be 150 mV rms when the levels on the power lines are
250 V rms and 20 A rms. In order to achieve
500 pulse-per-kW Hr per unit-energy, the
PulseRateE
Register setting is determined using the
1,2
following equation:
sag level for more than half of the voltage sag duration
(see Figure 7).
To activate Voltage Sag detect, a voltage sag level must
be specified in the Voltage Sag Level Register
(VSAG
Level), and a voltage sag duration must be spec-
ified in the Voltage Sag Duration Register
(VSAG
Duration). The voltage sag level is specified as the
average of the absolute instantaneous voltage. Voltage
sag duration is specified in terms of ADC cycles.
Therefor, the PulseRateE
1.929 Hz. The PulseRateE
Register is approximately
1,2
Register cannot be set to
1,2
a frequency of exactly 1.929 Hz. The closest setting is
0x00003E = 1.9375 Hz.
To improve the accuracy, either gain register can be
programmed to correct for the round-off error. This value would be calculated as
If (MCLK/K) is not equal to 4.096 MHz, the
PulseRateE
Register must be scaled by a correction
1,2
factor of:
Therefore if (MCLK/K) = 3.05856 MHz the value of
PulseRateE
Register is
1,2
5.5 Voltage Sag-detect Feature
Status bit VSAG in the Status Register, indicates a voltage sag occurred in the power line voltage. For a voltage sag condition to be identified, the absolute value of
the instantaneous voltage must be less than the voltage
5.6 No Load Threshold
The CS5461A includes the LoadIntv (No Load Detection Interval) register and the LoadMin register to implement the no load threshold function. When the
accumulated energy measured within the time defined
by the LoadIntv register does not reach the value in the
LoadMin register, the pulse outputs will be disabled.
5.7 On-chip Temperature Sensor
The on-chip temperature sensor is designed to assist in
characterizing the measurement element over a desired
temperature range. Once a temperature characterization is performed, the temperature sensor can then be
utilized to assist in compensating for temperature drift.
Temperature measurements are performed during continuous conversions and stored in the TemperatureRegister. The Temperature Register (T) default is Celsius scale (
and Te mperature Offset Register (T
ues allowing for temperature scale conversions.
The temperature update rate is a function of the number
of ADC samples. With MCLK = 4.096 MHz and K = 1
the update rate is:
o
C). The Temperature Gain Register (T
) are constant val-
off
gain
)
DS661F319
CS5461A
T
offToff
T+2.737649 10
4
–
=
T
off
0.09511262.0–+2.737649 10
4
–
–0.09566–==
F
o
9
5
-- -
C
o
17.7778+=
TF
o
9
5
-- -
T
gain
TC
o
T
off
17.7778 2.737649 10
4
–
++=
Oscillator
Circuit
DGND
XIN
XOUT
C1
C1 =
22 pF
C2
C2 =
Figure 8. Oscillator Connection
The Cycle Count Register (N) must be set to a value
greater than one. Status bit TUP in the Status Register,
indicates when the Temperature Register is updated.
The Temperature Offset Register sets the zero-degree
measurement. To improve temperature measurement
accuracy, the zero-degree offset should be adjusted after the CS5461A is initialized. Temperature offset calibration is achieved by adjusting the Temperature OffsetRegister (T
) by the differential temperature ( T) mea-
off
sured from a calibrated digital thermometer and the
CS5461A temperature sensor. A one-degree adjustment to the Temperature Register (T) is achieved by
adding 2.737649x10
ter (T
if T
). Therefore,
off
= -0.0951126 and T=-2.0 (oC), then
off
-4
to the Temperature Offset Regis-
or 0xF3C168 (2’s compliment notation) is stored in the
Temperature Offset Register (T
off
).
To convert the Temperature Register (T) from a Celsius
scale (
o
C) to a Fahrenheit scale (oF) utilize the formula
A hardware reset is initiated when the RESET
pin is asserted with a minimum pulse width of 50 ns. The
RESET
input. Once the RESET
eight-XIN-clock-period delay is enabled
signal is asynchronous, with a Schmitt-trigger
pin is de-asserted, an
.
A software reset is initiated by writing the command of
0x80. After a hardware or sof tware reset, the internal
registers (some of which drive output pins) will be reset
to their default values. Status bit DRDY in the StatusRegister, indicates the CS5461A is in its active state
and ready to receive commands.
5.10 Power-down States
The CS5461A has two power-down states, stand-by
and sleep. In the stand-by state all circuitry except the
voltage reference and crystal oscillator is turned off. To
return the device to the active state a power-up command is sent to the device.
In sleep state all circuitry except the instruction decoder
is turned off. When the power-up command is sent to
the device, a system initialization is performed (see
Section 5.9 System Initialization on page 20).
5.11 Oscillator Characteristics
The XIN and XOUT pins are the input and output of an
inverting amplifier configured as an on-chip oscillator,
as shown in Figure 8. The oscillator circuit is designed
Applying the above relationship to the CS5461A temperature measurement algorithm
If T
= -0.09566 and T
off
scale, then the modified values are T
(0xF460E1) and T
gain
= 23.507 for a Celsius
gain
off
= 42.3132 (0x54A05E) for a
Fahrenheit scale.
5.8 Voltage Reference
The CS5461A is specified for oper ation with a +2.5 V
reference between the VREFIN and AGND pins. To utilize the on-chip 2.5 V reference, connect the VREFOUT
pin to the VREFIN pin of the device . The VREFIN pin
can be used to connect external filtering and/or references.
5.9 System Initialization
Upon powering up, the digital circuitry is h eld in reset
until the analog voltage reaches 4.0 V. At that time, an
eight-XIN-clock-period delay is enabled to allow the oscillator to stabilize. The CS5461A will then initialize.
= -0.0907935
to work with a quartz crystal. To reduce circuit cost, two
load capacitors C1 and C2 are integrated in the device,
from XIN to DGND, and XOUT to DGND. PCB trace
lengths should be minimized to reduce stray capacitance. To drive the device from an external clock
source, XOUT should be left unconnected while XIN is
driven by the external circuitry. There is an amplifier between XIN and the digital section which provides
CMOS-level signals. This amplifier works with sinusoi-
20DS661F3
CS5461A
dal inputs so there are no problems with slow edge
times.
The CS5461A can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must
be set such that the internal MCLK will run somewhere
between 2.5 MHz and 5 MHz. The K divider value is set
with the K[3:0] bits in the Configuration Register. As an
example, if XIN = MCLK = 15 MHz, and K is set to 5,
then DCLK is 3 MHz, which is a valid value for DCLK.
5.12 Event Handler
The INT pin is used to indicate that an internal error or
event has taken place in the CS5461A. Writin g a logic 1
to any bit in the Mask Register allows the corresponding
bit in the Status Register to activate the INT
terrupt condition is cleared by writing a logic 1 to the bi t
that has been set in the Status Register.
The behavior of the INT
and IINV bits of the Configuration Register.
IMODEIINVINT
00Active-low Level
01Active-high Level
10 Low Pulse
Table 3. Interrupt Configuration
pin is controlled by the IMODE
pin. The in-
Pin
IMODEIINVINT
11High Pulse
Table 3. Interrupt Configuration
If the interrupt output signal format is set for either falling
or rising edge, the duration of the INT
least one DCLK cycle (DCLK = MCLK/K).
Pin
pulse will be at
5.12.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
INITIALIZATION
1) All Status bits are cleared by writing 0xFFFFFF to
the Status Register.
2) The condition bits which will be used to generate
interrupts are then set to logic 1 in the Mask Register.
3) Enable interrupts.
INTERRUPT HANDLER ROUTINE
4) Read the Status Register.
5) Disable all interrupts.
6) Branch to the proper interrupt service routine.
7) Clear the Status Register by writing back the read
value in step 4.
8) Re-enable interrupts.
9) Return from interrupt service routine.
:
:
DS661F321
CS5461A
5.13 Serial Port Overview
The CS5461A incorporates a serial port transmit and receive buffer with a command decoder that interprets
one-byte (8 bits) commands as they are received. There
are four types of commands; instructions, synchronizing, register writes and register reads (See Section 5.14
Commands on page 23).
Instructions are one byte in length and will interrupt any
instruction currently executing. Instructions do not affect
register reads currently being transmitted.
Synchronizing commands are one byte in length and
only affect the serial interface. Synchronizing commands do not affect operations currently in progress.
Register writes must be followed by three bytes of data.
register reads can return up to four bytes of data.
Commands and data are transferred most-significant bit
(MSB) first. Figure 1 on page 11, defines the serial port
timing and required sequence necessary to write to and
read from the serial port receive and transmit buffer, respectively. While reading data from the serial port, commands and data can be simultaneously written. Starting
a new register read command while data is being read
will terminate the current read in progress. This is acceptable if the remainder of the current read dat a is no t
needed. During data reads, the serial port requires input
data. If a new command and data is not sent, SYNC0 or
SYNC1 must be sent.
5.13.1 Serial Port Interface
The serial port interface is a “4-wire” synchronous serial
communications interface. The in terface is enabled to
start excepting SCLKs when CS
ed. SCLK (Serial bit-clock) is a Schmitt-trigger input that
is used to strobe the data on SDI (Serial Data In) into the
receive buffer and out of the transmit buffer onto SDO
(Serial Data Out).
If the serial port interface becomes unsynchronized with
respect to the SCLK input, any attempt to clock valid
commands into the serial interface may result in unexpected operation. The serial port interface must then be
re-initialized by one of the following actions:
-Drive the CS
-Hardware Reset (drive RESET
least 10 µs).
-Issue the Serial Port Initialization Sequence,
which is 3 (or more) SYNC1 command bytes
(0xFF) followed by one SYNC0 command byte
(0xFE).
If a resynchronization is necessary, it is best to re-initialize the part either by hardware or software reset (0x80),
as the state of the part may be unknown.
pin high, then low.
(Chip Select) is assert-
pin low, for at
22DS661F3
CS5461A
5.14 Commands
All commands are 8-bits in length. Any byte that is not listed in this section is invalid. Commands that write to registers must be followed by 3 bytes of data. Commands that read data can be chained with other commands (e.g., while
reading data, a new command can be sent which can execute during the original read). All commands except register reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands.
5.14.1 Start Conversions
B7B6B5B4B3B2B1B0
1110C3C200
Initiates acquiring measurements and calculating results. The device has three modes of acquisition.
C[3:2]Modes of acquisition/measurement
00 = Perform a single computation cycle
01 = Not Used
10 = Perform continuous computation cycles
11 = Perform continuous computation cycles with APF enabled on the other channel
5.14.2 SYNC0 and SYNC1
B7B6B5B4B3B2B1B0
1111111SYNC
The serial port can be initialized by asserting CS or by sending three or more consecutive SYNC1 commands followed by a SYNC0 command. The SYNC0 or SYNC1 can also be sent while sending data out.
SYNC 0 = Last byte of a serial port re-initialization sequence.
1 = Used during reads and serial port initialization.
5.14.3 Power-Up/Halt
B7B6B5B4B3B2B1B0
10100000
If the device is powered-down, Power-Up/Halt will initiate a power on reset. If the part is already powered-on, all
computations will be halted.
5.14.4 Power-down and Software Reset
B7B6B5B4B3B2B1B0
100S1S0000
To conserve power the CS5461A has two power-down states. In stand- by state all circuitry, except the analog/digital
clock generators, is turned off. In the sleep state all circuitry, except the instruction decoder, is turned off. Bringing
the CS5461A out of sleep state requires more time than out of stand-by state, because of the extra time needed to
re-start and re-stabilize the analog oscillator.
S[1:0]Power-down state
00 = Software Reset
01 = Halt and enter stand-by power saving state. This stat e allo ws qu ick po wer- on
10 = Halt and enter sleep power saving state.
11 = Reserved
DS661F323
CS5461A
5.14.5 Register Read/Write
B7B6B5B4B3B2B1B0
0W/R
The Read/Write informs the command decoder that a register access is required. During a re ad operation, the addressed register is loaded into an output buffer and clocked out by SCLK. During a write operation, the data is
clocked into an input buffer and transferred to the addressed register upon completion of the 24
RA4RA3RA2RA1RA00
th
SCLK.
W/R
Write/Read control
0 = Read
1 = Write
RA[4:0]Register address bits (bits 5 through 1) of the read/write command.
Note: For proper operation, do not attempt to write to unspecified registers.
24DS661F3
CS5461A
5.14.6 Calibration
B7B6B5B4B3B2B1B0
110CAL4 CAL3 CAL2 CAL1 CAL0
The CS5461A can perform system calibrations. Proper input signals must be applied to the current and voltage
channel before performing a designated calibration.
CAL[4:0]* Designates calibration to be performed
01001 = Current channel DC offset
01010 = Current channel DC gain
01101 = Current channel AC offset
01110 = Current channel AC gain
10001 = Voltage channel DC offset
10010 = Voltage channel DC gain
10101 = Voltage channel AC offset
10110 = Voltage channel AC gain
11001 = Current and Voltage channel DC offset
11010 = Current and Voltage channel DC gain
11101 = Current and Voltage channel AC offset
11110 = Current and Voltage channel AC gain
*Values for CAL[4:0] not specified should not be used.
DS661F325
CS5461A
6. REGISTER DESCRIPTION
1. “Default” => bit status after power-on or reset
2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits .
6.1 Configuration Register
Address: 0
2322212019181716
PC6PC5PC4PC3PC2PC1PC0
15141312111098
EWAIMODEIINVEPPEOPEDP
76543210
AL TVHPFIHPFiCPUK3K2K1K0
Default = 0x000001
PC[6:0]Phase compensation. A 2’s complement number which sets a delay in the voltage channe l rel-
ative to the current channel. When MCLK = 4.096 MHz and K = 1, the phase adjustment range
is approximately 2.8 degrees with each step approxima te ly 0.04 de grees ( assumin g a p ower
line frequency of 60 Hz). If (MCLK/K) is not 4.096 MHz, the values for the range and step size
should be scaled by the factor 4.096 MHz / (MCLK/K). Default setting is 0000000 = 0.0215 degree phase delay at 60 Hz (when MCLK = 4.096 MHz).
Igain
IgainSets the gain of the current PGA.
0 = Gain is 10x (default)
1 = Gain is 50x
EWAAllows the E1
0 = Normal outputs (default)
1 = Only the pull-down device of the E1
IMODE, IINVInterrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
iCPUInverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active du rin g the samp le edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising-edge logic
K[3:0]Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. A value of “0000” will set K to 16 (not zero). K = 1 at reset.
6.2 Current and Voltage DC Offset Register ( I
DCoff ,VDCoff
)
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
MSBLSB
0
)2-12
-(2
-2
-3
2
-4
2
-5
2
-6
2
-7
2
.....
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
Default = 0x000000
The DC Offset registers (I
DCoff,VDCoff
) are initialized to 0.0 on reset. When DC Offset calibration is performed, the
register is updated with the DC offset measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system offset compensation. The value is represented in two's complement notation and in the range of -1.0 I
DCoff
, V
1.0, with the binary point to the
DCoff
right of the MSB.
6.3 Current and Voltage Gain Register ( I
gn ,Vgn )
Address: 2 (Current Gain); 4 (Voltage Gain)
MSBLSB
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
.....
-16
2
-17
2
-18
2
-19
2
-20
2
-21
2
Default = 0x400000 = 1.000
The gain registers (I
gn,Vgn)
are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
the register is updated with the gain measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system gain compensation. The value is in the
range 0.0 I
< 3.9999, with the binary point to the right of the second MSB.
gn,Vgn
-23
2
-22
2
6.4 Cycle Count Register
Address: 5
MSBLSB
23
2
DS661F327
22
2
21
2
20
2
19
2
18
2
17
2
16
2
.....
6
2
5
2
4
2
3
2
2
2
1
2
0
2
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024N). A one second computational cycle period occurs wh en
MCLK = 4.096 MHz, K = 1, and N = 4000.
CS5461A
6.5 PulseRateE
Register
1,2
Address: 6
MSBLSB
18
2
17
2
16
2
15
2
14
2
13
2
12
2
11
2
.....
1
2
0
2
-1
2
-2
2
-3
2
-4
2
Default = 0xFA000 = 32000.00 Hz
PulseRateE
sets the frequency of the E1 and/or E2 pulses. The smallest valid frequency is 2-4 with 2-5 incre-
1,2
mental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value
is represented in unsigned notation, with the binary point to the right of bit 5.
6.6 Instantaneous Current, Voltage and Power Registers ( I , V , P )
I and V contain the instantaneous measured values for current and voltage, respectively. The instantaneous
voltage and current samples ar e multiplied to obtain Instantaneous Power (P). The value is represen ted in two's
complement notation and in the range of -1.0 I, V, P 1.0, with the binary point to the right of the MSB.
6.7 Active (Real) Power Registers ( P
Address: 10
-2
-3
2
-4
2
-5
2
-6
2
Active
-7
2
.....
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
)
-5
2
-23
2
MSBLSB
0
)2-12
-(2
-2
-3
2
-4
2
-5
2
-6
2
-7
2
.....
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
The instantaneous power is averaged over each computation cycle (N conversions) to compute Active Power
(P
). The value is represented in two's complement n otation a nd in th e ra nge of -1.0 P
Active
1.0, with the
Active
binary point to the right of the MSB.
6.8 I
MSBLSB
2
and V
RMS
Address: 11 (I
-1
I
RMS
-2
2
and V
Registers ( I
RMS
); 12 (V
RMS
2
RMS
-3
-4
2
contain the Root Mean Square (RMS) value of I and V, calculated over each computation cycle.
RMS
-5
2
)
RMS
-6
2
, V
RMS
-7
2
)
-8
2
.....
-18
2
-19
2
The value is represented in unsigne d binary notation and in the range of 0.0 I
-20
2
2
RMS,VRMS
-21
-22
2
-23
2
1.0, with the binary
point to the left of the MSB.
6.9 Power Offset Register ( P
off
)
Address: 14
MSBLSB
0
)2-12
-(2
-2
-3
2
-4
2
-5
2
-6
2
-7
2
.....
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
Default = 0x000000
-23
2
-24
2
-23
2
Power Offset (P
) is added to the instantaneous power being accumulated in the P
off
register and can be
active
used to offset contributions to the energy result that are caused by undesirab le sources of energy that are inherent in the system. The value is represented in two's complement notation and in the range of -1.0 P
off 1.0,
with the binary point to the right of the MSB.
28DS661F3
CS5461A
6.10 Status Register and Mask Register ( Status , Mask )
Address: 15 (Status); 26 (Mask)
2322212019181716
DRDYCRDYIORVOR
15141312111098
IRORVROREOR
76543210
TUPTODVODIODLSDVSAG
Default = 0x000001 (Status Register), 0x000000 (Mask Register)
The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit
to reset. Writing a '0' to a bit will not change it’s current state.
IC
The Mask Register is used to control the activation of the INT
corresponding bit in the Status Register to activate the INT
pin. Placing a logic '1' in a Mask bit will allow the
pin when the status bit is asserted.
DRDYData Ready. During conversions, this bit will indicate the end of computation cycles. For cali-
brations, this bit indicates the end of a calibration sequence.
CRDYConversion Ready. Indicates a new conversion is ready. This will occur at the output word rate.
IORCurrent Out of Range. Set when the Instantaneous Current Register overflows.
VORVoltage Out of Range. Set when the Instantaneous Voltage Register overflows.
IRORI
VRORV
EOREnergy Out of Range. Set when P
Out of Range. Set when the I
RMS
Out of Range. Set when the V
RMS
Register overflows.
RMS
Register overflows.
RMS
ACTIVE
overflows.
TUPTemperature Updated. Indicates the Temperature Register has updated.
TODModulator oscillation detected on the temperature channel. Set when the modulator oscillates
due to an input above full scale.
VOD (IOD)Modulator oscillation detected on the voltage (current) channel. Set when the modulator oscil-
lates due to an input above full scale. The level at which the modulator oscillates is significantly
higher than the voltage (current) channel’s differential input voltage range.
Note:The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the
power line. This event should not be confused with a DC overload situatio n at the inputs, when the IOD and VOD bits will re-assert themselves even after being cleared,
multiple times.
LSDLow Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh-
old (PMLO), with respect to AGND pin. The LSD bit cannot be reset until the voltage at PFMON
pin rises back above the high-voltage threshold (PMHI).
VSAGIndicates a voltage sag has occurred. See Section 5.5 Voltage Sag-detect Feature on page 19.
IC
Invalid Command. Normally logic 1. Set to logic 0 if an invalid command is received or the Sta-
tus Register has not been successfully read.
DS661F329
CS5461A
6.11 Current and Voltage AC Offset Register ( V
ACoff
, I
ACoff
)
Address: 16 (Current AC Offset); 17 (Voltage AC Offset)
MSBLSB
0
)2-12
-(2
-2
-3
2
-4
2
-5
2
-6
2
-7
2
.....
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
Default = 0x000000
The AC Offset Registers (V
ACoff, IACoff)are initialized to zero on reset, allowing for u ncalibrated normal operation.
AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cycles (where
N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration. These values
may be read and stored for future system AC offset compensation. The value is represented in two's complement notation and in the range of -1.0 V
ACoff, IACoff 1.0, with the binary point to the right of the MSB.
6.12 PulseRateE3 Register
Address: 18
MSBLSB
18
2
17
2
16
2
15
2
14
2
13
2
12
2
11
2
.....
1
2
0
2
-1
2
-2
2
-3
2
-4
2
Default = 0xFA0000 = 32000.00 Hz
PulseRateE
sets the frequency of the E3 pulses. The register’s smallest valid frequency is 2-4 with 2-5 incre-
3
mental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value
is represented in unsigned notation, with the binary point to the right of bit #5.
-23
2
-5
2
6.13 Temperature Register ( T )
Address: 19
MSBLSB
7
)262
-(2
T contains measurements from the on-chip temperature sensor. Measurements are performed during continuous conversions, with the default the Celsius scale (
and in the range of -128.0 T 128.0, with the binary point to the right of the eighth MSB.
6.14 System Gain Register ( SYS
Address: 20
MSBLSB
1
-(2
)202
Default = 0x500000 = 1.25
System Gain (SYS
ulator due to temperature can be fine adjusted by changing the system gain. The value is represented in two's
complement notation and in the range of -2.0 SYS
MSB.
5
-1
4
2
-2
2
Gain) determines the one’s density of the channel measurements. Small changes in the mod-
3
2
-3
2
2
2
Gain
-4
2
1
2
0
.....
2
o
C). The value is represented in two's complement notation
-10
2
-11
2
-12
2
-13
2
-14
2
2
)
-5
2
-6
2
.....
Gain 2.0, with the binary point to the right of the second
-16
2
-17
2
-18
2
-19
2
-20
2
2
-15
-21
-16
2
-22
2
30DS661F3
CS5461A
PulseWidth
MCLK
K1024
-------------------------------------------- -
6.15 Pulsewidth Register ( PW )
Address: 21
MSBLSB
23
2
22
2
21
2
20
2
19
2
18
2
Default = 0x000200 = 512 sample periods
17
2
16
2
.....
6
2
5
2
4
2
3
2
2
2
1
2
0
2
PW sets the pulsewidth of E1
and E2 pulses in Alternate Pulse and Mechanical Counter format. The width is a
function of number of sample periods. The default corresponds to a pulsewidth of
512 samples/[(MCLK/K)/1024] = 128 msec with MCLK = 4.096 MHz and K = 1. The value is represented in unsigned notation.
The PulseWidth register sets the pulse width of E3
E3
pulse width =
The range of this register is from 1 to 8388607.
6.17 Voltage Sag Duration Register ( VSAG
Address: 23
MSBLSB
0
22
2
21
2
20
2
19
2
18
2
17
2
16
2
.....
6
2
5
2
4
2
3
2
2
2
1
2
pulses in units of 1/OWR.
.....
)
6
2
5
2
4
2
3
2
2
2
1
2
Duration
21
2
20
2
19
2
18
2
17
2
16
2
0
2
0
2
Default = 0x000000
Voltage Sag Duration (VSAG
termine a voltage level sag event (VSAG
)defines the number of instantaneous voltage measurements utilized to de-
Duration
). Setting this register to zero will disable Voltage Sag-detect. The
LEVEL
value is represented in unsigned notation.
6.18 Voltage Sag Level Register ( VSAG
Level
)
Address: 24
MSBLSB
0
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
.....
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
2
Default = 0x000000
Voltage Sag Level (VSAG
) defines the voltage level that the magnitude of input sam ples, averaged over the
Level
sag duration, must fall below in order to register a sag condition. This value is represented in unsigned notation
and in the range of 0 VSAG
1.0, with the binary point to the right of the MSB.
Level
DS661F331
CS5461A
6.19 No Load Threshold Interval Register ( LoadIntv)
Address: 25
MSBLSB
23
2
6.20 No Load Threshold ( LoadMin )
MSBLSB
-(2
22
2
21
2
20
2
19
2
18
2
17
2
16
2
.....
6
2
5
2
4
2
3
2
2
2
1
2
Default = 0x000000 = No load threshold feature disabled
LoadMin determines the duration or interval of the no load detection window in units of 1/OWR. The range is
from 1 to 16777215.
Address: 27
0
)2-12
-2
-3
2
-4
2
-5
2
-6
2
-7
2
.....
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
Default = 0x000000 = No load threshold feature disabled
LoadMin sets the no load threshold value. Lo ad M in is a two’s complement value in the range of
-1.0 LoadMin 1.0 with the binary point to the right of the MSB. Negative values are not allowed.
0
2
-23
2
32DS661F3
CS5461A
6.21 Control Register
Register Address: 28
2322212019181716
15141312111098
FACEACSTOP
76543210
MECHINTODNOCPUNOOSCSTEP
Default = 0x000000
FACDetermines if anti-creep is enabled for pulse output E3.
or E2 becomes active low pulses with an output frequency proportional to the active power
0 = Normal (default) or Stepper Motor Format
1 = Mechanical Counter Format, also ALT = 0
INTODConverts INT output pin to an open drain output.
0 = Normal (default)
1 = Open drain
NOCPUSaves power by disabling the CPUCLK pin.
0 = Normal (default)
1 = Disables CPUCLK
NOOSCSaves power by disabling the crystal oscillator.
0 = Normal (default)
1 = Oscillator circuit disabled
STEPStepper Motor Format, E1
and E2 becomes active low pulses with an output frequency proportional to the active power
0 = Normal Format (default)
1 = Stepper Motor Format, also MECH = 0 and ALT = 0
6.22 Temperature Gain Register ( T
Gain
)
Address: 29
MSBLSB
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
2
.....
-11
2
-12
2
-13
2
-14
2
-15
2
-16
2
-17
2
Default = 0x2F02C3 = 23.5073471
Sets the temperature channel gain. Temperature gain (T
other. The Celsius scale (
0 T
128, with the binary point to the right of the seventh MSB.
Gain
o
C) is the default. Values are represented in unsigned notation and in the range of
) is utilized to convert from one temperature scale to an-
Gain
DS661F333
CS5461A
6.23 Temperature Offset Register ( T
off
)
Address: 30
MSBLSB
0
)2-12
-(2
-2
-3
2
-4
2
-5
2
-6
2
-7
2
.....
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
Default = 0xF3D35A = -0.0951126
Temperature offset (T
are represented in two's complement notation and in the range of -1.0 T
) is used to remove the temperature channel’s offset at the zero degr ee reading. Values
off
off 1.0, with the binary point to the
right of the MSB.
6.24 Apparent Power Register ( S )
Address: 31
MSBLSB
-1
2
-2
2
Apparent power (S) is the product of the V
-3
2
-4
2
-5
2
-6
2
-7
2
RMS
-8
2
and I
.....
. The value is represented in unsigned binary notation
RMS
-18
2
-19
2
and in the range of 0.0 S 1.0, with the binary point to the left of the MSB.
-20
2
-21
2
-22
2
-23
2
-23
2
-24
2
34DS661F3
7. SYSTEM CALIBRATION
Figure 9. Calibration Data Flow
In
Modulator
+
X
to V*, I* Registers
Filter
N
V
RMS
*, I
RMS
*
Registers
DC Offset*
Gain*
0.6
+
+
+
* Denotes readable/writable register
N
+
X
N
Inver se
X
-1
RMS
AC O ffs e t*
N
X
-1
+
+
-
XGAIN
+
-
External
Connections
0V
+
-
AIN+
AIN-
CM
+
-
Figure 10. System Calibration of Offset.
CS5461A
7.1 Channel Offset and Gain Calibration
The CS5461A provides digital DC offset and gain compensation that can be applied to the instantaneous voltage and current measurements, and AC offset
compensation to the voltage an d current RMS calculations.
Since the voltage and current channels have independent offset and gain registers, system offset and/or
gain can be performed on either channel without the
calibration results from one channel affecting the other.
The computational flow of the calibration sequences are
illustrated in Figure 9. The flow applies to both the voltage channel and current channel.
7.1.1 Calibration Sequence
The CS5461A must be operating in its active state and
ready to accept valid commands. Refer to Section 5.14
Commands on page 23. The calibration algorithms are
dependent on the value N in the Cycle Count Register
(see Figure 9). Upon completion, the results of the calibration are available in their corresponding register. The
DRDY bit in the Status Register will be set. If the DRDY
bit is to be output on the INT
Mask Register must be set. The initial values stored in
the AC gain and offset registers do affect the calibration
results.
7.1.1.1 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines
the number of conversions performed by the CS5461A
during a given calibration sequence. For DC offset and
gain calibrations, the calibration sequence takes at least
N + 30 conversion cycles to complete. For AC offset
pin, then DRDY bit in the
calibrations, the sequence takes at least 6N + 30 ADC
cycles to complete, (about 6 computation cycles). As N
is increased, the accuracy of calibration results will increase.
7.1.2 Offset Calibration Sequence
For DC- and AC offset calibrations, the VIN pins of the
voltage and IIN pins of the current channels should be
connected to their ground-reference level.
See Figure 10.
The AC offset registers must be set to the default
(0x000000).
7.1.2.1 DC Offset Calibration Sequence
Channel gain should be set to 1.0 when performing DC
offset calibration. Initiate a DC offset calibration. The DC
offset registers are updated with the negative of the average of the instantaneous samples taken over a computational cycle. Upon completion of the DC offset
calibration the DC offset is stored in the correspo nding
DC offset register. The DC offset value will be added to
each instantaneous measurement to cancel out the DC
DS661F335
CS5461A
+
-
+
-
External
Connections
IN+
IN-
CM
+
-
+
-
XGAIN
Reference
Signal
Figure 11. System Calibration of Gain
V
RMS
Register =
230
/
x
1
/
250
0.65054
250 mV
230 mV
0 V
-230 mV
-250 mV
0.9999...
0.92
-0.92
-1.0000...
V
RMS
Register =0.600000
250 mV
230 mV
0 V
-230 mV
-250 mV
0.84853
-0.84853
Before AC Gain Calibration (Vgn Register = 1)
After AC Gain Calibration (Vgn Register changed to approx. 0.9223)
Instantaneous Voltage
Register Values
Instantaneous Voltage
Register Values
Sinewave
Sinewave
0.92231
-0.92231
INPUT
SIGNAL
INPUT
SIGNAL
Figure 12. Example of AC Gain Calibration
V
RMS
Register =
230
=0.92
250 mV
230 mV
0 V
-250 mV
0.9999...
0.92
-1.0000...
V
RMS
Register =0.600000
250 mV
230 mV
0 V
-250 mV
0.6000
Before AC Gain Calibration (Vgain Register = 1)
After AC Gain Calibration (Vgain Register changed to approx. 0.65217)
Instantaneous Voltage
Register Values
Instantaneous Voltage
Register Values
DC Signal
DC Signal
0.65217
-0.65217
INPUT
SIGNAL
INPUT
SIGNAL
250
Figure 13. Another Example of AC Gain Calibration
component present in the system during conversion
commands.
7.1.2.2 AC Offset Calibration Sequence
Corresponding offset registers I
should be cleared prior to initiating AC offset calibrations. Initiate an AC offset calibration. The AC offset registers are updated with an offset value that reflects the
RMS output level. Upon completion of the AC offset calibration the AC offset is stored in the corresponding AC
offset register. The AC offset register value is subtracted from each successive V
RMS
and I
and/or V
ACoff
RMS
ACoff
calculation.
7.1.3 Gain Calibration Sequence
When performing gain calibrations, a reference signal
should be applied to the VIN pins of the voltage and
IIN pins of the current channels that represents the desired maximum signal level. Figure 11 shows the basic
setup for gain calibration.
A typical rms calibration value which allows for reasonable over-range margin would be 0.6 or 60% of the voltage and current channel’s maximum input voltage level.
Two examples of AC gain calibration and the updated
digital output codes of the channel’s instantaneous data
registers are shown in Figures 12 and 13. Figure 13
For gain calibrations, there is an absolute limit on the
RMS voltage levels that are selected for the gain-calibration input signals. The maximum value that the gain
registers can attain is 4. Therefore, if the signal level of
the applied input is low enough that it causes the
CS5461A to attempt to set either gain register higher
than 4, the gain calibration result will be invalid and all
CS5461A results obtained while performing measurements will be invalid.
If the channel gain registers are initially set to a gain other then 1.0, AC gain calibration should be used.
7.1.3.1 AC Gain Calibration Sequence
The corresponding gain regist er should be set to 1.0,
unless a different initial gain value is desired. Initiate an
AC gain calibration. The AC gain calibration algorithm
computes the RMS value of the reference signal applied
to the channel inputs. The RMS register value is then divided into 0.6 and the quotient is stored in the corresponding gain register. Each instantaneous
measurement will be multiplied by its corresponding AC
gain value.
36DS661F3
shows that a positive (or negative), DC-level signal can
be used even though an AC gain calibration is being ex-
CS5461A
ecuted. However, an AC signal should no t be used for
DC gain calibration.
7.1.3.2 DC Gain Calibration Sequence
Initiate a DC gain calibration. The corresponding gain
register is restored to default (1.0). The DC gain calibration algorithm averages the channel’s instantaneous
measurements over one computation cycle (N samples). The average is then divided into 1.0 and the quotient is stored in the corresponding gain register
After the DC gain calibration, the instantaneous register
will read at full-scale whenever the DC level of the input
signal is equal to the level of the DC calibration signal
applied to the inputs during the DC gain calibration.The
HPF option should not be enabled if DC gain calibration
is utilized.
7.1.4 Order of Calibration Sequences
1. If the HPF option is enab led, then any dc component that may be present in the selected signal path
will be removed and a DC offset calibration is not required. However, if the HPF option is disabled the
DC offset calibration sequence should be performed.
When using high-pass filters, it is recommended
that the DC offset register for the corresponding
channel be set to zero. When performing DC offset
calibration, the corresponding gain channel should
be set to one.
2. If an ac offset exist, in the V
then the AC offset calibrati on sequence should be
performed.
3. Perform the gain calibration sequence.
4. Finally, if an AC offset calibration was performed
(step 2), then the AC offset may need to be adjusted
to compensate for the change in gain (step 3). This
RMS
or I
calculation,
RMS
can be accomplished by restoring zero to the AC
offset register and then perform an AC offset calibration sequence. The adjustment could also be
done by multiplying the AC offset register value that
was calculated in step 2 by the gain calculated in
step 3 and updating the AC offset register with the
product.
7.2 Phase Compensation
The CS5461A is equipped with phase compensation to
cancel out phase shifts introduced by the measurement
element. Phase Compensation is set by bits PC[6:0] in
the Configuration Register.
The default value of PC[6:0] is zero. With
MCLK = 4.096 MHz and K = 1, the phase compensation has a range of 2.8 degrees when the input sign als
are 60 Hz. Under these conditions, each step of the
phase compensation register (value of one LSB) is approximately 0.04 degrees. For values of MCLK other
than 4.096 MHz, the range and step size should be
scaled by 4.096 MHz/(MCLK/K). For power-line frequencies other than 60Hz, the values of the range and
step size of the PC[6:0] bits can be determined by converting the above values from angular measurement
into time-domain (seconds), and then computing the
new range and step size (in degrees) with resp ect to the
new line frequency.
7.3 Active Power Offset
The Power Offset Register can be used to offset system
power sources that may be resident in the system, but
do not originate from the power-line signal. These
sources of extra energy in the system contribute undesirable and false offsets to the power and energy measurement results. After determining the amount of stray
power, the Power Offset Register can be set to cancel
the effects of this unwanted energy.
DS661F337
8. AUTO-BOOT MODE USING E2PROM
Figure 14. Typical Interface of E2PROM to CS5461A
CS5461A
EEPROM
EOUT1
EOUT2
MODE
SCLK
SDI
SDO
CS
SCK
SO
SI
CS
Connector to Calibrator
VD+
5 K
5 K
Mech. Counter
Stepper Motor
or
When the CS5461A MODE pin is asserted (logic 1), the
CS5461A auto-boot mode is enabled. In auto-boot
mode, the CS5461A downloads the required commands and register data from an external serial
2
E
PROM, allowing the CS5461A to begin performing
energy measurements.
8.1 Auto-Boot Configuration
A typical auto-boot serial connection between the
CS5461A and a E
auto-boot mode, the CS5461A’s CS
figured as outputs. The CS5461A asserts CS
a clock on SCLK, and sends a read command to the
2
E
PROM on SDO. The CS5461A reads the user-specified commands and register data presented on the SDI
pin. The E
2
PROM’s programmed data is utilized by the
CS5461A to change the designated registers’ default
values and begin registering energy.
2
PROM is illustrated in Figure 14. In
and SCLK are con-
, provides
CS5461A
operation, when the auto-boot initialization sequence is
running. Any of the valid commands can be used.
8.2 Auto-Boot Data for E2PROM
Below is an example code set for an auto-boot sequence. This code is written into the E
er. The serial data for such a sequence is shown below
in single-byte, hexidecimal notation:
- 40 00 00 61
Write Configuration Register, turn high-pass filters
on, set K=1.
- 44 7F C4 A9
Write value of 0x7FC4A9 to Current Gain
Register.
- 48 FF B2 53
Write value of 0xFFB253 to Voltage Gain
Register.
- 4C 00 7D 00
Set PulseRateE
Register to 1000 Hz.
1,2
- 74 00 00 04
Unmask bit #2 (LSD) in the Mask Register).
- E8
Start continuous conversions
- 78 00 01 00
Write STOP bit to Control Register, to terminate
auto-boot initialization sequence.
2
PROM by the us-
Figure 14 also shows the external connections that
would be made to a calibrator device, such as a PC or
custom calibration board. When the metering system is
installed, the calibrator would be used to control calibration and/or to program user-specified commands and
calibration values into the E
2
PROM. The user-specified
commands/data will determine the CS5461A’s exact
38DS661F3
8.3 Suggested E2PROM Devices
Several industry-standard, serial E2PROMs that will
successfully run auto-boot with the CS5461A are listed
below:
•Atmel AT25010, AT25020 or AT25040
•National Semiconductor NM25C040M8 or NM25020M8
•Xicor X25040SI
These types of serial E2PROMs expect a specific 8-bit
command (00000011) in order to perform a memory
read. The CS5461A has been hardware progra mmed to
transmit this 8-bit command to the E
ginning of the auto-boot sequence.
2
PROM at the be-
9. BASIC APPLICATION CIRCUITS
VA+VD+
CS5461A
0.1 µF470 µF
500
470 nF
500
N
R
1
R
2
10
14
VIN+
9
VIN-
IIN-
10
15
16
IIN+
PFMON
CPUCLK
XOUT
XIN
Optional
Clock
Source
Serial
Data
Interface
RESET
17
2
1
24
19
CS
7
SDI
23
SDO
6
SCLK
5
INT
20
E1
0.1 µF
VREFIN
12
VREFOUT
11
AGNDDGND
134
3
4.096 MHz
0.1 µF
10 k
5k
L
R
Shunt
R
V-
R
I-
R
I+
ISOLATION
120 VAC
Mech. Counter
Stepper Motor
or
22
21
C
I-
C
I+
C
Idiff
C
V-
C
V+
C
Vdiff
E2
Note:
Indicates common (floating) return.
Figure 15. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line)
Figure 15 shows the CS5461A configured to measure
power in a single-phase, 2-wire syste m while op erat ing
in a single-supply configuration. In this diagram, a shunt
resistor is used to sense the line current and a voltage
divider is used to sense the lin e voltage. In this type of
shunt resistor configuration, the common-mode level of
the CS5461A must be referenced to the line side of the
power line. This means that the common -mode potential of the CS5461A will track the high-voltage levels, as
well as low-voltage levels, with respect to earth ground
potential. Isolation circuitry is re quired when an earthground-referenced communication interface is connected.
CS5461A
Figure 16 shows the same single-phase, two-wire sys-
tem with complete isolation from the power lines. This
isolation is achieved using three transformers: a general
purpose transformer to supply the on-board DC power;
a high-precision, low-impedance voltage transformer
with very little roll-off/phase-delay, to measure voltage;
and a current transformer to sense the line current.
Figure 17 shows a single-phase, 3-wire system. In
many 3-wire residential power systems within the United States, only the two line terminals are available (neutral is not available). Figure 18 shows the CS5461A
configured to meter a three-wire system with no neutral
available.
Notes: 3. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch
and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
4. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in
excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more
than 0.07 mm at least material condit ion.
5. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
42DS661F3
CS5461A
11. ORDERING INFORMATION
ModelTemperaturePackage
CS5461A-ISZ (lead free)-40 to +85 °C24-pin SSOP
12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model NumberPeak Reflow TempMSL Rating*Max Floor Life
CS5461A-ISZ (lead free)260 °C37 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS661F343
CS5461A
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and it s su bsi d iari e s (“Ci r ru s”) be li eve t hat the inf or mati o n con tai n ed in th i s docu ment i s acc urate and reliable. Ho we v er , t h e inf o rmat io n i s subj e ct
to change without noti ce and is provi ded “AS I S” with out warran ty of any kind ( express or implied ). Cust omers are a dvised to obtain the latest version of relevant
information to verify, before placing orders, tha t inform atio n bei ng relied on is curr ent and com plete. Al l prod ucts are sold s ubject to the ter ms and co nditio ns of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights o f third
parties. This document is the property of Ci rrus and by furnishing this information , Cir rus gr an ts no li cen se, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for ge neral distribution, advertising or promotional pu rp ose s , or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR W ARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SU CH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF C IRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRI BUTORS AND OTHER A GENTS FROM ANY AND ALL LIAB ILITY, INCLUDING
ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Lo gic logo designs are trademarks of C irrus Logic, Inc. All other brand and product names in this document may be tra dem a rks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
13. REVISION HISTORY
RevisionDateChanges
A1DEC 2004Advance Release
PP1FEB 2005Initial Preliminary Release
F1AUG 2005Final version Updated with most-recent characterization data. MSL data added.
F2APR 2008Added LoadIntv, LoadMin, & PulseWidth registers. Added APF function.
F3APR 2011Removed lead-containing (Pb) device ordering information.
44DS661F3
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