Cirrus Logic CS5461A User Manual

CS5461A

VA+ VD+

IIN+

IIN-

VIN+

VIN-

VREFIN

VREFOUT

AGND

XIN XOUT CPUCLK DGND

CS

SDO

SDI

SCLK
INT

Voltage

Reference

System

Clock

/K

Clock

Generator

Serial

Interface

E-to-F

Power

Monitor

PFMON

x1

RESET

Digital

Filter

Calibration

MODE

Power

Calculation

Engine

4th Order 

Modulator

2nd Order 

Modulator

Temperature

Sensor

Digital

Filter

PGA

HPF

Option

HPF

Option

E1
E2
E3

x10

Single Phase, Bi-directional Power/Energy IC

Features

• Energy Data Linearity: ±0.1% of Reading over
1000:1 Dynamic Range

• On-chip Functions:

- Instantaneous Voltage, Current, and Power

- I

and V

RMS

- Energy-to-pulse Conversion for Mechanical
Counter/Stepper Motor Drive

- System Calibrations and Phase Compensation

- Temperature Sensor

- Voltage Sag Detect

• Meets Accuracy Spec for IEC, ANSI, & JIS.

• Low Power Consumption

• Current Input Optimized for Sense Resistor.

• GND-referenced Signals with Single Supply

• On-chip 2.5 V Reference (25 ppm/°C typ)

• Power Supply Monitor

• Simple Three-wire Digital Serial Interface

• “Auto-boot” Mode from Serial E

• Power Supply Configurations:

VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V

, Apparent and Active (Real) Power

RMS

2

PROM.

Description

The CS5461A is an integrated power measure­ment device which combines two 
analog-to-digital converters, power calculation
engine, energy-to-frequency converter, and a
serial interface on a single chip. It is designed to
accurately measure instantaneous current and
voltage, and calculate V
neous power, apparent power, and active power
for single-phase, 2- or 3-wire power metering
applications.

The CS5461A is optimized to interface to shunt
resistors or current transformers for current mea­surement, and to resistive dividers or potential
transformers for voltage measurement.

The CS5461A features a bi-directional serial in­terface for communication with a processo r, an d
a programmable energy-to-pulse output func­tion. Additional features include on-chip
functionality to facilitate system-level calibration,
temperature sensor, voltage sag detection, and
phase compensation.

ORDERING INFORMATION:

See Page 43.

RMS

, I

, instanta-

RMS

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2011

(All Rights Reserved)

APR ‘11

DS661F3

CS5461A

TABLE OF CONTENTS

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.1 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.2 Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.3 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.4 Linearity Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.1.1 Voltage Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.1.2 Current Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.2 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.3 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.4 Energy Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.4.1 Normal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.4.2 Alternate Pulse Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5.4.3 Mechanical Counter Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5.4.4 Stepper Motor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5.4.5 Pulse Output E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.4.6 Anti-creep for the Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.4.7 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.5 Voltage Sag-detect Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.6 No Load Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.7 On-chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.8 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5.9 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5.10 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5.11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5.12 Event Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.12.1 Typical Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.13 Serial Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.13.1 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.14 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

6.1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

6.2 Current and Voltage DC Offset Register ( I

DCoff ,VDCoff

) . . . . . . . . . . . . . . . . . . . .27

2 DS661F3

CS5461A

6.3 Current and Voltage Gain Register ( Ign ,V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

gn

6.4 Cycle Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

6.5 PulseRateE

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

1,2

6.6 Instantaneous Current, Voltage and Power Registers ( I , V , P ) . . . . . . . . . . . . . .28

6.7 Active (Real) Power Registers ( P

6.8 I

6.9 Power Offset Register ( P

RMS

and V

Registers ( I

RMS

, V

RMS

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

off

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Active

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

RMS

6.10 Status Register and Mask Register ( Status , Mask ) . . . . . . . . . . . . . . . . . . . . . .29

6.11 Current and Voltage AC Offset Register ( V

ACoff

, I

) . . . . . . . . . . . . . . . . . . .30

ACoff

6.12 PulseRateE3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6.13 Temperature Register ( T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6.14 System Gain Register ( SYSGain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6.15 Pulsewidth Register ( PW ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

6.16 E3 Pulse Width Register ( PulseWidth ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

6.17 Voltage Sag Duration Register ( VSAG

6.18 Voltage Sag Level Register ( VSAG

Level

Duration

) . . . . . . . . . . . . . . . . . . . . . . . . . .31

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

6.19 No Load Threshold Interval Register ( LoadIntv) . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.20 No Load Threshold ( LoadMin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.21 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.22 Temperature Gain Register ( T

6.23 Temperature Offset Register ( T

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Gain

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

off

6.24 Apparent Power Register ( S ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7.1 Channel Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7.1.1 Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7.1.1.1 Duration of Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7.1.2 Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7.1.2.1 DC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7.1.2.2 AC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

7.1.3 Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

7.1.3.1 AC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

7.1.3.2 DC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

7.1.4 Order of Calibration Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

7.3 Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

8. Auto-boot Mode Using E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

8.1 Auto-Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

2

8.2 Auto-Boot Data for E

8.3 Suggested E

2

PROM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

9. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

10. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

12. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . . . .43

13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

DS661F3 3

CS5461A

LIST OF FIGURES

Figure 1. CS5461A Read and Write Timing Diagrams ........................................................................... 11

Figure 2. Data Flow.................................................................................................................................13

Figure 3. Normal Format on pulse outputs E1
Figure 4. Alternate Pulse Format on E1
Figure 5. Mechanical Counter Format on E1
Figure 6. Stepper Motor Format on E1

Figure 7. Voltage Sag Detect..................................................................................................................19

Figure 8. Oscillator Connection...............................................................................................................20

Figure 9. Calibration Data Flow...............................................................................................................35

Figure 10. System Calibration of Offset..................................................................................................35

Figure 11. System Calibration of Gain ....................................................................................................36

Figure 12. Example of AC Gain Calibration............................................................................................36

Figure 13. Another Example of AC Gain Calibration ..............................................................................36

Figure 14. Typical Interface of E

Figure 15. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line)........... 39

Figure 17. Typical Connection Diagram (Single-phase, 3-wire)..............................................................40

Figure 16. Typical Connection Diagram (Single-phase, 2-wire – Isolated from Power Line)..................40

Figure 18. Typical Connection Diagram (Single-phase, 3-wire – No Neutral Available)......................... 41

and E2.......................................................................................18

2

PROM to CS5461A ............................................................................38

and E2 ............................................................................ 16

and E2.....................................................................................17

and E2..............................................................................17

LIST OF TABLES

Table 1. Current Channel PGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. E1

Table 3. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 DS661F3

and E2 Pulse Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CS5461A

1. OVERVIEW

The CS5461A is a CMOS monolithic power measurement device with a computation engine and an en­ergy-to-frequency pulse output. The CS5461A combines a programmable-gain amplifier, two  ana­log-to-digital converters (ADCs), system calibration and a computation engine on a single chip.

The CS5461A is designed for power measurement applications and is optimized to interface to a cur­rent-sense resistor or transformer for current measurement, and to a resistive divider or potential trans­former for voltage measurement. The voltage and current channels provide programmable gains to
accommodate various input levels from a wide variety of sensing elements. With single +5 V supply on
VA+/AGND, both of the CS5461A’s input channels can accommodate common mode as well as signal
levels between (AGND - 0.25 V) and VA+.

Additionally, the CS5461A is equipped with a computation engine that calculates I
power and active (real) power. To facilitate communication to a microprocessor, the CS5461A includes a
simple three-wire serial interface which is SPI™ and Microwire™ compatible. The CS5461A provides
three outputs for energy registration. E1
stepper motor, or interface to a microprocessor. The pulse output E3
ibration.

and E2 are designed to directly drive a mechanical counter or

is designed to assist with meter cal-

RMS

, V

, apparent

RMS

DS661F3 5

CS5461A

VREFIN 12Voltage Reference Input

VREFOUT 11Voltage Reference Output

VIN- 10Differential Voltage Input

VIN+ 9Differential Voltage Input

MODE 8Mode Select

CS 7Chip S e le c t

SDO 6Serial D a ta Ouput

SCLK 5Serial Clock

DGND 4Digital Ground

VD+ 3Positiv e Digital Supply

CPUCLK 2CPU Clock Output

XOUT 1Crystal Out

AGND13 Analog Ground

VA+14 Positive Analog Supply

IIN-15 Differential Current Input

IIN+16 Differential Current Input

PFMON17 Power Fail Monito r

E318 High Frequency Energ y O utput

RESET19 Reset

INT20 Interr up t

E121 Energy Output 1

22

SDI23 Serial Data Input

XIN24 Crystal In

E2

Energy Output 2

2. PIN DESCRIPTION

Clock Generator

Crystal Out
Crystal In

CPU Clock Output 2

Control Pins and Serial Data I/O

Serial Clock Input 5

Serial Data Output 6
Chip Select 7
Mode Select 8
High Frequency Energy

Output
Reset 19

Interrupt 20
Energy Output 21,22

Serial Data Input 23

Analog Inputs/Outputs

Differential V ol tage Inputs 9,10
Differential Current Inputs 15,16
Voltag e Reference Output 11

Voltage Reference Input 12

Power Supply Connections

Positive Digital Supply 3
Digital Ground 4
Positive Analog Supply 14
Analog Ground 13
Power Fail Monitor

6 DS661F3

XOUT, XIN - The output and input of an inverting amplifier. Oscillation occurs when connected to

1,24

a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to
the XIN pin to provide the system clock for the device.

CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.

SCLK - A Schmitt Trigger input pin. Clocks data from the SDI pin into the receive buffer and out of

the transmit buffer onto the SDO pin when CS

SDO -Serial port data output pin.SDO is forced into a high impedance state when CS is high.
CS - Low, activates the serial port interface.
MODE - High, enables the “auto-boot” mode. The mode pin is pulled low by an internal resistor.

18

E3 - Active low pulses with an output frequency proportional to the active power. Used to assist

in system calibration.
RESET - A Schmitt Trigger input pin. Low activates Reset, all internal registers (some of which

drive output pins) are set to their default states.
INT - Low, indicates that an enabled event has occurred.

is low.

E1, E2 - Active low pulses with an output frequency proportional to the active power. Indicates if

the measured energy is negative.

SDI - Serial port data input pin. Data will be input at a rate determined by SCLK.

VIN+, VIN- - Differential analog input pins for the voltage channel.
IIN+, IIN- - Differential analog input pins for the current channel.
VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magni-

tude of 2.5 V and is referenced to the AGND pin on the converter.

VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.

VD+ - The positive digital supply.
DGND - Digital Ground.
VA+ - The positive analog supply.
AGND - Analog ground.
PFMON - The power fail monitor pin monitors the analog supply. If PFMON’s voltage threshold is

17

not met, a Low-Supply Detect (LSD) bit is set in the status register.

CS5461A

3. CHARACTERISTICS & SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Positive Digital Power Supply VD+ 3.135 5.0 5.25 V
Positive Analog Power Supply VA+ 4.75 5.0 5.25 V
Voltage Reference VREFIN - 2.5 - V
Specified Temperature Range T

A

ANALOG CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.

• MCLK = 4.096 MHz.

Parameter Symbol Min Typ Max Unit

Linearity Performance

Active Power Accuracy (All Gain Ranges)
(Note 1) Input Range 0.1% - 100%

Current RMS Accuracy (All Gain Ranges)
(Note 1) Input Range 0.2% - 100%

Input Range 0.1% - 0.2%

Voltage RMS Accuracy (All Gain Ranges)
(Note 1) Input Range 5% - 100%

Analog Inputs (Both Channels)

Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB
Common Mode + Signal (All Gain Ranges) -0.25 - VA+ V

Analog Inputs (Current Channel)

Differential Input Range (Gain = 10)
[(IIN+) - (IIN-)] (Gain = 50)

Total Harmonic Distortion (Gain = 50) THD 80 94 - dB
Crosstalk with Voltage Channel at Full Scale (50, 60 Hz) - -115 - dB
Input Capacitance (Gain = 10)

(Gain = 50)
Effective Input Impedance EII 30 - - k
Noise (Referred to Input) (Gain = 10)

(Gain = 50)
Offset Drift (Without the high-pass filter) OD - 4.0 - µV/°C

Gain Error (Note 2) GE - ±0.4 %

Analog Inputs (Voltage Channel)

Differential Input Range {(VIN+) - (VIN-)}
Total Harmonic Distortion THD 65 75 - dB

Crosstalk with Current Channel at Full Scale (50, 60 Hz) - -70 - dB
Input Capacitance All Gain Ranges IC - 0.2 - pF
Effective Input Impedance EII 2 - - M
Noise (Referred to Input) N

Offset Drift (Without the high-pass Filter) OD - 16.0 - µV/°C
Gain Error (Note 2) GE - ±3.0 %

P

Active

I

RMS

V

IIN

VIN

RMS

IC

N

I

V

-40 - +85 °C

-±0.1-%

-

-

±0.2
±1.5

-

-

%
%

-±0.1-%

-

-

-

-

-

-

-500-mV

-140-µV

500
100

32
52

22.5

4.5

-

-

-

-

-

-

mV
mV

µV
µV

P-P
P-P

pF
pF

rms
rms

P-P

rms

DS661F3 7

CS5461A

PSRR 20

150

V

eq

--------- -







log=

(VREFOUTMAX - VREFOUTMIN)

VREFOUT

AVG

(

(

1

T

A

MAX

- T

A

MIN

(

(

1.0 x 10

(

(

6

TC

VREF

=

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Unit

Temperature Channel

Temperature Accuracy T - ±5 - °C

Power Supplies

Power Supply Currents (Active State) I

I

(VA+ = VD+ = 5 V)

D+

I

(VA+ = 5 V, VD+ = 3.3 V)

D+

A+

PSCA
PSCD
PSCD

Power Consumption Active State (VA+ = VD+ = 5 V)
(Note 3) Active State (VA+ = 5 V, VD+ = 3.3 V)

Stand-By State

PC

Sleep State

Power Supply Rejection Ratio (DC, 50 and 60 Hz)
(Note 4) Voltage Channel

Current Channel

PSRR

PFMON Low-voltage Tr igger Threshold (Note 5) PMLO 2.3 2.45 - V
PFMON High-voltage Power-On Trip Point (Note 6) PMHI - 2.55 2.7 V

1. Applies when the HPF option is enabled.

2. Applies before system calibration.

3. All outputs unloaded. All inputs CMOS level.

4. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz)
sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input
channels are shorted to AGND. Then the CS5461A is commanded to continuous conversion acquisition mode, and
digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output
signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured
in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output.
This voltage is then defined as Veq. PSRR is then (in dB)

:

45
70

-

-

-

-

-

-

-

1.1

2.9

1.7
21

12

8

10

65
75

-

-

-

28

16.5

-

-

-

-

mA
mA
mA

mW
mW
mW

µW

dB
dB

5. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.

6. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at
which the LSD bit can be permanently reset back to 0.

VOLTAGE REFERENCE

Parameter Symbol Min Typ Max Unit

Reference Output

Output Voltage VREFOUT +2.4 +2.5 +2.6 V
Temperature Coefficient (Note 7) TC

Load Regulation (Note 8) V

Reference Input

VREF

R

Input Voltage Range VREFIN +2.4 +2.5 +2.6 V
Input Capacitance - 4 - pF
Input CVF Current - 25 - nA

Notes: 7. The voltage at VREFOUT is measured across the temperature range. From these measurements the follo wing

formula is used to calculate the VREFOUT Temperature Coefficient:.

8. Specified at maximum recommended output of 1 µA, source or sink.

- 25 60 ppm/°C

-610mV

8 DS661F3

CS5461A

DIGITAL CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply volt ages and TA = 25 °C.

• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• MCLK = 4.096 MHz.

Parameter Symbol Min Typ Max Unit

Master Clock Characteristics

Master Clock Frequency Internal Gate Oscillator (Note 10) MCLK 2.5 4.096 20 MHz
Master Clock Duty Cycle 40 - 60 %
CPUCLK Duty Cycle (Note 11 and 12) 40 60 %

Filter Characteristics

Phase Compensation Range (Voltag e Channel, 60 Hz) -2.8 - +2.8 °
Input Sampling Rate DCLK = MCLK/K - DCLK/8 - Hz
Digital Filter Output Word Rate (Both Channels) OWR - DCLK/1024 - Hz
High-pass Filter Corner Frequency -3 dB - 0.5 - Hz
Full Scale Calibration Range (
Channel-to-channel Time-shift Error (Note 14) 1.0 µs

Input/Output Characteristics

High-level Input Voltage

All Pins Except XIN and SCLK and RESET

Low-level Input Voltage (VD = 5 V)

All Pins Except XIN and SCLK and RESET

Low-level Input Voltage (VD = 3.3 V)

All Pins Except XIN and SCLK and RESET

High-level Output Voltage I
Low-level Output Voltage I
Input Leakage Current (Note 15) I
3-state Leakage Current I
Digital Output Pin Capacitance C

Referred to Input) (Note 13) FSCR 25 - 100 %F.S.

XIN

SCLK and RESET

XIN

SCLK and RESET

XIN

SCLK and RESET

= +5 mA V

out

= -5 mA V

out

IH

0.6 VD+

(VD+) - 0.5

V

0.8VD+

V

IL

-

-

-

V

IL

-

-

-

(VD+) - 1.0 - - V

OH
OL
in

OZ

out

--0.4V

-±1±10µA

--±10µA

-5-pF

-

-

-

-

-

-

-

-

-

-

-

-

0.8

1.5

0.2VD+

0.48

0.3

0.2VD+

V
V
V

V
V
V

V
V
V

Notes: 9. All measurements performed under static conditions.

10. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used,
XIN frequency range is 2.5 M Hz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz.

11. If external MCLK is used, then the duty cycl e must be between 45% and 55% to maintain this specific ation.

12. The frequency of CPUCLK is equal to MCLK.

13. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the
full-scale signal applied to the channel input.

14. Configuration Register bits PC[6:0] are set to “0000000”.

15. The MODE pin is pulled low by an internal resistor.

DS661F3 9

CS5461A

SWITCHING CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply volt ages and TA = 25 °C.

• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.

Parameter Symbol Min Typ Max Unit

Rise Times Any Digital Input Except SCLK
(Note 16) SCLK

Any Digital Output

Fall Times Any Digital Input Except SCLK
(Note 16) SCLK

Any Digital Output

Start-up

Oscillator Start-Up Time XTAL = 4.096 MHz (Note 17) t

Serial Port Timing

Serial Clock Frequency SCLK - - 2 MHz
Serial Clock Pulse Width High

Pulse Width Low

SDI Timing

CS Falling to SCLK Rising t
Data Set-up Time Prior to SCLK Rising t
Data Hold Time After SCLK Rising t

SDO Timing

CS Falling to SDO Driving t
SCLK Falling to New Data Bit (hold time) t

Rising to SDO Hi-Z t

CS

Auto-Boot Timing

Serial Clock Pulse Width Low

Pulse Width High

MODE setup time to RESET
RESET
CS
SCLK falling to CS
CS

rising to CS falling t

falling to SCLK rising t

rising t

rising to driving MODE low (to end auto-boot sequence). t

Rising t

SDO guaranteed setup time to SCLK rising t

Notes: 16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external
clock source.

t

rise

t

t

fall

ost

t
t

t

10
11
12
13
14
15
16

-

-

-

-

-

-

50

50

-

-

-

-

1.0

100

-

1.0

100

-

µs
µs
ns

µs
µs
ns

-60-ms

1
2

3
4
5

6
7
8

9

200
200

50 - - ns
50 - - ns

100 - - ns

-2050ns

-2050ns

-2050ns

-

-

8
8

-

-

ns
ns

MCLK
MCLK

50 ns
48 MCLK

100 8 MCLK

16 MCLK

50 ns

100 ns

10 DS661F3

t

1

t

2

t

3

t

4

t

5

MSB

MSB-1

LSB

MSB

MSB-1

LSB

MSB

MSB-1

LSB

MSB

MSB-1

LSB

Com m and Time 8 S CLKs High Byte Mid Byte Low B yte

CS

SCLK

SDI

t

10

t

9

RESET

SDO

SCLK

CS

Last 8

Bits

SDI

MODE

STOP bit

D a ta fro m E E P R O M

t

16

t

4

t

5

t

14

t

15

t

7

t

13

t

12

t

11

(INPUT)

(INPUT)

(O UT P U T )

(O UT P U T )

(O UT P U T )

(INPUT)

SDI Write Timing (Not to Scale)

SDO Read Timing (Not to Scale)

Figure 1. CS5461A Read and Write Timing Diagrams

Auto-Boot Sequence Timing (Not to Scale)

t

1

t

2

MSB

MSB-1

LSB

Com m and Time 8 SC LKs

SYNC0 or SYNC1

Command

SYN C 0 or SYN C1

Command

MSB

MSB-1

LSB

MSB

MSB-1

LSB

MSB

MSB-1

LSB

H igh B y te M id B y te Lo w B y te

CS

SDO

SDI

t

6

t

7

t

8

SYN C 0 or SYN C1

Command

UNKNOWN

CS5461A

DS661F3 11

ABSOLUTE MAXIMUM RATINGS

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Notes 18 and 19)

Positive Digital

Positive Analog

Input Current, Any Pin Except Supplies (Notes 20, 21, 22) I
Output Current, Any Pin Except VREFOUT I
Power Dissipation (Note 23) P

Analog Input Voltage All Analog Pins V
Digital Input Voltage All Digital Pins V
Ambient Operating Temperature T
Storage Temperature T

Notes: 18. VA+ and AGND must satisfy {(VA+) - (AGND)}  + 6.0 V.

19. VD+ and AGND must satisfy {(VD+) - (AGND)}

20. Applies to all pins including cont inuous over-voltage conditions at the analog input pins.

21. Transient current of up to 100 mA will not cause SCR latch-up.

22. Maximum DC input current for a power supply pin is ±50 mA.

23. Total power dissipation, including all input currents and output currents.

 + 6.0 V.

.

VD+
VA+

IN

OUT

D --500mW

INA
IND

A

stg

-0.3

-0.3

-

-

--±10mA

--100mA

- 0.3 - (VA+) + 0.3 V

-0.3 - (VD+) + 0.3 V

-40 - 85 °C

-65 - 150 °C

CS5461A

+6.0
+6.0

V
V

12 DS661F3

4. THEORY OF OPERATION

VOLTAGE

SINC

3

+

X

V*

gn

X

V

*

CURRENT

SINC

3

+

X

I*

gn

DELAY

REG

DELAY

REG

HPF

Option

X

I*

RMS

V*

RMS

E1

IIR

I

*

I

DCoff

*

V

DCoff

*

PGA

IIR

X

+

+





Energy-to-pulseX

E3

+



X

+

Configuration Register *

Digital Filter

Digital Filter

HPF

Option

X

S

*

2nd Order



Modulator

4th Order



Modulator

x10

+

I

ACoff

*



+

+

V

ACoff

*



+

E2



N

÷

N



N

÷

N



P

*

Active



N

÷

N



P

off

*

P

*

X

X

SYS

Gain

*

PC6 PC5 PC4 PC3

PC2

PC1 PC0

6

PulseRateE

1,2

*

PulseRateE

3

*

Energy-to-pulse

*

DENOTES REGISTER NAME.

APF

Option

APF

Option

Figure 2. Data Flow.

I

RMS

I

n

n0=

N1–



N

--------------------

=

The CS5461A is a dual-channel analog-to-digital con­verter (ADC) followed by a computation engine that per­forms power calculations and energy-to-pulse
conversion. The flow diagram for the tw o data paths is
depicted in Figure 2. The analog inputs are structured
with two dedicated channels, voltage and current, then
optimized to simplify interfacing to sensing elements.

The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is sub­ject to a gain of 10x. A second-order, delta-sigma mod­ulator samples the amplified signal for digitization.

Simultaneously, the current-sensing element introduces
a voltage waveform on the current channel input IIN±
and is subject to the two selectable gains of the pro­grammable gain amplifier (PGA). The amplified signal is
sampled by a fourth-order, delta-sigma modulator for
digitization. Both converters sample at a rate of
MCLK /8, the over-sampling provides a wide dynamic
range and simplified anti-alias filter design.

CS5461A

When the HPF option is used in only one channel, the
APF (all pass filter) option can be applied to the other
channel to preserve the phase match between the two
channels.

4.2 Voltage and Current Measurements

The digital filter output word is then subject to a DC off­set adjustment and a gain calibration (See Section 7.

System Calibration on page 35). The calibrated me a-

surement is available to the user by reading the instan­taneous voltage and current registers.

The Root Mean Square (RMS) calculations are per­formed on N instantaneous voltage and current sam­ples, V

n and In respectively (where N is the cycle count),

using the formula:

4.1 Digital Filters

The decimating digital filters on both channels a re Sinc
filters followed by 4th-order, IIR filters. The single-bit
data is passed to the low-pass decimation filter and out­put at a fixed word rate. The o utput word is passed to
the IIR filter to compensate for the magnitude roll-off of
the low-pass filtering operation.

An optional digital High-pass Filter (HPF in Figure 2) re­moves any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled, the DC component will be removed
from the calculated V
ent power.

DS661F3 13

RMS

and I

as well as the appar-

RMS

3

and likewise for V

, using Vn. I

RMS

RMS

and V

RMS

cessible by register reads, which are updated once ev­ery cycle count (referred to as a computational cycle).

4.3 Power Measurements

The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Fig-

ure 2). The product is then averaged over N conver-

provides a uni-

sions to compute active power and used to drive energy
pulse outputs E1, E2 and E3. Output E3
form pulse stream that is proportional to the active pow­er and is designed for system calibration.

are ac-

CS5461A

SV

RMSIRMS

=

To generate a value for the accumulated active energy
over the last computation cycle, the active power can be
multiplied by the time duration of the computation cycle.

The apparent power is the combination of the active
power and reactive power, without reference to an im­pedance phase angle, and is calculated by the
CS5461A using the following formula:

The apparent power is registered on ce eve ry co mpu ta­tion cycle.

4.4 Linearity Performance

The linearity of the V
surements (before calibration) will be within ±0.1% of

RMS

, I

, and active power mea-

RMS

reading over the ranges specified, with respect to the in­put voltage levels required to cause full-scale readings
in the I

RMS

and V

registers. Refer to Linearity Per-

RMS

formance Specifications on page 7.

Until the CS5461A is calibrated, the accuracy of the
CS5461A (with respect to a reference line-voltage and
line-current level on the power mains) is not guaranteed
to within ±0.1%. See Section 7. System Calibration on
page 35. The accuracy of the internal calculations can
often be improved by selecting a value for the Cycle
Count Register that will cause the time duration of one
computation cycle to be equal to (or very close to) a
whole-number of power-line cycles (and N must be
greater than or equal to 4000).

14 DS661F3