Energy Data Linearity: ±0.1% of Reading
over 1000:1 Dynamic Range.
On-Chip Functions: (Real) Energy, I ∗ V,
and V
I
RMS
Smart “Auto-Boot” Mode from Serial
EEPROM Enables Use without MCU.
AC or DC System Calibration
Mechanical Counter/Stepper Motor Driver
Meets Accuracy Spec for IEC 687/1036, JIS
Power Consumption <12 mW
Interface Optimized for Shunt Sensor
V vs. I Phase Compensation
Ground-Referenced Signals with Single
Supply
On-chip 2.5 V Reference (MAX 60 ppm/°C
drift)
Simple Three-Wire Digital Serial Interface
Watch Dog Timer
Power Supply Monitor
Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD+ = +3.3 V to +5 V
, Energy-to-Pulse Conversion
RMS
Description
The CS5460A is a highly integrated ∆Σ Analog-to-Digital
Converter (ADC) which combines two ∆Σ ADCs, high
speed power calculation functions, and a serial interface
on a single chip. It is designed to accurately measure
and calculate: Real (True) Energy, Instantaneous Power, I
metering applications. The CS5460A interfaces to a
low-cost shunt resistor or transformer to measure current, and resistive divider or potential transformer to
measure voltage. The CS5460A features a bi-directional
serial interface for communication with a micro-controller and a pulse output engine for which the average
pulse frequency is proportional to the real power.
CS5460A has on-chip functionality to facilitate AC or DC
system-level calibration.
The “Auto-Boot” feature allows the CS5460A to function
‘stand-alone’ and to initialize itself on system power-up.
In Auto-Boot Mode, the CS5460A reads the calibration
data and start-up instructions from an external EEPROM. In this mode, the CS5460A can operate without
a microcontroller, in order to lower the total bill-of-materials cost, when the meter is intended for use in
high-volume/residential metering applications.
Microwire is a trademark of National Semiconductor Corporation.
Preliminary product i nformation describes products which are in production, but for which full characterization data is not yet availabl e. Advance product information describes products which are in development and subject to development changes. Cir rus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this i nformation, nor for infri ngements of patents or other rights
of third parties. This document is the property o f Ci rrus Logic, Inc. and implies no license under patents, copyrights, t rademarks, or trade secr ets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, i n any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the print out or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the pri or written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendor s and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. tr ademarks and service marks can be found at http://www.cirrus.com.
2DS487PP4
CS5460A
4.3.3 Which EEPROMs Can Be Used? ....................................................................... 31
4.4 Interrupt and Watchdog Timer ......................................................................................... 33
Table 1. Differential Input Voltage vs. Output Code ............................................................................ 15
Table 2. Available range of ±0.1% output linearity, with default settings in the gain/offset registers... 15
Table 3. Default Register Values upon Reset Event ........................................................................... 24
4DS487PP4
1. CHARACTERISTICS AND SPECIFICATIONS
CS5460A
ANALOG CHARACTERISTICS (T
= -40° C to +85° C; VA+ = VD+ = +5 V ±10%; VREFIN = +2.5 V;
A
VA- = AGND = 0 V; MCLK = 4.096 MHz, K = 1; N = 4000 ==> OWR = 4000 Sps.)(See Notes 1, 2, 3, 4, and 5.)
ParameterSymbolMinTypMaxUnit
Accuracy (Both Channels)
Common Mode Rejection(DC, 50, 60 Hz)CMRR80--dB
Offset Drift (Without the High Pass Filter)-5-nV/°C
Analog Inputs (Current Channel)
Maximum Differential Input Voltage Range(Gain = 10)
{(V
IIN+)-(VIIN-)}(Gain = 50)
Total Harmonic DistortionTHD
IN-
I
-
I74--dB
±250
±50
-
-
mV
mV
Common Mode + Signal on IIN+ or IIN-(Gain = 10 or 50)-0.25-VA+V
Crosstalk with Voltage Channel at Full Scale(50, 60 Hz)---115dB
Input Capacitance(Gain = 10)
(Gain = 50)
in-
C
-
25
25
-
-
pF
pF
Effective Input Impedance(Note 6)
(Gain = 10)
(Gain = 50)
Noise(ReferredtoInput)(Gain=10)
(Gain = 50)
Z
ZinI
inI
-
-
-
-
30
30
-
-
-
-
20
4
µV
µV
kΩ
kΩ
rms
rms
Accuracy (Current Channel)
Bipolar Offset Error(Note 1)VOS
Full-Scale Error(Note 1)FSE
I-±0.001-%F.S.
I-±0.001-%F.S.
Analog Inputs (Voltage Channel)
Maximum Differential Input Voltage Range{(V
Total Harmonic DistortionTHD
VIN+)-(VVIN-)}VIN-±250-mV
V62--dB
Common Mode + Signal on VIN+ or VIN--0.25-VA+V
Crosstalk with Current Channel at Full Scale(50, 60 Hz)---70dB
Input CapacitanceC
Effective Input Impedance(Note 6)Z
Noise(ReferredtoInput)--250µV
inV-0.2-pF
inV-5-MΩ
rms
Accuracy (Voltage Channel)
Bipolar Offset Error(Note 1)VOS
Full-Scale Error(Note 1)FSE
V-±0.01-%F.S.
V-±0.01-%F.S.
Notes: 1. Bipolar Offset Errors and Full-Scale Gain Errors for the current and voltage channels refer to the
respective Irms Register and Vrms Register output, when the device is operating in ‘continuous
computation cycles’ data acquisition mode, after offset/gain system calibration sequences have been
executed. These specs do not apply to the error of the Instantaneous Current/Voltage Register output.
2. Specifications guaranteed by design, characterization, and/or test.
3. Analog signals are relative to VA- and digital signals to DGND unless otherwise noted.
4. In requiring VA+=VD+=5V ±10%, note that it is allowable for VA+, VD+ to differ by as much as ±200mV,
as long as VA+ > VD+.
5. Note that “Sps” is an abbreviation for units of “samples per second”.
6. Effective Input Impedance (Z
Z
in = 1/(IC*DCLK/4). Note that DCLK = MCLK / K.
in) is determined by clock frequency (DCLK) and Input Capacitance (IC).
Notes: 7. The minimum FSCR is limited by the maximum allowed gain register value.
8. All outputs unloaded. All inputs CMOS level.
9. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5V, a 150mV zero-to-peak sinewave
(frequency = 60Hz) is imposed onto the +5V supply voltage at VA+ and VD+ pins. The “+” and “-” input
pins of both input channels are shorted to VA-. Then the CS5460A is commanded to ’continuous
computation cycles’ data acquisition mode, and digital output data is collected for the channel under
test. The zero-peak value of the digital sinusoidal output signal is determined, and this value is
converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the
channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as
Veq. PSRR is then (in dB):
0.150V
PSRR20
--------- ---------
log⋅=
V
eq
10. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.
11. Assuming that the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), then if/when
the PFMON voltage starts to rise again, PMHI is the voltage level (on PFMON pin) at which the LSD bit
can be permanently reset back to 0 (without instantaneously changing back to 1). Attempts (by the
user) to reset the LSD bit before this condition is true will not be successful. This condition indicates
that power has been restored. Typically, for a given sample, the PMHI voltage will be ~100mV above
the PMLO voltage.
6DS487PP4
CS5460A
VREFOUT REFERENCE OUTPUT VOLTAGE
ParameterSymbolMinTypMaxUnit
Reference Output
Output VoltageREFOUT+2.4-+2.6V
VREFOUT Temperature Coefficient(Note 12) T
Load Regulation(Output Current 1 µA Source or Sink)∆V
Reference Input
Input Voltage RangeVREFIN+2.4+2.5+2.6V
Input Capacitance-4-pF
Input CVF Current-25-nA
Notes: 12. See Section 4.7 for definition of VREFOUT Temperature Coefficient spec.
VREFO UT-25-ppm/°C
R
-610mV
5V DIGITAL CHARACTERISTICS (T
= -40° C to +85° C; VA+ = VD+ = 5 V ±10% VA-, DGND =
A
0 V) (See Notes 3, 4, and 13)
ParameterSymbolMinTypMaxUnit
High-Level Input Voltage
All Pins Except XIN, SCLK and RESET
XIN
SCLK and RESET
Low-Level Input Voltage
All Pins Except XIN, SCLK, and RESET
XIN
SCLK and RESET
High-Level Output Voltage (except XOUT)I
Low-Level Output Voltage (except XOUT)I
=+5mAV
out
=-5mAV
out
Input Leakage Current(Note 14)I
3-State Leakage CurrentI
Digital Output Pin CapacitanceC
13. Note that the 5V characteristics are guaranteed by characterization. Only the more rigorous 3.3 V digital
characteristics are actually verified during production test.
14. Applies to all INPUT pins except XIN pin (leakage current < 50 µA) and MODE pin (leakage current <
25 µA).
V
V
OH
OL
in
OZ
out
IH
IL
0.6 VD+
(VD+) - 0.5
0.8 VD+
-
-
-
-
-
-
-
-
-
(VD+) - 1.0--V
--0.4V
-±1±10µA
--±10µA
-5-pF
-
-
-
0.8
1.5
0.2 VD+
V
V
V
V
V
V
DS487PP47
CS5460A
3.3 V DIGITAL CHARACTERISTICS (T
= -40° C to +85° C; VA+ = 5 V ±10%, VD+ = 3.3 V ±10%;
A
VA-, DGND = 0 V) (See Notes 3, 4, and 13)
ParameterSymbolMinTypMaxUnit
High-Level Input Voltage
All Pins Except XIN, XOUT, SCLK, and RESET
XIN
SCLK and RESET
Low-Level Input Voltage
AllPinsExceptXIN,XOUT,SCLK,andRESET
XIN
SCLK and RESET
High-Level Output Voltage (except XIN, XOUT) I
Low-Level Output Voltage (except XIN, XOUT) I
=+5mAV
out
=-5mAV
out
Input Leakage Current(Note 14)I
3-State Leakage CurrentI
Digital Output Pin CapacitanceC
Notes: 15. All measurements performed under static conditions.
16. If VD+ = 3V and if XIN input is generated using crystal, then XIN frequency must remain between 2.5
MHz - 5.0 MHz. If using oscillator, full XIN frequency range is available, see Switching Characteristics.
V
V
OH
OL
in
OZ
out
IH
IL
0.6 VD+
(VD+) - 0.5
0.8 VD+
-
-
-
-
-
-
-
-
-
(VD+) - 1.0--V
--0.4V
-±1±10µA
--±10µA
-5-pF
-
-
-
0.48
0.3
0.2 VD+
V
V
V
V
V
V
ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 17) WARNING: Operation at or beyond
these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
ParameterSymbolMinTypMaxUnit
DC Power Supplies(Notes 18 and 19)
Positive Digital
Positive Analog
Negative Analog
Input Current, Any Pin Except Supplies(Note 20, 21, and 22)I
Output CurrentI
Power Dissipation(Note 23)P
Analog Input VoltageAll Analog PinsV
Digital Input VoltageAll Digital PinsV
Ambient Operating TemperatureT
Storage TemperatureT
Notes: 17. All voltages with respect to ground.
18. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.0 V.
19. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +6.0 V.
20. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins.
21. Transient current of up to 100 mA will not cause SCR latch-up.
22. Maximum DC input current for a power supply pin is ±50 mA.
23. Total power dissipation, including all input currents and output currents.
VD+
VA+
VA-
IN
OUT
D--500mW
INA
IND
A
stg
-0.3
-0.3
+0.3
-
-
-
+6.0
+6.0
-6.0
--±10mA
--±25mA
(VA-) - 0.3-(VA+) + 0.3V
DGND - 0.3-(VD+) + 0.3V
-40-85°C
-65-150°C
V
V
V
8DS487PP4
CS5460A
SWITCHING CHARACTERISTICS (T
= -40° C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10%
Serial Clock FrequencySCLK--2MHz
Serial ClockPulse Width High
Pulse Width Low
t
1
t
2
200
200
-
-
-
-
ns
ns
SDI Timing
CS
Falling to SCLK Risingt
Data Set-up Time Prior to SCLK Risingt
Data Hold Time After SCLK Risingt
SCLK Falling Prior to CS
Disablet
3
4
5
6
50--ns
50--ns
100--ns
100--ns
SDO Timing
Falling to SDO Drivingt
CS
SCLK Falling to New Data Bitt
Rising to SDO Hi-Zt
CS
7
8
9
-2050ns
-2050ns
-2050ns
Auto-Boot Timing
Serial ClockPulse Width High
Pulse Width Low
MODEsetuptimetoRESET
RESET
CS
SCLK falling to CS
CS
rising to CS fallingt
falling to SCLK risingt
risingt
rising to driving MODE low (to end auto-boot sequence).t
Risingt
SDO guaranteed setup time to SCLK risingt
t
10
t
11
12
13
14
15
16
17
50ns
48MCLK
1008MCLK
50ns
100ns
8
8
16MCLK
MCLK
MCLK
Notes: 24. Device parameters are specified with a 4.096 MHz clock, however, clocks between 3 MHz to 20 MHz
can be used. However, for input frequencies over 5 MHz, an external oscillator must be used, or if a
crystal over 5 MHz is to be used, then VD+ must be set to 5V (not 3V).
25. If external MCLK is used, then duty cycle must be between 45% and 55% to maintain this specification.
26. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
DS487PP49
CS5460A
6
t
LSB
9
t
LSB
Low Byte
MSB MSB - 1
LSB
MSB MSB - 1
LSB
High ByteMid ByteLow Byte
t
45
t
MSB MSB - 1
LSB
MSB MSB - 1
LSB
.
I
O
D
D
S
S
n
m
o
o
r
d
f
n
a
a
MSB MSB - 1
LSB
SDI Write Timing (Not to Scale)
High ByteMid Byte
8
t
MSB MSB -1
LSB
t
a
m
d
m
f
o
o
c
e
t
"
y
0
b
C
h
N
c
Y
a
S
e
"
g
e
n
b
i
o
d
r
t
a
e
s
r
t
s
n
u
e
h
M
w
SDO Read Timing (Not to Scale)
2
t
1
t
3
t
CS
SCLK
Command Time 8 S CLKs
MSB MSB - 1
SDI
CS
2
t
1
t
7
t
SDO
SCLK
CommandTime8SCLKs
MSB MSB - 1
SDI
Figure 1. CS5460A Read and Write Timing Diagrams
10DS487PP4
CS5460A
16
t
15
t
LAST 8 BITS
BIT
STOP
5
t
4
t
8
t
17
t
Data from EEPROM
Figure 2. CS5460A Auto-Boot Sequence Timing
10
t
14
t
13
t
12
t
RES
(Input)
(Input)
MODE
CS
(Output)
1
1
t
SDI
SCLK
SDO
(Output)
(Input)
(Output)
DS487PP411
CS5460A
2. GENERAL DESCRIPTION
The CS5460A is a CMOS monolithic power measurement device with a real power/energy computationengine.TheCS5460Acombinestwo
programmable gain amplifiers, two ∆Σ modulators,
two high rate filters, system calibration, and
rms/power calculation functions to provide instantaneous voltage/current/power data samples as well
as periodic computation results for real (billable)
energy, V
lower cost metering applications, the CS5460A can
also generate pulse-train signals on certain output
pins, for which the number of pulses emitted on the
pins is proportional to the quantity of real (billable)
energy registered by the device.
The CS5460A is optimized for power measurement
applications and is designed to interface to a shunt
or current transformer to measure current, and a resistive divider or potential transformer to measure
voltage. To accommodate various input voltage
levels, the current channel includes a programmable gain amplifier (PGA) which provides either
±250 mV or ±50 mV as the full-scale input level.
The voltage channel’s PGA provides a single input
voltage range of
ply across VA+/VA- the pins, the differential input
pins of both input channels accommodate common
mode + signal levels between -0.25 V and +5V.
Note that the designer can realize true differential
bipolar input configurations on either/both channels, in which the common-mode level of the input
signal is at AGND potential (if desired).
The CS5460A includes two high-rate digital filters
(one per channel), which decimate/integrate the output from the 2 ∆Σ modulators. The filters yield
24-bit output data at a (MCLK/K)/1024 output word
rate (OWR). The OWR can be thought of as the effective sample frequency of the voltage channel and
the current channel.
To facilitate communication to a microcontroller,
the CS5460A includes a simple three-wire serial
RMS
, and I
±250 mV. With single +5 V sup-
. In order to accommodate
RMS
interface which is SPI™ and Microwire™ compatible. The serial port has a Schmitt Trigger input on
its SCLK (serial clock) and RESET
pins to allow
for slow rise time signals.
2.1 Theory of Operation
A computational flow diagram for the two data
paths is shown in Fig. 3. The reader should refer to
this diagram while reading the following data processingdescription,whichiscovered
block-by-block.
2.1.1 ∆Σ Modulators
The analog waveforms at the voltage/current channel inputs are subject to the gains of the input PGAs
(not shown in Figure 3). These waveforms are then
sampled by the delta-sigma modulators at a rate of
(MCLK/K)/8 Sps.
2.1.2 High-Rate Digital Low-Pass Filters
The data is then low-pass filtered, to remove
high-frequency noise from the modulator output.
Referring to Figure 3, the high rate filter on the
voltage channel is implemented as a fixed Sinc
ter. The current channel uses a Sinc
4
filter, which
allows the current channel to make accurate measurements over a wider span of the total input
range, in comparison to the accuracy range of the
voltage channel. (This subject is discussed more in
Section 2.2.1)
Also note from Figure 3 that the digital data on the
voltage channel is subjected to a variable time-delay filter. The amount of delay depends on the value of the seven phase compensation bits (see PhaseCompensation), which can be set by the user. Note
that when the phase compensation bits PC[6:0] are
set to their default setting of “0000000” (and if
MCLK/K = 4.096MHz) then the nominal time delay that is imposed on the original analog voltage
input signal, with respect to the original analog current input signal, is ~1.0
µs. This translates into a
delay of ~0.0216 degrees at 60Hz.
2
fil-
12DS487PP4
CS5460A
2.1.3 Digital Compensation Filters
The data from both channels is then passed through
two FIR compensation filters, whose purpose is to
compensate for the magnitude roll-off of the
low-pass filtering operation (mentioned earlier).
2.1.4 Digital High-Pass Filters
Both channels provide an optional high-pass filter
(denoted as “HPF” in Figure 3) which can be engaged into the signal path, to remove the DC content
from the current/voltage signal before the RMS/energy calculations are made. These filters are activated by enabling certain bits in the Configuration
Register.
If the user wants to engage the high-pass filter in
only one of the two channels, then the all-pass filter
(see “APF” in Figure 3) will be enabled on the other channel, in order to preserve the relative phase
relationship between the voltage-sense and current-sense input signals. For example, if the HPF is
engaged for the voltage channel, but not the current
channel, then the APF will be engaged in the current
channel, to nullify the additional phase delay introduced by the high-pass filter in the current channel.
2.1.5 Overall Filter Response
When the CS5460A is driven with a 4.096 MHz
clock (K=1), the composite magnitude response
(over frequency) of the voltage channel’s input filter network is shown in Figure 4, while the composite magnitude response of the current channel’s
input filter network is given in Figure 5. Note that
the composite filter response of both channels
scales with MCLK frequency and K.
2.1.6 Gain and DC Offset Adjustment
After the filtering, the instantaneous voltage and
current digital codes are both subjected to offset/gain adjustments, based on the values in the DC
offset registers (additive) and the gain registers
(multiplicative). These registers are used for calibration of the device (see Section 4.8, Calibration).
After offset and gain, the 24-bit instantaneous data
sample values are stored in the Instantaneous Voltage and Current Registers, from which the user can
read out the data samples (via the serial interface).
2.1.7 Real Energy and RMS Computations
The digital instantaneous voltage and current data
is then processed further. Referring to Figure 3, the
instantaneous voltage/current data samples are
multiplied together (one multiplication for each
pair of voltage/current samples) to form instantaneous (real) power samples. After each A/D conversion cycle, the new instantaneous power sample
is stored (and can be read by the user) in the Instantaneous Power Register.
The instantaneous power samples are then grouped
into sets of N samples (where N = value in Cycle
Count Register). The cumulative sum of each successive set of N instantaneous power is used to
compute the result stored in the Energy Register,
which will be proportional to the amount of real energy registered by the device during the most recent
N A/D conversion cycles. Note from Figure 3 that
the bits in this running energy sum are right-shifted
12 times (divided by 4096) to avoid overflow in the
Energy Register. RMS calculations are also performed on the data using the last N instantaneous
voltage/current samples, and these results can be
read from the RMS Voltage Register and the RMS
Current Register.
2.2 Performing Measurements
To summarize Section 2.1, the CS5460A performs
measurements of instantaneous current and instantaneous voltage, and from this, performs computations of the corresponding instantaneous power, as
well as periodic calculations of real energy, RMS
current, and RMS voltage. These measurement/calculation results are available to the user in the form
of 24-bit signed and unsigned words. The scaling
of all outputwords is normalized to unity
full-scale. Note that the 24-bit signed output words
DS487PP413
CS5460A
VOLTAGE
CURRENT
∆Σ
∆Σ
DELAY
REG
DELAY
2
SINC
SINC
REG
Confi guratio n Register *
PC[6:0] Bits
4
FIRHPF
AP F
FIR
HPF
AP F
Figure 3. Data Flow.
are expressed in two’s complement format. The
24-bit data words in the CS5460A output registers
represent values between 0 and 1 (for unsigned output registers) or between -1 and +1 (for signed output registers). A register value of 1 represents the
maximum possible value. Note that a value of 1.0
is never actually obtained in the registers of the
CS5460A. As an illustration, in any of the signed
output registers, the maximum register value is
[(2^23 - 1) / (2^23)] = 0.999999880791. After each
A/D conversion, the CRDY bit will be asserted in
the Status Register, and the INT
pin will also be-
come active if the CRDY bit is unmasked (in the
V
DCoff
I
DCoff
+
+
V*
*
I*
*
gn
x
x
gn
*
V
V
*
ACoff
x
-
*
P
off
xx
+
*
P
x
-
*
I
I
ACoff
* DENOTES REGISTER NAME
2
SINC
TBC *
N
Σ
2
SINC
*
N
EtoF
÷÷÷÷
4096
PULSE-RATE*
N
÷
E*
E
E
N
out
dir
N
÷
Mask Register). The assertion of the CRDY bit indicates that new instantaneous 24-bit voltage and
current samples have been collected, and these two
samples have also been multiplied together to provide a corresponding instantaneous 24-bit power
sample .
Table 1 conveys the typical relationship between
the differential input voltage (across the “+” and
“-” input pins of the voltage channel input) and the
corresponding output code in the Instantaneous
Voltage Register. Note that this table is applicable
for the current channel if the current channel’s
PGA gain is set for the “10x” gain mode.
Table 1. Differential Input Voltage vs. Output Code
The V
RMS,IRMS
(hexidecimal)
, and energy calculations are up-
Output Code
(decimal)
dated every N conversions (which is known as 1
“computation cycle”), where N is the value in the
Cycle Count Register. At the end of each computation cycle, the DRDY bit in the Mask Register will
be set, and the INT
pin will become active if the
DRDY bit is unmasked.
DRDY is set only after each computation cycle has
completed, whereas the CRDY bit is asserted after
each individual A/D conversion. After any time
that these bits are asserted by the CS5460A, they
must be cleared (by the user) before they can be asserted again, so that they can trigger another interrupt event on the INT pin.If the Cycle Count
Register value (N) is set to 1, all output calculations
are instantaneous, and DRDY will indicate when
instantaneous calculations are finished, just like the
CRDY bit. For the RMS results to be valid, the Cycle-Count Register must be set to a value greater
than 10.
The computation cycle frequency is derived from
themasterclock,andhasavalueof
(MCLK/K)/(1024*N). Under default conditions,
with a 4.096 Mhz clock at XIN, and K = 1, instantaneous A/D conversions for voltage, current, and
power are performed at a 4000 Sps rate, whereas
I
RMS
,V
, and energy calculations are per-
RMS
formed at a 1 Sps rate.
2.2.1 CS5460A Linearity Performance
Table 2 lists the range of input levels (as a percentage of full-scale registration in the Energy, Irms,
and Vrms Registers) over which the (linearity +
CS5460A
variation) of the results in the Vrms, Irms and Energy Registers are guaranteed to be within
reading, after the completion of each successive
computation cycle. Note that until the CS5460A is
calibrated (see Calibration) the accuracy of the
CS5460A (with respect to a reference line-voltage
and line-current level on the power mains) is not
guaranteed to within
±0.1%. But the linearity of
any given sample of CS5460A, before calibration,
will indeed be to within ±0.1% of reading over the
ranges specified, with respect to the input voltage
levels required (on the voltage and current channels) to cause full-scale readings in the Irms/Vrms
Registers. After both channels of the device are
calibrated for offset/gain, the ±0.1% of reading
spec will also reflect accuracy of the Vrms, Irms,
and Energy Register results. Finally, observe that
the typical maximum (full-scale) differential input
voltage for the voltage channel (and current channel, when its PGA is set for 10x gain) is 250mV
(nominal). If the gain registers of both channels
aresetto1(default)andthetwoDCoffsetregisters are set to zero (default), then a 250mV dc
signal applied to the voltage/current inputs will
measure at (or near) the maximum value of
0.9999... in the RMS Current/Voltage Registers.
Remember that the RMS value of a 250mV (dc)
signal is also 250mV. However, for either input
channel, it would not be practical to inject a sinusoidal voltage with RMS value of 250mV. This is because when the instantaneous value of such a sine
EnergyVrmsIrms
Range (% of FS)
Max. Differential
Input
Linearity
Table 2. Available range of ±0.1% output linearity, with
default settings in the gain/offset registers.
0.1% - 100%
not applicable
0.1% of
reading
50% - 100%0.2% - 100%
V-channel:
±250mV
0.1% of
reading
±0.1% of
I-channel:
±250mV 10x
±50mV 50x
0.1% of
reading
DS487PP415
CS5460A
wave is at or near the level of its positive/negative
peak regions (over each cycle), the voltage level of
this signal would exceed the maximum differential
input voltage range of the input channels. The largest sine wave voltage signal that can be presented
across the inputs, with no saturation of the inputs,
is (typically) 250mV / sqrt(2) = ~176.78 mV
(RMS), which is at ~70.7% of full-scale.This
would imply that for the current channel, the (linearity+variation) tolerance of the RMS measurements for a purely sinusoidal 60 Hz input signal
could be measured to within
a magnitude range of 0.2% - 70.7% (of the maximum full-scale differential input voltage level).
The range over which the (linearity + variation)
will remain within ±0.1% of reading can often be
increased by selecting a value for the Cycle-Count
Register such that the time duration of one computation cycle is equal to (or very close to) a
whole-number of power-line cycles (and N must be
greater than or equal to 4000). For example, with
the cycle count set to 4200, the ±0.1% of reading
(linearity + variation) range for measurement of a
60 Hz sinusoidal current-sense voltage signal (created by sensing the current on a power line) can be
increased beyond the range of 0.2% - 70.7%. The
accuracy range will be increased because (4200
samples / 60 Hz) is a whole number of cycles (70).
Note that this increase in the measurement range
refers to an extension of the low end of the input
scale (i.e., this does not extend the high-end of the
range above 100% of full-scale). This enables accurate measurement of even smaller power-line
current levels, thereby extending the load range
over which the power meter can make accurate energy measurements. Increasing the accuracy range
can be beneficial for power metering applications
which require accurate power metering over a very
large load range.
±0.1% of reading over
2.2.2 Single Computation Cycle (C=0)
Note that ‘C’ refers to the value of the C bit, contained in the ‘Start Conversions’ command (see
Section 3.1).This commands instructs the
CS5460A to perform conversions in ‘single computation cycle’ data acquisition mode. Based on
the value in the Cycle Count Register, a single
computation cycle is performed after the user transmits the ‘Start Conversions’ command to the serial
interface. After the computations are complete,
DRDY is set. 32 SCLKs are then needed to read out
a calculation result from one of several result registers. The first 8 SCLKs are used to clock in the
command to determine which register is to be read.
The last 24 SCLKs are used to read the desired register. After reading the data, the serial port remains
in the active state, and waits for a new command to
be issued. (See Section 3 for more details on reading register data from the CS5460A).
2.2.3 Continuous Computation Cycles (C=1)
When C=1, the CS5460A will perform conversions
in ‘continuous computation cycles’ data acquisition
mode. Based on the information provided in the Cycle Count Register, computation cycles are repeatedly performed on the voltage and current channels
(after every N conversions). Computation cycles
cannot be started/stopped on a ‘per-channel’ basis.
After each computation cycle is completed, DRDY
is set. Thirty-two SCLKs are then needed to read a
register. The first 8 SCLKs are used to clock in the
command to determine which results register is to be
read. The last 24 SCLKs are used to read out the
24-bit calculation result. While in this acquisition
mode, the designer/programmer may choose to acquire (read) only those calculations required for
their particular application, as DRDY repeatedly indicates the availability of new data. Note again that
the user’s MCU firmware must reset the DRDY bit
to “0” before it can be asserted again.
Referring again to Figure 3, note that within the
Irms and Vrms data paths, prior to the square-root
16DS487PP4
CS5460A
operation, the instantaneous voltage/current data is
2
low-pass filtered by a Sinc
filter. Then the data is
decimated to every Nth sample. Because of the
2
Sinc
filter operation, the first output for each channel will be invalid (i.e. all RMS calculations are invalid in the ‘single computation cycle’ data
acquisition mode and the first RMS calculation results will be invalid in the ‘continuous computation
cycles’ data acquisition mode). However, all energy calculations will be valid since energy calcula-
2
tions do not require this Sinc
operation.
After the user issues the ’Start Conversions’ command to the CS5460A (see Section 3.1, Commands(Write Only)), and if the ‘C’ bit in this command is
set to a value of ‘1’, the device will remain in its ac-
tive state. Once commanded into continuous computationcyclesdataacquisitionmode,the
CS5460A will continue to perform A/D conversions on the voltage/current channels, as well as all
subsequentcalculations,untila)the‘Power-Up/Halt’ command is received through the serial
interface, or b) the device looses power, or c) the
RS bit in the Configuration Register is asserted by
the user (‘software reset’), or d) the /RESET pin is
asserted and then de-asserted (‘hardware reset’).
2.3 Basic Application Circuit
Configurations
Figure 6 shows the CS5460A connected to a service to measure power in a single-phase 2-wire system operating from a single power supply. Note
that in this diagram the shunt resistor used to monitor the line current is connected on the “Line” (hot)
side of the power mains. In most residential power
metering applications, the power meter’s current-sense shunt resistor is intentionally placed on
the ‘hot’ side of the power mains in order to help
detect any attempt by the subscriber to steal power.
In this type of shunt-resistor configuration, note
that the common-mode level of the CS5460A must
be referenced to the hot side of the power line. This
means that the common-mode potential of the
CS5460A will typically oscillate to very high positive voltage levels, as well as very high negative
voltage levels, with respect to earth ground potential. The designer must therefore be careful when
attempting to interface the CS5460A’s digital output lines to an external digital interface (such as a
LAN connection or other communication network). Such digital communication networks may
require that the CMOS-level digital interface to the
meter is referenced to an earth-ground. In such cases, the CS5460A’s digital serial interface pins mustbe isolated from the external digital interface, so
that there is no conflict between the ground references of the meter and the external interface. The
CS5460A and associate circuitry should be enclosed in a protective insulated case when used in
this configuration, to avoid risk of harmful electric
shock to humans/animals/etc.
Figure 7 shows how the same single-phase
two-wire system can be metered while achieving
complete isolation from the power lines. This isolation is achieved using three transformers. One
transformer is a general-purpose voltage transformer, used to supply the on-board DC power to
the CS5460A. A second transformer is a high-precision, low-impedance voltage transformer (often
called a ‘potential transformer’) with very little
roll-off/phase delay, even at the higher harmonics.
A current transformer is then used to sense the line
current. A burden resistor placed across the secondary of the current transformer creates the current-sense voltage signal, for the CS5460A’s
current channel inputs. Because the CS5460A is
not directly connected to the power mains, isolation
is not required for the CS5460A’s digital interface.
Figure 8 shows the CS5460A configured to measure power in a single-phase 3-wire system.In
many 3-wire residential power systems within the
United States, only the two Line terminals are
available (neutral is not available). Figure 9 shows
how the CS5460A can be configured to meter a
3-wire system when no neutral is available.
DS487PP417
CS5460A
N
120 VAC
R
2
To Service
Ω
5k
L
Ω
500
470 nF
R
1
R
*
R
I-
R
Shunt
*
R
I+
* Re fer to Input Pr otecti on
** Re fer to Input Fi ltering
*
V-
Ω
500
*
*
C
V+
**
C
V-
I+
0.1 µF
- Secti on 4.12
- Section 4.13
0.1 µF100 µF
9
**
C
Vdiff
10
15
**
C
Idiff
16
12
11
+
**
C
I-
**
C
Ω
10
14
VA+VD+
CS5460A
VIN+
VIN-
IIN-
NOTE: Currentchannel
inputm easures voltage
(just likevoltage input).
IIN+
VREFIN
VREFOUT
PFMON
CPUCLK
RESET
VA-DGND
134
XOUT
EOUT
XIN
SDI
SDO
SCLK
INT
EDIR
3
17
2
1
24
19
7
CS
23
6
5
20
22
21
0.1 µF
2.5 MHz to
20 MHz
ISOLATION
Me ch. C ounter
or
Stepper Mot or
10 k
Optional
Clock
Source
Ω
Serial
Data
Interface
Figure 6. Typical Connection Diagram (One-Phase 2-Wire, Direct Connect to Power Line)
N
120 VAC
To Service
L
Voltage
Transformer
M:1
Low Phase-Shift
Pot entia l Tr ansfo rmer
N:1
Current
Transformer
200
Ω
12 VAC
12 VAC
1k
Ω
1k
Ω
R
Burden
* Refer to Input Protection
** Re fer to I nput Fi lteri ng
+
*
R
V+
*
R
V-
1k
Ω
1k
Ω
R
200
200
µF
**
C
V+
**
C
V-
*
R
I-
C
C
*
I+
0.1 µF
- Section 4.12
- Secti on 4.13
Ω
5k
Ω
Ω
0.1µF
**
C
Vdiff
10
15
**
I+
**
C
Idiff
**
16
I-
12
11
10
14
VA+VD+
CS5460A
9
VIN+
VIN-
IIN-
NOTE: Currentchannel
inputmeasures voltage
(just likev oltage input).
IIN+
VREFIN
VREFOUT
VA-DGND
134
PFMON
CPUCL K
XOUT
XIN
RESET
SDI
SDO
SCLK
INT
EDIR
EOUT
3
17
2
1
24
19
7
CS
23
6
5
20
22
21
0.1 µF
2.5 MHz to
20 MHz
Mec h. C ounte r
or
Stepper Mo tor
10 k
Ω
Optional
Clock
Source
Serial
Data
Interface
Figure 7. Typical Connection Diagram (One-Phase 2-Wire, Isolated from Power Line)
3. SERIAL PORT OVERVIEW
The CS5460A's serial port incorporates a state machine with transmit/receive buffers. The state machine interprets 8 bit command words on the rising
edge of SCLK. Upon decoding of the command
word, the state machine performs the requested
command or prepares for a data transfer of the addressed register. Request for a read requires an internal register transfer to the transmit buffer, while
a write waits until the completion of 24 SCLKs before performing a transfer. The internal registers
are used to control the ADC's functions. All regis-
ters are 24-bits in length. Figure 25 summarizes the
internal registers available to the user.
The CS5460A is initialized and fully operational in
its active state upon power-on. After a power-on,
the device will wait to receive a valid command
(the first 8-bits clocked into the serial port). Upon
receiving and decoding a valid command word, the
state machine instructs the converter to either perform a system operation, or transfer data to or from
an internal register. The user should refer to the
“Commands” section to decode all valid commands.
DS487PP419
CS5460A
3.1 Commands (Write Only)
All command words are 1 byte in length. Commands that write to a register must be followed by 3 bytes of register
data. Commands that read from registers initiate 3 bytes of register data. Commands that read data can be ‘chained’
with other commands (e.g., while reading data, a new command can be sent to SDI which can execute before the
original read is completed). This allows for ‘chaining’ commands.
3.1.1 Start Conversions
B7B6B5B4B3B2B1B0
1110C000
This command indicates to the state machine to begin acquiring measurements and calculating results. The device
has two modes of acquisition.
CModes of acquisition/measurement
0 = Perform a single computation cycle
1 = Perform continuous computation cycles
3.1.2 SYNC0 Command
B7B6B5B4B3B2B1B0
11111110
This command is the end of the serial port re-initialization sequence. It can also be used as a NOP command. The
serial port is resynchronized to byte boundaries by sending three or more consecutive SYNC1 commands followed
by a SYNC0 command.
3.1.3 SYNC1 Command
B7B6B5B4B3B2B1B0
11111111
This command is part of the serial port re-initialization sequence. It can also serve as a NOP command.
3.1.4 Power-Up/Halt
B7B6B5B4B3B2B1B0
10100000
If the device is powered-down into either stand-by or sleep power saving mode (See 3.1.5), this command will power-up the device. After the CS5460 is initially powered-on, no conversions/computations will be running. If the device
is already powered on and the device is running either ‘single computation cycle’ or ‘continuous computation cycles’
data acquisition modes, all computations will be halted once this command is received.
20DS487PP4
CS5460A
3.1.5 Power-Down
B7B6B5B4B3B2B1B0
100S1S0000
The device has two power-down states to conserve power. If the chip is put in stand-by state, all circuitry except the
analog/digital clock generators is turned off. In the sleep state, all circuitry except the digital clock generator and the
instruction decoder is turned off. Waking up the CS5460A out of sleep state requires more time than waking the
device out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog clock signal.
[S1 S]0Power-down state
00 = Reserved
01 = Halt and enter stand-by power saving state. This state allows quick power-on time
10 = Halt and enter sleep power saving state. This state requires a slow power-on time
11 = Reserved
3.1.6 Calibration
B7B6B5B4B3B2B1B0
110VIRGO
The device has the capability of performing a system AC offset calibration, DC offset calibration, AC gain calibration,
and DC gain calibration. The user can calibrate the voltage channel, the current channel, or both channels at the
same time. Offset and gain calibrations should NOT be performed at the same time (must do one after the other).
For a given application, if DC gain calibrations are performed, then AC gain calibration should not be performed (and
vice-versa). The user must supply the proper inputs to the device before initiating calibration.
[V I]Designates calibration channel
00 = Not allowed
01 = Calibrate the current channel
10 = Calibrate the voltage channel
11 = Calibrate voltage and current channel simultaneously
RSpecifies AC calibration (R=1) or DC calibration (R=0)
GDesignates gain calibration
0 = Normal operation
1 = Perform gain calibration
ODesignates offset calibration
0 = Normal operation
1 = Perform offset calibration
DS487PP421
CS5460A
3.1.7 Register Read/Write
B7B6B5B4B3B2B1B0
0W/R
This command informs the state machine that a register access is required. On reads the addressed register is loaded into the output buffer and clocked out by SCLK. On writes the data is clocked into the input buffer and transferred
to the addressed register on the 24
RA4RA3RA2RA1RA0 0
th
SCLK.
W/R
Write/Read control
0 = Read register
1 = Write register
RA[4:0]Register address bits. Binary encoded 0 to 31. All registers are 24 bits in length.
AddressAbbreviationName/Description
00000ConfigConfiguration Register.
00001I
00010I
00011V
00100V
DCoffCurrent Channel DC Offset Register.
gnCurrent Channel Gain Register.
DCoffVoltage Channel DC Offset Register.
gnVoltage Channel Gain Register.
00101Cycle CountNumber of A/D cycles per computation cycle.
00110Pulse-RateUsed to set the energy-to-pulse ratio on EOUT
(and EDIR).
00111IInstantaneous Current Register (most recent current sample).
01000VInstantaneous Voltage Register (most recent voltage sample).
01001PInstantaneous Power Register (most recent power sample).
01010EEnergy Register (accumulated over latest computation cycle).
01011I
01100V
RMS
RMS
RMS Current Register (computed over latest computation cycle).
RMS Voltage Register (computed over latest computation cycle).
01101TBCTimebase Calibration Register.
01110PoffPower Offset Register.
01111StatusStatus Register.
10000I
10001V
† These registers are for Internal Use only and should not be written to.
22DS487PP4
CS5460A
3.2 Serial Port Interface
The CS5460A’s slave-mode serial interface consists of two control lines and two data lines, which
have the following pin-names: CS
SDO. Each control line is now described.
CS
Chip Select (input pin), is the control line
which enables access to the serial port. When CS
is set to logic 1, the SDI, SDO, and SCLK pins will
be held at high impedance. When the CS
to logic 0, the SDI, SDO, and SCLK pins have the
following functionality:
SDI Serial Data In (input pin), is the user-generated signal used to transfer (send) data/command/address/etc. bits into the device.
SDO Serial Data Out (output pin), is the data signal used to read output data bits from the device’s
registers.
SCLKSerial Clock (input pin), is the serial
bit-clock which controls the transfer rate of data
to/from the ADC’s serial port. To accommodate
opto-isolators,SCLKisdesignedwitha
Schmitt-trigger input to allow an opto-isolator with
slower rise and fall times to directly drive the pin.
Additionally, SDO is capable of sinking or sourcing up to 5 mA to directly drive an opto-isolator
LED. SDO will have less than a 400 mV loss in the
drive voltage when sinking or sourcing 5 mA.
,SCLK,SDI,
pin is set
3.3 Serial Read and Write
The state machine decodes the command word as it
is received. Data is written to and read from the
CS5460A by using the Register Read/Write command. Figure 1 illustrates the serial sequence necessary to write to or read from the serial port
buffers. As shown in Figure 1, a transfer of data is
always initiated by sending the appropriate 8-bit
command (MSB first) to the serial port (SDI pin).
It is important to note that some commands use information from the Cycle-Count Register and Configuration Register to perform the function. For
those commands, it is important that the correct information is written to those registers first.
3.3.1 Register Write
When a command involves a write operation, the
serial port will continue to clock in the data bits
(MSB first) on the SDI pin for the next 24 SCLK
cycles.Command words instructing a register
write must be followed by 24 bits of data. For instance, to write the Configuration Register, the user
would transmit the command (0x40) to initiate a
write to the Configuration Register. The CS5460A
will then acquire the serial data input from the
(SDI) pin when the user pulses the serial clock
(SCLK) 24 times. Once the data is received, the
state machine writes the data to the Configuration
Register and then waits to receive another valid
command.
3.3.2 Register Read
When a read command is initiated, the serial port
will start transferring register content bits (MSB
first) on the SDO pin for the next 8, 16, or 24 SCLK
cycles. Command words instructing a register read
may be terminated at 8-bit boundaries (e.g., read
transfers may be 8, 16, or 24 bits in length). Also
data register reads allow “command chaining”.
This means that the micro-controller is allowed to
send a new command while reading register data.
The new command will be acted upon immediately
and could possibly terminate the first register read.
For example, if a command word is sent to the state
machine to read one of the output registers, then after the user pulses SCLK for 16-bits of data, a second write command word (e.g., to clear the Status
Register) may be pulsed on to the SDI line at the
same time the last 8-bits of data (from the first read
command) are pulsed from the SDO line. As another example, suppose that the user is only interested in acquiring the 16-most significant bits of
data from the first read. In this case, the user can
begin to strobe a second read command on SDI after the first 8 data bits have been read from SDO.
DS487PP423
CS5460A
During the read cycle, the SYNC0 command
(NOP) should be strobed on the SDI port while
clocking the data from the SDO port.
3.4 System Initialization
A software or hardware reset can be initiated at any
time. The software reset is initiated by writing a
logic 1 to the RS (Reset System) bit in the Configuration Register, which automatically returns to
logic 0 after reset. At the end of the 32ndSCLK
(i.e., 8 bit command word and 24 bit data word) internal synchronization delays the loading of the
Configuration Register by 3 or 4 DCLK cycles.
Then the reset circuit initiates the reset routine on
st
the 1
A hardware reset is initiated when the RESET
is forced low for at least 50 ns. The RESET
is asynchronous, requiring no MCLKs for the part
to detect and store a reset event. The RESET
a Schmitt Trigger input, which allows it to accept
slow rise times and/or noisy control signals. (It is
not uncommon to experience temporary periods of
abnormally high noise and/or slow, gradual restoration of power, during/after a power “black-out”
or power “brown-out” event.)Once the RESET
pin is de-asserted, the internal reset circuitry remains active for 5 MCLK cycles to insure resetting
the synchronous circuitry in the device. The modulators are held in reset for 12 MCLK cycles after
RESET
reset, the internal registers (some of which may
drive output pins) will be reset to their default values
on the first MCLK received after detecting a reset
event (see Table 3). The CS5460A will then assume
its
other possible power states of the CS5460A, are describedinSection3.6).
falling edge of MCLK.
is de-asserted
active
state. (The term
pin
signal
pin is
. After a hardware or software
active state
,aswellasthe
The reader should refer to Section 5 for a complete
description of the registers listed in Table 3.
Configuration Register:0x000001
DC offset registers:0x000000
Gain registers0x400000
Pulse-Rate Register:0x0FA000
Cycle-Counter Register:0x000FA0
Timebase Register:0x800000
Status Register:(see Section 5)
Mask Register:0x000000
Control Register:0x000000
AC offset registers:0x000000
Power Offset Register:0x000000
All data registers:0x000000
All unsigned data registers0x000000
Table 3. Default Register Values upon Reset Event
3.5 Serial Port Initialization
It is possible for the serial interface to become unsynchronized with respect to the SCLK input. If
this occurs, any attempt to clock valid CS5460A
commands into the serial interface will result in either no operation or unexpected operation because
the CS5460A will not interpret the input command
bits correctly. The CS5460A’s serial port must then
be re-initialized. To initialize the serial port, any of
the following actions can be performed:
1) Power on the CS5460A. (Or if the device is already powered on, recycle the power.)
2) Hardware Reset.
3) Issue the Serial Port Initialization Sequence,
which is performed by clocking 3 (or more)
SYNC1 command bytes (0xFF) followed by
one SYNC0 command byte (0xFE) to the serial
interface.
24DS487PP4
CS5460A
3.6 CS5460A Power States
Active state denotes the operation of CS5460A
when the device is fully powered on (i.e., not in
sleep state or stand-by state). Performing any of
the following actions will insure that the CS5460A
is operating in the active state:
1) Power on the CS5460A. (Or if the device is already powered on, recycle the power.)
2) Hardware Reset
3) Software Reset
In addition to the three actions listed above, note
that if the device is operating in sleep state or
stand-by state, the action of waking up the device
out of sleep state or stand-by state (by issuing the
Power-Up/Halt command) will also insure that the
device is set into active state. But remember that in
order to send the Power-Up/Halt command to the
device, the user must be sure that the serial port has
already been (or is still) initialized. Therefore, if
there are situations in which the user wants to wake
the CS5460A out of sleep state or stand-by state,
successful wake-up of the device will be insured if
the serial port initialization sequence is written to
the serial interface, prior to writing the Power-Up/Halt command.
For a description of the sleep power state and the
stand-by power state, see the Power Down Command, located in Section 3.1.
DS487PP425
CS5460A
4. FUNCTIONAL DESCRIPTION
4.1 Pulse-Rate Output
As an alternative to reading the real energy through
the serial port, the EOUT
simple interface with which signed energy can be
accumulated. Each EOUT
termined quantity of energy. The quantity of energy represented in one pulse can be varied by
adjusting the value in the Pulse-Rate Register.
Corresponding pulses on the EDIR output pin signify that the sign of the energy is negative. Note
that these pulses are not influenced by the value of
the Cycle-Count Register, and they have no reliance on the computation cycle, described earlier.
With MCLK = 4.096 MHz, K = 1, the pulses will
have an average frequency (in Hz) equal to the frequency setting in the Pulse Rate Register when the
input signals into the voltage and current channels
cause full-scale readings in the Instantaneous Voltage and Current Registers. When MCLK/K is not
equal to 4.096 MHz, the user should scale the
pulse-rate that one would expect to get with
MCLK/K = 4.096 MHz by a factor of 4.096 MHz /
(MCLK / K) to get the actual output pulse-rate.
EXAMPLE #1: Suppose thatwe want the
pulse-frequency on the EOUT pin to be ‘IR’ = 100
pulses per second (100 Hz) when the RMS-voltage/RMS-current levels on the power line are
220 V and
15 A respectively, noting that the max-
imum rated levels on the power line are 250 V and
20 A. We also assume that we have calibrated the
CS5460A voltage/current channel inputs such that
a DC voltage level of 250 mV across the voltage/current channels will cause full-scale readings
of 1.0 in the CS5460A Instantaneous Voltage and
Current Registers as well as in the RMS-Voltage
and RMS-Current Registers. We want to find out
what frequency value we should put into the
CS5460A’s Pulse-Rate Register (call this value
‘PR’) in order to satisfy this requirement. Our first
step is to set the voltage and current sensor gain
and EDIR pins provide a
pulse represents a prede-
constants, K
V and KI, such that there will be accept-
able input voltage levels on the inputs when the
power line voltage and current levels are at the
maximum values of 250 V and 20 A, respectively.
We need to calculate KV and KI in order to determine the appropriate ratios of the voltage/current
transformers and/or shunt resistor values to use in
the front-end voltage/current sensor networks.
We assume here that we are dealing with a sinusoidal AC power signal. For a sinewave, the largest
RMS value that can be accurately measured (without over-driving the inputs) will register at ~0.7071
of the maximum DC input level. Since power signals are often not perfectly sinusoidal in real-world
situations, and to provide for some over-range capability, we will set the RMS Voltage Register and
RMS Current Register to measure at 0.6 when the
RMS-values of the line-voltage and line-current
levels are at 250 V and 20 A. Therefore, when the
RMS registers measure 0.6, the voltage level at the
inputs will be 0.6 x 250 mV = 150 mV. We now
find our sensor gain constants, K
V and KI,byde-
manding that the voltage and current channel inputs should be at 150 mV RMS when the power
line voltage and current are at the maximum values
of 250 V and 20 A.
K
V = 150 mV / 250 V = 0.0006
I = 150 mV / 20 A = 0.0075 Ω
K
These sensor gain constants can help determine the
ratios of the transformer or resistor-divider sensor
networks. We now use these sensor gain constants
to calculate what the input voltage levels will be on
the CS5460A inputs when the line-voltage and
line-current are at 220 V and 15 A. We call these
values V
Vnom and VInom.
VVnom =KV * 220 V = 132 mV
Inom =KI * 15 A = 112.5 mV
V
The pulse rate on EOUT
will be at ‘PR’ pulses per
second (Hz) when the RMS-levels of voltage/current inputs are at 250 mV. When the voltage/cur-
26DS487PP4
CS5460A
rent inputs are set at VVnom and VInom,wewantthe
pulse rate to be at ‘IR’ = 100 pulses per second. IR
will be some percentage of PR. The percentage is
defined by the ratios of V
V
Inom/250 mV with the following formula:
PulseRateIRPR
Vnom/250 mV and
Vnom
V
Inom
------------- ----250mV
V
---------- --------
⋅⋅==
250mV
We can rearrange the above equation and solve for
PR.This is the value that we put into the
Pulse-Rate Register.
Therefore we set the Pulse-Rate Register to
~420.875 Hz. Therefore, the Pulse-Rate Register
would be set to 0x00349C.
The above equation is valid when current channel
is set to x10 gain. If current channel gain is set to
x50, then the equation becomes:
----------- ------------ ------------- -----=
V
Vnom
------------ ------
250mV
IR
V
--------- ------
×
50mV
Inom
PR
where it is assumed that the current channel has
been calibrated such that the Instantaneous Current
Register will read at full-scale when the input voltage across the IIN+ and IIN- inputs is 50 mV (DC).
ation, the nominal line voltage and current do not
determine the appropriate pulse-rate setting.Instead, the maximum line-voltage and line-current
levels must be considered. We use the given maximum line-voltage and line-current levels to determine K
V and KI as previously described to get:
K
V = 150 mV / 250 V = 0.0006
K
I = 150 mV / 20 A = 0.0075 Ω
where we again have calculated our sensor gains
such that the maximum line-voltage and line-current levels will measure as 0.6 in the RMS Voltage
Register and RMS Current Register.
We can now calculate the required Pulse-Rate Register setting by using the following equation:
PR500
pulses
--------- --------kW hr⋅
------------ --
⋅⋅ ⋅ ⋅=
3600s
1hr
----------- ------1000W
----------- -------
250mV
--------- ---------
K
V
K
I
250mV
1kW
Therefore PR = ~1.929 Hz.
Note that the Pulse-Rate Register cannot be set to a
frequency of exact 1.929 Hz. The closest setting
thatthePulse-RateRegistercanobtainis
0x00003E = 1.9375 Hz. To improve the accuracy,
either gain register can be programmed to correct
for the round-off error in PR. This value would be
calculated as
PR
Ign or Vgn
----------- --
1.929
1.00441≅0x404830==
EXAMPLE #2: Suppose that instead of being given a desired frequency of pulses per second to be issued at a specific voltage/current level, we are
given a desired number of pulses per unit energy to
be present at EOUT,
given that the maximum
line-voltage is at 250 V (RMS) and the maximum
line-current is at 20 A (RMS). For example, suppose that the required number of pulses per kW-hr
In the last example, suppose that the designer must
use a value for MCLK/K of 3.05856MHz. When
MCLK/K is not equal to 4.096MHz, the result for
‘PR’ that is calculated for the Pulse-Rate Register
mustbescaledby acorrectionfactorof:
4.096MHz / (MCLK/K). In this case we would
scale the result by 4.096/3.05856 to get a final PR
result of ~2.583 Hz.
is specified to be 500 pulses/kW-hr. In such a situ-
DS487PP427
CS5460A
4.2 Pulse Output for Normal Format,
Stepper Motor Format and Mechanical
Counter Format
The duration and shape of the pulse outputs at the
EOUT
and EDIR pins can be set for three different
output formats. The default setting is for Normal
output pulse format. When the pulse is set to either
of the other two formats, the time duration and/or
the relative timing of the EOUT
and EDIR pulses is
increased/varied such that the pulses can drive either an electro-mechanical counter or a stepper motor. The EOUT
and EDIR output pins are capable
ofdrivingcertainlow-voltage/low-power
counters/stepper motors directly. This depends on
the drive current and voltage level requirements of
the counter/motor. The ability to set the pulse output format to one of the three available formats is
controlled by setting certain bits in the Control
Register.
4.2.1 Normal Format
Referring to the description of the Control Register
in Section 5., REGISTER DESCRIPTION, if both
the MECH and STEP bits are set to ‘0’, the pulse
output format at the EOUT
trated in Figure 10. These are active-low pulses
with very short duration. The pulse duration is an
integer multiple of MCLK cycles, approximately
equal to 1/16 of the period of the contents of the
Pulse-Rate Register. However for Pulse-Rate Register settings less than the sampling rate (which is
[MCLK/8]/1024), the pulse duration will remain at
and EDIR pins is illus-
a constant duration, which is equal to the duration
of the pulses when the Pulse-Rate Register is set to
[MCLK/K]/1024. The maximum pulse frequency
from the EOUT pin is therefore [MCLK/K]/16.
When energy is positive, EDIR
When energy is negative, EDIR
put as EOUT
.When MCLK/K is not equal to
is always high.
has the same out-
4.096 MHz, the user can predict the pulse-rate by
first calculating what the pulse-rate would be if a
4.096MHz crystal is used (with K=1) and then scaling the result by a factor of (MCLK/K) /
4.096MHz.
When set to run in Normal pulse output format, the
pulses may be sent out in “bursts” depending on
both the value of the Pulse-Rate Register as well as
the amount of billable energy that was registered by
the CS5460 over the most recent A/D sampling period, which is (in Hz): 1 / [(MCLK/K) / 1024]. A
running total of the energy accumulation is maintained in an internal register (not accessible to the
user) inside the CS5460A. If the amount of energy
that has accumulated in this register over the most
recent A/D sampling period is equal to or greater
than the amount of energy that is represented by
one pulse, the CS5460A will issue a “burst” of one
or more pulses on EOUT (and also possibly on
EDIR
). The CS5460A will issue as many pulses as
are necessary to reduce the running energy accumulation value in this register to a value that is less
than the energy represented in one pulse.If the
amount of energy that has been registered over the
most recent sampling period is large enough that it
Positive Energy BurstNegative Energy Burst
...
EOUT
...
EDIR
Figure 10. Time-plot representation of pulse output for a typical burst of pulses (Normal Format)
28DS487PP4
t
Pulse-Rate Register Period
t
=
16
=
2
n
x
(MCLK / K)
for Integer n
...
...
EOUT
EDIR
128 ms
...
128 ms
...
Positive Energy
Figure 11. Mechanical Counter Format on EOUT and EDIR
Negative Energy
CS5460A
...
...
cannot be expressed with only one pulse, then a
burst of pulses will be issued, possibly followed by
a period of time during which there will be no pulses, until the next A/D sampling period occurs. After the pulse or pulses are issued, a certain residual
amount of energy may be left over in this internal
energy accumulation register, which is always less
(in magnitude) than the amount of energy represented by one pulse. In this situation, the residual
energy is not lost or discarded, but rather it is maintained and added to the energy that is accumulated
during the next A/D conversion cycle. The amount
of residual energy that can be left over becomes
larger as the Pulse-Rate Register is set to lower and
lower values, because lower Pulse-Rate Register
values correspond to a higher amount of energy per
pulse (for a given calibration).
4.2.2 Mechanical Counter Format
Setting the MECH bit in the Control Register to ‘1’
and the STEP bit to ‘0’ enables wide-stepping pulses for mechanical counters and similar discrete
counter instruments. In this format, active-low
pulses are 128 ms wide when using a 4.096 MHz
crystal and K=1. When energy is positive, the pulses appear on EOUT
pulses appear on EDIR
that pulses will not occur at a rate faster than the
. When energy is negative,
. It is up to the user to insure
128 ms pulse duration, or faster than the mechanical counter can accommodate. This is done by verifying that the Pulse-Rate Register is set to an
appropriate value. Because the duration of each
pulse is set to 128 ms, the maximum output pulse
frequency is limited to ~7.8 Hz (for MCLK/K =
4.096 MHz). For values of MCLK / K different
than 4.096 MHz, the duration of one pulse is (128
* 4.096 MHz)/(MCLK / K) milliseconds. See
Figure 11 for a diagram of the typical pulse output.
4.2.3 Stepper Motor Format
Setting the STEP bit in the Control Register to ‘1’
and the MECH bit to ‘0’ transforms the EOUT
EDIR
pins into two stepper motor phase outputs.
When enough energy has been registered by the
CS5460A to register one positive/negative energy
pulse, one of the output pins (either EOUT
EDIR
) changes state. When the CS5460A must issue another energy pulse, the other output changes
state. The direction the motor will rotate is determined by the order of the state changes. When energy is positive, EOUT will lead EDIR such that
the EOUT
pulse train will lead the EDIR pulse train
by ~1/4 of the periods of these two pulse train signal. When energy is negative, EDIR
EOUT
in a similar manner. See Figure 12.
and
or
will lead
EOUT
EDIR
DS487PP429
...
...
Positive EnergyNegative Energy
Figure 12. Stepper Motor Format on EOUT and EDIR
...
...
CS5460A
4.3 Auto-Boot Mode Using EEPROM
The CS5460A has a MODE pin. When the MODE
pin is set to logic low, the CS5460A is in normal
operating mode, called host mode. This mode denotes the normal operation of the part, that has been
described so far. But when this pin is set to logic
high, the CS5460A auto-boot mode is enabled. In
auto-boot mode, the CS5460A is configured to request a memory download from an external serial
EEPROM. The download sequence is initiated by
driving the RESET
pin to logic high. Auto-Boot
mode allows the CS5460A to operate without the
need for a microcontroller. Note that if the MODE
pin is left unconnected, it will default to logic low
because of an internal pull-down on the pin.
4.3.1 Auto-Boot Configuration
Figure 13 shows the typical connections between
the CS5460A and a serial EEPROM for proper auto-boot operation. In this mode, CS
driven outputs. SDO is always an output. During
the auto-boot sequence, the CS5460A drives CS
low, provides a clock output on SCLK, and drives
out-commands on SDO. It receives the EEPROM
data on SDI. The serial EEPROM must be pro-
and SCLK are
grammed with the user-specified commands and
register data that will be used by the CS5460A to
change any of the default register values (if desired) and begin conversions.
Figure 13 also shows the external connections that
would be made to a calibrator device, such as a PC
or custom calibration board. When the metering
system is installed, the calibrator would be used to
control calibration and/or to program user-specified commands and calibration values into the EEPROM.The user-specified commands/data will
determine the CS5460A’s exact operation, when
the auto-boot initialization sequence is running.
Any of the valid commands can be used.
4.3.2 Auto-Boot Data for EEPROM
This section illustrates what a typical set of code
would look like for an auto-boot sequence. This
code is what would be written into the EEPROM
by the user. In the sequence below, the EEPROM
is programmed so that it will first send out commands that write calibration values to the calibration registers inside the CS5460A. This is followed
by the commands used to set (write) the desired
Pulse-Rate Register value, and also to un-mask the
VD+
5K
30DS487PP4
CS5460A
MODE
Figure 13. Typical Interface of EEPROM to CS5460A
/EOUT
/EDIR
SCK
SDI
SDO
/CS
Mech. Counter
or
Stepp er Motor
5K
Connector to
Calibrator
EEPROM
SCK
SO
SI
/CS
CS5460A
‘LSD’ status bit in the Mask Register (the purpose
for this action is described in section ). Finally, the
EEPROM code will initiate ‘continuous computation cycles’ data acquisition mode and select one of
the alternate pulse-output formats (e.g., set the
MECH bit in the Control Register). The serial data
for such a sequence is shown below in single-byte
hexidecimal notation:
This data from the EEPROM will drive the SDI pin
of the CS5460A during the auto-boot sequence.
The following sequence of user-controlled events
will cause the CS5460A to execute the auto-boot
mode initialization sequence: (A simple timing diagram for this sequence is shown below in
Figure 14.) If the MODE pin is set to logic high (or
if the MODE pin was set/tied to logic high during/after the CS5460A has been powered on), then
changing the RESET
pin from active state to inactive state (low to high) will cause the CS5460A to
drive the CS
pin low, and after this, to issue the standardEEPROMblock-readcommandonthe
CS5460A’s SDO line. Once these events have completed, the CS5460A will continue to issue SCLK
pulses, to accept data/commands from the EEPROM. The serial port will become a
master
-mode
interface. For a more detailed timing diagram, see
SWITCHING CHARACTERISTICS
(in
Section 1
.)
4.3.3 Which EEPROMs Can Be Used?
Several industry-standard serial EEPROMs that
will successfully run auto-boot with the CS5460A
are listed below:
•AtmelAT25010
AT25020
AT25040
•National SemiconductorNM25C040M8
NM25020M8
•XicorX25040SI
MODE
RES
CS
SCLK
SDO
SDI
DS487PP431
EE ReadAddress 0
5460ACommandsStop
Figure 14. Timing Diagram for Auto-Boot Sequence
CS5460A
These types of serial EEPROMs expect a specific
8-bit command word (00000011) in order to perform a memory download. The CS5460A has been
hardware programmed to transmit this 8-bit command word to the EEPROM at the beginning of the
auto-boot sequence.
The auto-boot sequence is terminated by writing a
‘1’ to the STOP bit in the CS5460A’s Control Register. This action is performed as the last command
in the EEPROM command sequence. At the completion of the write to the Control Register (provided STOP bit = “1”), SCLK stops, and CS
rises,
thereby reducing power consumed by the EEPROM. At completion of the Auto-Boot sequence,
the serial port will revert to functioning as a
slave-mode interface.Therefore, if desired, the
CS5460A registers can still be read by an external
device, such as a central office controller, connected to the meter assembly by a bus interface.
When the CS5460A is commanded by the EEPROM to perform a certain operation, the operation will not be pre-maturely terminated by the
assertion of the Control Register’s STOP bit. In the
above example, the ‘Start Conversions’ command
(0xE8) is issued from the EEPROM, and therefore
the CS5460A will continue to perform continuous
A/D conversions even after the STOP bit is asserted.Auto-Boot Reset during Brown-Out/Black-Out
Conditions
The power line that is to be metered may enter a
black-out or brown-out condition at certain times,
due to problems at the power plant or other environmental conditions (ground fault, electrical
storms, etc.) In such conditions, it is important for
the meter assembly to accomplish a proper reset, so
that it can continue normal metering operations
once the line power is restored.When the
CS5460A is controlled by a microcontroller, the
microcontroller is typically programmed (by the
user) to handle these power-fail-reset situations. In
the case of auto-boot, the CS5460A may be expected to reset itself (by re-executing the Auto-Boot se-
quence) whenever the line-power is restored.
Figure 15 shows a reasonably reliable way to configure the CS5460A’s RESET
and INT pins so that
CS5460A to restart the Auto-Boot sequence after a
brown-out or black-out condition. This configuration employs a diode, a resistor, and a capacitor on
the RESET pin in attempt to allow the CS5460A to
reboot after a sudden loss of power, followed by a
reinstatement of power.
Note in the above auto-boot example code set (see
Section 4.3.2) that the LSD bit is un-masked, in order to cause a high-to-low transition on the INT
pin
whenever the PFMON low-supply threshold is
reached on the PFMON pin. If a power supply loss
condition is sensed on PFMON, then the INT
pin is
asserted to low (because LSD is un-masked), which
allows the BAT85 diode to quickly drain the charge
BOOT. But whenever the +5V power is restored,
on C
the resistor-capacitor network will force RESET
to
recharge slowly. The slow rise-time on the RESET
pin can help to allow the oscillator circuitry and the
CS5460A’s internal reference circuitry enough
time to stabilize before the device attempts to
re-execute with the Auto-Boot sequence. This will
allow the CS5460A to resume its normal metering
operations after power is restored. (User must provide suitable resistor divider configuration on the
PFMON pin, see Figure 15.) Use of this configuration does not guarantee that the CS5460A will resetproperly,whenexposedtoanysudden
disturbance in power.
In addition to the configuration described above,
thedesignershouldincludesizeablecommon-mode capacitors to the VA+/VD+ pins (see
Figure 15). Such capacitance on the analog/digital
power supply pins will increase the amount of time
over which the CS5460A will remain operational
after power is lost, which therefore increases the
chances that the CS5460A will successfully re-execute a proper reboot upon restoration of power.
Suggested values are >47 µF (per pin) or >100 µF
(total).
32DS487PP4
CS5460A
4.4 Interrupt and Watchdog Timer
4.4.1 Interrupt
The INT pin is used to indicate that an event has
taken place in the CS5460A that (may) need attention. These events inform the meter system about
operation conditions and internal error conditions.
The INT signal is created by combining the Status
Register with the Mask Register. Whenever a bit in
the Status Register becomes active, and the corresponding bit in the Mask Register is a logic 1, the
signal becomes active.
INT
4.4.1.1 Clearing the Status Register
Unlike the other registers, the bits in the Status
Register can only be cleared (set to logic 0). When
a word is written to the Status Register, any 1s in
the word will cause the corresponding bits in the
Status Register to be cleared. The other bits of the
Status Register remain unchanged. This allows the
clearing of particular bits in the register without
having to know the state of the other bits. This
mechanism is designed to facilitate handshaking
and to minimize the risk of losing events that haven’t been processed yet.
4.4.1.2 Typical use of the INT pin
The steps below show how interrupts can be handled by the on-board MCU.
•Initialization:
Step I0 - All Status bits are cleared by writing
FFFFFF (Hex) into the Status Register.
Step I1 - The conditional bits which will be
used to generate interrupts are then written to
logic 1 in the Mask Register.
Step I3 - Enable interrupts.
•Interrupt Handler Routine:
Step H0 - Read the Status Register.
Step H1 - Disable all interrupts.
Step H2 - Branch to the proper interrupt service
routine.
N
LOAD
L
T2
47 uF
AGND
T1
AGND
AG
+
ND
4.096 MHz
CRYSTAL
AGND
+5V
VA+ VD+
PFMON
VIN+
VIN-
CS5460A
IIN+
IIN-
XIN
XOUT
REFIN
REFOUT
VA-DGND
Mode
EOUT
EDIR
INT
RESET
DGND
+5V
10k
30uF
SPI
+
+
C
47 uF
BOOT
DGND
E2PROM
BAT85
00000
TOTALIZER
DGND
This resistor-capacitor- diode
configuration helps to ensure a
smooth power-down, as well as
a proper power-up/reset during
and after a power black-out or
brown-out event.
Figure 15. CS5460A Auto-Boot Configuration: Automatic Restart After Power Failure
DS487PP433
CS5460A
Step H3 - Clear the Status Register by writing
back the value read in step H0.
Step H4 - Re-enable interrupts.
Step H5 - Return from interrupt service routine.
This handshaking procedure insures that any
new interrupts activated between steps H0 and
H3 are not lost (cleared) by step H3.
4.4.1.3 INT Active State
The behavior of the INT pin is controlled by the SI1
and SI0 bits of the Configuration Register. The pin
can be active low (default), active high, active on a
return to logic 0 (pulse-low), or active on a return
to logic 1 (pulse-high).
If the interrupt output signal format is set for either
active-high or active-low assertion, the interrupt
condition is cleared when the bits of the Status
Register are returned to their inactive state. If the
interrupt output signal format is set for either
pulse-high or pulse-low, note that the duration of
the INT
although in some cases the pulse may last for 2
MCLK/K cycles.
pulse will be at least one MCLK/K cycle,
4.4.1.4 Exceptions
The IC (Invalid Command) bit of the Status Register can only be cleared by performing the port initialization sequence. This is also the only Status
Register bit that is active low.
To properly clear the WDT (Watch Dog Timer) bit
of the Status Register, first read the Energy Register, then clear the bit in the Status Register.
4.4.2 Watch Dog Timer
The Watch Dog Timer (WDT) is provided as a
means of alerting the system that there is a potential
breakdown in communication with the microcontroller. By allowing the WDT to cause an interrupt,
a controller can be brought back, from some unknown code space, into the proper code for processing the data created by the converter. The
time-out is preprogrammed to approximately 5 seconds. The countdown restarts each time the Energy
Register is read. Under typical situations, the Energy Register is read every second. As a result, the
WDT will not time out. Other applications that use
the watchdog timer will need to ensure that the Energy Register is read at least once in every 5 second
span.
4.5 Oscillator Characteristics
XIN and XOUT are the input and output, respectively, of an inverting amplifier to provide oscillation and can be configured as an on-chip oscillator,
as shown in Figure 16. The oscillator circuit is designed to work with a quartz crystal or a ceramic
resonator. To reduce circuit cost, two load capacitors C1 are integrated in the device, one between
XIN and DGND, one between XOUT and DGND.
Lead lengths should be minimized to reduce stray
capacitance. With these load capacitors, the oscillator circuit is capable of oscillation up to 20 MHz,
if +5V is used for VD+. Note that for VD+ =
+3.3V, the maximum crystal frequency that can be
used is 5 MHz.
To drive the device from an external clock source,
XOUT should be left unconnected while XIN is
driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works
with sinusoidal inputs so there are no problems
with slow edge times.
The CS5460A can be driven by a clock ranging
from 2.5 to 20 MHz. The user must appropriately
set the K divider value such that MCLK/K will be
some value between 2.5 MHz and 5 MHz. The K
divider value is set with the K[3:0] bits in the Configuration Register.As an example, if XIN =
MCLK = 15 MHz, and K is set to 5, then MCLK/K
= 3 MHz, which is a valid value for MCLK/K.
Note that if the K[3:0] bits are all set to zero, the
value of the K divider value is 16.
34DS487PP4
CS5460A
4.6 Analog Inputs
The CS5460A accommodates a full-scale differential input voltage range of
channels. (If the PGA setting on the current channel is set for the 50x gain setting instead of the 10x
gain setting, then the differential full-scale input
range on the current channel reduces to ±50 mV.)
XOUT
XIN
DGND
Figure 16. Oscillator Connection
±250 mV on both input
C1
C2
C1 =22 pF
Oscillator
Circuit
C2 =
System calibration can be used to increase or decrease the full scale span of the converter as long as
the calibration register values stay within the limits
specified. See Section 4.8, Calibration,formore
details.
4.7 Voltage Reference
The CS5460A is specified for operation with a
+2.5 V reference between the VREFIN and VApins. A reference voltage must be supplied to the
VREFIN pin for proper operation of the two ADCs.
The CS5460A includes an internal 2.5 V reference,
available on the VREFOUT pin, that can be used as
the reference input voltage by connecting the VREFOUT pin to the VREFIN pin.
The VREFOUT Temperature Coefficient spec (for
the on-chip voltage reference) indicated in Section
1 of this data sheet is now described. A plot of the
VREFOUT Voltage vs. Temperature characteristic
for a typical CS5460A sample is shown in Figure
17. Note the general shape of this characteristic is
Figure 17. VREFOUT Voltage vs. Temperature characteristic for a typical CS5460A sample.
DS487PP435
CS5460A
an upside-down parabola. The TVREFOUT for any
particular CS5460A sample is derived from that
sample’s individual VREFOUT Voltage vs. Temperature characteristic.Using the data from the
sample’s VREFOUT Voltage vs. Temperature
characteristic, two lines are calculated, each of
which is defined by two significant data points
along this characteristic.The first line is determined by connecting the VREFOUT data point
taken at T = -40°C to the VREFOUT data point located at the peak of the characteristic (i.e., the top
of the parabola). The second line is defined by connecting the VREFOUT data point located at the
peak of the characteristic to the VREFOUT data
point taken at T = +80°C. Determine (in units of
ppm/°C) the slopes of these two lines. The higher
of these two slopes is the VREFOUT Temperature
Coefficient.
The VREFOUT Temperature Coefficient (tempco)
foragivenCS5460Asampleistypically
25 ppm/°C of drift.The maximum VREFOUT
TemperatureCoefficientthatanyparticular
CS5460Asamplewillexhibitistypically
60 ppm/°C of drift. But this maximum VREFOUT
tempco value is not guaranteed. If higher accuracy/stability is required, an external reference can be
used, in which case the VREFOUT pin can be left
unconnected.
In some cases, the designer may prefer to characterize the energy registration drift of the entire device over temperature, as opposed to the drift of the
voltage reference only. A “Device-Level Energy
Registration Temperature Coefficient” (referred to
as T
Edevice) can be defined in accordance with the
temperature coefficient requirement specified in
the IEC 1036/687 Standard.[Specifically, this
Edevice specification is defined as the CS5460A’s
T
maximum “mean temperature coefficient” (as defined in IEC1036, Section 4.6.3) over the temperature range specified per the “Limit range of
operation” for Outdoor Meters (see IEC 1036, Sec-tion 4.3.1)]. Instead of using the VREFOUT Voltage vs. Temperature characteristic, TEdevice is
based on the device’s Energy Registration Drift vs.
Temperature characteristic (for any particular
CS5460A sample), which indicates the drift of the
device’s energy registration drift over temperature,
using either the registration of the device’s energy-to-pulse engine or the Energy Register. Note
that typically this characteristic will have a shape
that is roughly similar to the shape to the sample’s
VREFOUT vs. Temperature Characteristic
in Figure 17. T
Edevice is defined as the greatest slope
, shown
of all possible lines that are defined by connecting
any two data points which lie along the Energy
Registration Drift vs. Temperature characteristic
such that 1) the two data points are separated by a
span of 20 degrees (Celsius) and 2) the temperature
value at the mid-point of the 20-degree span must
be within the temperature range between T = -25°C
and T = +60°C.
4.8 Calibration
4.8.1 Overview of Calibration Process
The CS5460A offers digital calibration. The user
determines which calibration sequence will be executed by setting/clearing one or more of the 8 bits
in the calibration command word. For both channels, there are calibration sequences for both AC
and DC purposes. Regardless of whether an AC or
DC calibration sequence is desired, there are two
basic types of calibrations: system offset and system gain. When the calibration sequences are being performed by the CS5460A, the user must
supply the input calibration signals to the “+” and
“-” pins of the voltage-/current-channel inputs.
Theseinputcalibrationsignalsrepresent
full-scale levels (for gain calibrations) and ground
input levels (for offset calibrations).
The AC and DC calibration sequences are differenct. Depending on the user’s specific metering
application and accuracy requirements, some or all
of the calibration sequences may not be executed
by the user. (This is explained in more detail in the
following paragraphs). In order to help the reader
to better understand the functionality of each cali-
36DS487PP4
CS5460A
bration sequence, we first define the various calibration registers within the CS5460A.
4.8.2 The Calibration Registers
Refer to Figure 3 and Figure 25.
Voltage Channel DC Offset Register and Current Channel DC Offset Register - Store additive
correction values that are used to correct for DC
offsets which may be present on the voltage/current
channels within the entire meter system.These
registers are updated by the CS5460A after a DC
offset calibration sequence has been executed.
Voltage Channel Gain Register and Current
Channel Gain Register - Store the multiplicative
correction values determined by the full-scale gain
calibration signals that are applied (by the user) to
the meter’s voltage/current channels. These registers are updated by the CS5460A after either an AC
or DC gain calibration sequence has been executed.
Voltage Channel AC Offset Register and Current Channel AC Offset Register - Store additive
offset correction values that are used to correct for
AC offsets which may be created on the voltage/current channels within the entire meter system. Although a noise signal may have an average
value of zero [no DC offset] the noise may still
have a non-zero rms value, which can add an undesirable offset in the CS5460A’s Irms and Vrms results. These registers are updated by the CS5460A
after an AC offset calibration sequence has been
executed.
Referring to Figure 3, one should note that the AC
offset registers affect the output results differently
than the DC offset registers. The DC offset values
are applied to the voltage/current signals very early
in the signal path; the DC offset register value affects all CS5460A results. This is not true for the
AC offset correction. The AC offset registers only
affect the results of the rms-voltage/rms-current
calculations.
Referring to Figure 3, the reader should note that
there are separate calibration registers for the AC
and DC offset corrections (for each channel). This
is not true for gain corrections, as there is only one
gain register per channel--AC and DC gain calibration results are stored in the same register. The results in the gain registers reflect either the AC or
DC gain calibration results, whichever was performed most recently. Therefore, both a DC and
AC offset can be applied to a channel at the same
time, but only one gain calibration can be applied
to each channel. The user must decide which type
of gain calibration will be used: AC or DC, but not
both.
To summarize, for both the voltage channel and the
current channel, while the AC offset calibration sequence performs an entirely different function than
the DC offset calibration sequence, the AC gain
and DC gain calibration sequences perform the
same function (but they accomplish the function
using different techniques).
Since both the voltage and current channels have
separate offset and gain registers associated with
them, system offset or system gain can be performed on either channel without the calibration
results from one channel affecting the other.
4.8.3 Calibration Sequence
1. The CS5460A must be operating in its active
state, and ready to accept valid commands via the
SPI interface, before a calibration sequence can be
executed. The user will probably also want to clear
the ‘DRDY’ bit in the Status Register.
2. The user should then apply appropriate calibration signal(s) to the “+” and “-” signals of the voltage/current channel input pairs. (The appropriate
calibration signals for each type of calibration sequence are discussed next, in Sections 4.8.4 and
4.8.5.)
3. Next the user should send the 8-bit calibration
command to the CS5460A serial interface.The
DS487PP437
CS5460A
calibration command is an 8-bit command. Various bits within this command specify the exact type
of calibration that is to be performed (e.g., AC gain
cal for voltage channel, DC offset cal for current
channel, etc.)The user must set or clear these bits
in the calibration command to correctly specify exactly which calibration sequence is to be executed.
4. After the CS5460A has finished running the desired internal calibration sequence and has stored
the updated calibration results in the appropriate
calibration registers, the DRDY bit is set (assuming
that it had previously been cleared) in the Status
Register to indicate that the calibration sequence
has been completed. If desired, the results of the
calibration can now be read from the appropriate
gain/offset registers, via the serial port.
Note that when the calibration command is sent to
the CS5460A by the user, the device must not be
performing A/D conversions (in either of the two
acquisitions modes). If the CS5460A is running
A/D conversions/computations in the ‘continuous
computation cycles’ acquisition mode (C=1), the
user must first issue the Power-Up/Halt Command
to terminate A/D conversions/computations. If the
CS5460A is running A/D conversions/computations in the ‘single computation cycle’ data acquisition mode (C=0), then the user must either issue
the Power-Up/Halt Command, or else wait until the
computation cycle has completed, before executing
any calibration sequence. The calibration sequences will not run if the CS5460A is running in either
of the two available acquisition modes.
4.8.4 Calibration Signal Input Level
For both the voltage and current channels, the differential voltage levels of the user-provided calibration signals must be within the specified voltage
input limits (refer to “Differential Input Voltage
Range” in Section 1., Characteristics and Specifi-cations). For the voltage channel the peak differential voltage level can never be more than
The same is true for the current channel if the cur-
±250 mV.
rent channel input PGA is set for 10x gain. If the
user sets the current channel’s PGA gain to 50x,
then the current channel’s input limits are
Note that for the AC/DC gain calibrations, there is
an absolute limit on the RMS/DC voltage levels
(respectively) that are selected for the voltage/current channel gain calibration input signals.The
maximum value that the gain register can attain is
4. Therefore, for either channel, if the voltage level
of a gain calibration input signal is low enough that
it causes the CS5460A to attempt to set either gain
register higher than 4, the gain calibration result
will be invalid, and after this occurs, all CS5460A
results obtained when the part is running A/D conversions will be invalid.
±50 mV.
4.8.5 Calibration Signal Frequency
The frequency of the calibration signals must be
less than 1 kHz (assume MCLK/K = 4.096 MHz
and K = 1). Optimally, the frequency of the calibration signal will be at the same frequency as the
fundamental power line frequency of the power
system that is to be metered.
4.8.6 Input Configurations for Calibrations
Figure 18 shows the basic setup for gain calibration. If a DC gain calibration is desired, the user
must apply a positive DC voltage level. The user
should set the value of this voltage such that it truly
represents the absolute maximum peak instantaneous voltage level that needs to be measured
acrosstheinputs(includingthemaximum
over-range level that must be accurately measured). In other words, the input signal must be a
positive DC voltage level that represents the desired absolute peak full-scale value. However, in
many practical power metering situations, an AC
signal is preferred over a DC signal to calibrate the
gain. If the user decides to perform AC gain calibration instead of DC, the user should apply an AC
reference signal that is set to the desired maximum
RMS level.Because the voltage/current wave-
38DS487PP4
forms that must be measured in most power systems are approximately sinusoidal in nature, the
designer/user will most likely need to set the RMS
levels of the AC gain calibration input signals such
that they will be significantly lower than the voltage/current channel’s maximum DC voltage input
level. This must be done in order to avoid the possibility that the peak values of the AC waveforms
that are to be measured will not register a value that
would be outside the available output code range of
the voltage/current A/D converters. For example,
on the voltage channel, if the Voltage Channel
Gain Register is set to it’s default power-on value
of 1.000... before calibration, then the largest pure
sinusoidal waveform that can be used in AC calibration is one whose RMS-value is ~0.7071 of the
value of the voltage channel’s peak DC input voltage value of
±250 mV. Thus the maximum value
of the input sinusoid would be ~176.78mV (rms).
But in many practical power metering situations,
the user will probably want to reduce the RMS
voltage input level of the AC gain calibration signal
even further, to allow for some over-ranging capability. A typical sinusoidal calibration value which
allows for reasonable over-range margin would be
0.6 of the voltage/current channel’s maximum input voltage level. For the voltage channel, such a
sine-wave would have a value of 0.6 x 250mV =
150mV (rms).
For the offset calibrations, there is no difference
between the AC and DC calibration signals that
must be supplied by the user: The user should simply connect the “+” and “-’ pins of the voltage/current channels to their ground reference level. (See
Figure 19.)
The user should not try to run both an offset and
gain calibration at the same time. This will cause
undesirable calibration results.
4.8.7 Description of Calibration Algorithms
The computational flow of the CS5460A’s AC and
DC gain/offset calibration sequences are illustrated
CS5460A
External
Connections
+
XGAIN
-
+
XGA IN
-
Full Scale
(DC or AC)
CM
AIN+
+
-
AIN-
+
-
Figure 18. System Calibration of Gain.
External
Connecti ons
AIN+
+
0V
-
AIN-
+
CM
-
Figure 19. System Calibration of Offset.
in Figure 20. This figure applies to both the voltage channel and the current channel. The following
descriptions of calibration sequences will focus on
the voltage channel, but apply equally to the current channel.
Note:For proper calibration, it is assumed that the
value of the Voltage-/Current-Channel Gain
Registers are set to default (1.0) before running
the gain calibration(s), and the value in the
Voltage-/Current Channel AC and DC Offset
Registers is set to default (0) before running
calibrations. This can be accomplished by a
software or hardware reset of the device. The
values in the voltage/current calibration
registers do affect the results of the calibration
sequences.
4.8.7.1 AC Offset Calibration Sequence
The idea of the AC offset calibration is to obtain an
offset value that reflects the square of the RMS output level when the inputs are grounded.During
normal operation, when the CS5460A is calculating the latest result for the RMS Voltage Register,
this AC offset register value will be subtracted
from the square of each successive voltage sample
in order to nullify the AC offset that may be inherent in the voltage-channel signal path. Note that
+
-
+
-
DS487PP439
InM odulator
Filter
DC Offset*
CS5460A
to V *, I* , P * , E * Reg iste rs
++
Σ
2
X
+
-+
N
AC O ffse t*
+
x
Gain*
SINC
2
N
2
X
X
N
÷
V
RMS
*
1
x
-X
* Denotes readable/writable register
Figure 20. Calibration Data Flow
÷
the value in the AC offset register is proportional to
the square of the AC offset. First, the inputs should
be grounded by the user, and then the AC offset calibration command should be sent to the CS5460A.
When the AC offset calibration sequence is initiated by the user, a valid RMS Voltage Register value
is acquired and squared. This value is then subtracted from the square of each voltage sample that
comes through the RMS data path. See Figure 20.
4.8.7.2 DC Offset Calibration Sequence
The Voltage Channel DC Offset Register holds the
negative of the simple average of N samples taken
while the DC voltage offset calibration was executed. The inputs should be grounded during DC offset calibration. The DC offset value is added to the
signal path to nullify the DC offset in the system.
4.8.7.3 AC Gain Calibration Sequence
The AC voltage gain calibration algorithm attempts
to adjust the Voltage Channel Gain Register value
such that the calibration reference signal level presented at the voltage inputs will result in a value of
0.6 in the RMS Voltage Register. The user must apply the ac calibration signal to the “+” and “-” input
pins of the channel under calibration, and the user
must select an appropriate rms level for this calibration signal. During AC voltage gain calibration,
the value in the RMS Voltage Register is divided
N
0.6
x
into 0.6. This result is the AC gain calibration result stored in the Voltage Channel Gain Register.
Two examples of AC calibration and the resulting
shift in the digital output codes of the channel’s instantaneous data registers are shown in Figures 21
and 22. Note Figure 22 shows that a positive (or
negative) DC level signal can be used even though
an AC gain calibration is being executed. However, an AC signal cannot be used if the DC gain calibration sequence is going to be executed.
4.8.7.4 DC Gain Calibration Sequence
Based on the level of the positive DC user-provided
calibration voltage that should be applied across
the “+’ and “-” inputs, the CS5460A determines the
Voltage Channel Gain Register value by averaging
the Instantaneous Voltage Register’s output signal
values over one computation cycle (N samples) and
then dividing this average into 1. Therefore, after
the DC voltage gain calibration has been executed,
the Instantaneous Voltage Register will read at
full-scale whenever the DC level of the input signal
is equal to the level of the DC calibration signal that
was applied to the voltage channel inputs during
the DC gain calibration.For example, if a
+230 mV DC signal is applied to the voltage channel inputs during the DC gain calibration for the
current channel, then the Instantaneous Voltage
Register will measure at unity whenever a 230 mV
40DS487PP4
Sinewave
INPUT
SIGNAL
Before AC Gain Calibration (Vgain Register = 1)
250 mV
230 mV
0V
-230 mV
-250 mV
V
RMS
Register =
230
/
x1/
≈
0.65054
250
√
2
0.9999...
0.92
Instantaneous Voltage
Register Values
-0.92
-1.0000...
Before AC Gain Calibration (Vgain Register = 1)
250 mV
230 mV
DC Si gnal
INPUT
0V
SIGNAL
-250 mV
V
RMS
Register =
230
/
250
CS5460A
0.9999...
0.92
Instantaneous Voltage
Register Values
-1.0000...
=
0.92
After A C Gain C alib ration (Vgain Register chan ged to ~0.9223)
Sinewave
INPUT
SIGNAL
250 mV
230 mV
-230 mV
-250 mV
0V
V
Register = 0.6000...
RMS
0.92231
0.84853
Instantaneous Voltage
Register Values
-0.84853
-0.92231
Figure 21. Example of AC Gain Calibration
DC level is applied to the voltage channel inputs.
See Figure 23. The reader should compare Figure
22 to Figure 23 to see the difference between the
AC and DC calibration gain calibration sequences.
4.8.8 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines the number of conversions that will be performed by the CS5460A during a given calibration
sequence. For DC offset/gain calibrations, the calibration sequence always takes at least N + 30 conversion cycles to complete.For AC offset/gain
calibrations, the calibration sequence takes at least
6N + 30 A/D conversion cycles to complete, (about
6 computation cycles). If N is increased by the user, the accuracy of calibration results will increase.
4.8.9Is Calibration Required?
The CS5460A does not have to be calibrated. After
CS5460A is powered on and then reset, the device
is functional. This is called the active state. Upon
receivinga‘StartConversions’command,
CS5460A can perform measurements without being calibrated. But the CS5460A’s output is always
After AC Gain Calibration (Vgain Regi ster changed to ~0. 65217)
DC Si gnal
INPUT
SIGNAL
250 mV
230 mV
-250 mV
0V
V
Register = 0.6000...
RMS
0.65217
0.6000
Instantaneous Voltage
Register Values
-0.65217
Figure 22. Another Example of AC Gain Calibration
affected by the values inside the various calibration
registers. If no calibrations are executed by the user, then these registers will contain the default values (Gains = 1.0, DC Offsets = 0.0, AC Offsets =
0). Although the CS5460A can be used without
performing an offset or gain calibration, the guar-
Before DC Gain Calibration (Vgain Register = 1)
250 mV
230 mV
DC Si gnal
INPUT
0V
SIGNAL
-250 mV
V
Register =
RMS
After DC Gain Calibration (Vgain Register changed to 1.0870)
230 mV
DC Si gnal
INPUT
0V
SIGNAL
V
RMS
230
/
=
250
Register = 0.9999...
0.92
Figure 23. Example of DC Gain Calibration
0.9999...
0.92
Instantaneous Voltage
Register Values
-1.0000...
0.9999...
Instantaneous Voltage
Register Values
DS487PP441
CS5460A
anteed ranges for accuracy of ±0.1% of reading
(with respect to a known voltage and current level)
will not be valid until a gain/offset calibration is
performed. Although the CS5460A will always exhibit the linearity + variation tolerances that are
specified in Table 2, the exact reference voltage
and current levels to which this linearity is referenced will vary from sample to sample. If no calibrationisperformed,thesevoltage/current
reference levels exist based on the full-scale DC input voltage limits for each channel, which are approximately equal to the voltages specified in the
“Max Input” row of Table 2. But these voltages
will have a variation from part to part. Any given
CS5460A sample must be calibrated to insure the
guaranteed accuracy = (linearity+variation) abilities of the sample, with respect to a specific input
voltage signal levels at the voltage/current channel
inputs. The exact calibration signals must be supplied by the user during calibration., and therefore
the user determines the levels of these reference
signals are determined by the user.
tively decrease the guaranteed “±0.1% of reading”
linearity + variation range (and therefore the accuracy range) of the RMS calculation results and the
overall energy results. [Refer to Table 2.] This will
occur whenever a DC gain calibration is performed
(on either channel) of a CS5460A sample while applying a DC signal whose value is less than the individual sample’s inherent maximum differential
DC input voltage level. This will also occur whenever an AC gain calibration is performed (on either
channel) using an AC signal whose RMS value is
less then 60% of the sample’s inherent maximum
AC input voltage levels.
Finally, remember that the ±0.1% (of reading) accuracy guarantee is made with the assumption that
the device has been calibrated with MCLK =
4.096 MHz, K = 1, and N = 4000. If MCLK/K becomes too small, or if N is set too low (or a combination of both), then the CS5460A may not exhibit
±0.1% linearity + variation.
4.8.10 Order of Calibration Sequences
As an example, suppose the user runs the DC gain
calibration sequence on the current channel (assume PGA gain set for “10x”) using a calibration
signal level across the IIN+/IIN- pins of 187.5 mV
(DC).After this calibration is performed, the
full-scale digital output code (0x7FFFFF in the Instantaneous Current Register) will be obtained
whenever the input voltage across the IIN+ and
IIN- pins is 187.5 mV (DC). Note that this level is
~75% of the (typical) maximum available input
voltage range [i.e, ~±250 mV DC.] In this situation, the current channel input ranges for which
±0.1% linearity + variation are guaranteed will be
reduced to between 0.5mV (DC) and 187.5mV
(DC), as opposed to what is specified in Table 2
[which would translate into a voltage range between 0.5mV (DC) and 250 mV (DC)].
Also note that using gain calibration signal levels
which cause the CS5460A to set the internal gain
registers to a value that is less than unity will effec-
Should offset calibrations be performed before gain
calibrations? Or vice-versa? This section summarizes the recommended order of calibration.
1. If the user intends to measure any DC content
that may be present in the voltage/current and power/energy signals, then the DC offset calibration sequences should be run (for both channels) before
any other calibration sequences. However if the
user intends to remove the DC content present in
either the voltage or current signals (by turning on
the voltage channel HPF option and/or the current
channel HPF option--in the Status Register) then
DC offset calibration does not need to be executed
for that channel. Note that if either the voltage HPF
or current HPF options are turned on, then any DC
component that may be present in the power/energy signals will be removed from the CS5460A’s
power/energy results.
2. If the user intends to set the energy registration
accuracy to within ±0.1% (with respect to reference
42DS487PP4
CS5460A
calibration levels on the voltage/current inputs)
then the user should next execute the gain calibrations for the voltage/current channels. The user can
execute either the AC or DC gain calibration sequences (for each channel).
3. Finally, the user should (if desired) run the AC
offset calibration sequences for the voltage and
current channels. Simply ground the “+” and “-”
inputs of both channels and execute the AC offset
cal sequence.
Note that technically, by following the order of calibrations as suggested above, if DC offset calibration is performed for a given channel, and
afterwards a gain calibration is performed on the
channel, then the DC offset register value for the
channel should be scaled by a factor equal to the respective channel’s new gain register value. For example, suppose that execution of DC offset
calibration for the voltage channel results in a value
of 0x0001AC = 0.0000510(d) in the Voltage Channel DC Offset Register (and we assume that the
value in the Voltage Channel Gain Register was at
its default value of 1.000... during execution of this
DC offset calibration). Then if AC or DC gain calibration is executed for the voltage channel such
that the Voltage Channel Gain Register is changed
to 0x4020A3 = 1.0019920(d), then the user may
want to modify the value in the Voltage Channel
DC Offset Register to 0x0001AD = 0.0000511(d),
whichis(approximately)equalto
1.0019920*0.0000510.
4.8.11 Calibration Tips
To minimize digital noise, the user should wait for
each calibration step to be completed before reading or writing to the serial port.
After a calibration is performed, the offset and gain
register contents can be read and stored externally
by the system microcontroller and recorded in
memory. The same calibration words can be uploaded into the offset and gain registers of the con-
verters when power is first applied to the system, or
when the gain range on the current channel is
changed.
4.9 Phase Compensation
The values of bits 23 to 17 in the Configuration
Register can be altered by the user to adjust the
amount of time delay that is imposed on the digitally sampled voltage channel signal. This time delay
is applied to the voltage channel signal in order to
compensate for the relative phase delay (with respect to the fundamental frequency) between the
sensed line-voltage/line-current signals that may be
introduced by the user-supplied voltage and current
sensor circuitry, external to the CS5460A. Voltage
and current transformers, as well as other sensor/filter/protectiondevicesdeployedatthe
front-end of the voltage/current sensor networks
can often introduce an ‘artificial’ phase-delay in
the system that distorts/corrupts the phase relationship between the line-voltage and line-current signals that are to be measured. The user can set the
phase compensation bits PC[6:0] in the Configuration Register to nullify undesirable phase distortion
between the digitally sampled signals in the two
channels. The value in the 7-bit phase compensation word indicates the amount of time delay that is
imposed on the voltage channel’s analog input signal with respect to the current channel’s analog input signal.
The default setting of the PC[6:0] bits at power-on/reset is “0000000”. Note that this setting represents the smallest time-delay (and therefore the
smallest phase delay) between the voltage- and current-channel signal paths. That is, the phase delay
between the voltage/current channels is smallest
with the “0000000” setting. But phase shifts introduced by the designer’s external voltage/current
sensor components may persuade the designer to
intentionally impose a non-zero time-shift correction value on the voltage channel signal. With the
default setting, the phase delay on the voltage chan-
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CS5460A
nel signal is ~0.995 µs (~0.0215 degrees assuming
a 60 Hz power signal). Note that the 7-bit phase
compensation word is a 2’s complement binary
number. With MCLK = 4.096 MHz and K=1, the
range of the internal phase compensation ranges
from -2.8 degrees to +2.8 degrees when the input
voltage/current signals are at 60 Hz. In this condition, each step of the phase compensation register
(value of one LSB) is ~0.04 degrees. For values of
MCLK other than 4.096 MHz, these values for the
span (-2.8 to +2.8 degrees) and for the step size
(0.04 degrees) should be scaled by 4.096 MHz /
(MCLK / K). For power line frequencies other than
60Hz (e.g., 50 Hz), the user can predict the values
of the range and step size of the PC[6:0] bits by
converting the above values to time-domain (seconds), and then computing the new range and step
size (in degrees) with respect to the new line frequency.
Unlike offset/gain calibration, the CS5460A does
not provide an automated on-chip phase calibration
sequence. If the user is concerned about nullifying
artificial phase shift between the voltage-sense and
current-sense signals, the user must determine the
optimal phase compensation setting experimentally. To calibrate the phase delay, the user may try
adjusting the phase compensation bits while the
CS5460A is running in ‘continuous computation
cycles’ data acquisition mode. While the CS5460A
is performing continuous computations, the user
should provide a purely resistive load (no inductance or capacitance) to the power line, such that
nominal-level voltage and current signals from the
power line are sensed into the voltage and current
channels of the CS5460A. In this condition, any
phase delay between the measured voltage and current signals is due only to phase delay introduced
by the user’s external voltage/current sensor circuitry. The user should then adjust the PC[6:0] bits
until the Energy Register value is maximized.
4.10 Time-Base Calibration Register
The Time-Base Calibration Register (notated as
“TBC” in Figure 3) is used to compensate for slight
errors in the XIN input frequency. External oscillators and crystals have certain tolerances. If the
user is concerned about improving the accuracy of
the clock for energy measurements, the Time-Base
Calibration Register value can be manipulated to
compensate for the frequency error.Note from
Figure 3 that the TBC Register only affects the value in the Energy Register.
As an example, if the desired XIN frequency is
4.096 MHz, but during production-level testing,
suppose that the average frequency of the crystal on
a particular board is measured to actually be
4.091 MHz. The ratio of the desired frequency to
the actual frequency is 4.096 MHz/4.091 MHz =
~1.00122219506. The TBC Register can be set to
1.00122213364 = 0x80280C(h), which is very
close to the desired ratio.
4.11 Power Offset Register
Referring to Figure 3, note the “Poff” Register that
appears just after the power computation. This register can be used to offset system power sources
that may be resident in the system, but do not originate from the power line signal. These sources of
extra energy in the system contribute undesirable
and false offsets to the power/energy measurement
results. For example, even after DC offset and AC
offset calibrations have been run on each channel,
when a voltage signal is applied to the voltage
channel inputs and the current channel is grounded
(i.e., there is zero input on the current channel), the
current channel may still register a very small
amount of RMS current caused by leakage of the
voltage channel input signal into the current channel input signal path. Although the CS5460A has
high channel-to-channel crosstalk rejection, such
crosstalk may not totally be eliminated.) The user
can experimentally determine the amount of ‘artificial’ power that might be induced into the volt-
44DS487PP4
CS5460A
age/currentchannelsignalsduetosuch
crosstalk/system noise/etc., and then program the
Power Offset Register to nullify the effects of this
unwanted energy.
4.12 Input Protection - Current Limit
In Figures 6, 7, 8, and 9, note the series resistor RI+
which is connected to the IIN+ input pin. This resistor serves two purposes. First, this resistor functions in coordination with C
a low-pass filter.The filter will a) remove any
broadband noise that is far outside of the frequency
range of interest, and also b) this filter serves as the
anti-aliasing filter, which is necessary to prevent
the A/D converter from receiving input signals
whose frequency is higher than one-half of the
sampling frequency (the Nyquist frequency). The
second purpose of this resistor is to provide current-limit protection for the Iin+ input pin, in the
event of a power surge or lightening surge. The
role that R
I+ contributes to input filtering will be
discussed in the Section 4.13. But first the current-limit protection requirements for the Iin+/Iinand Vin+/Vin- pins are discussed.
The voltage/current-channel inputs have surge-current limits of 100 mA. This applies to brief voltage/current spikes (<250 ms). The limit is 10 mA
for DC input overload situations. To prevent permanent damage to the CS5460A, the designer must
include adequate protection circuitry in the power
meter design, to insure that these pin current limits
are never exceeded, when CS5460A is operating in
the intended power-line metering environment.
Focussing specifically on Figure 7, which shows
how voltage/current transformers can be used to
sense the line-voltage/line-current, suppose for example that the requirements for a certain 120 VAC
power system require that the power meter must be
able to withstand up to a 8kV voltage spike on the
power line during normal operating conditions. To
provide a suitable sensor voltage input level to the
voltage channel input pins of the CS5460A, the
Idiff and/or CIdiff to form
turns ratio of the voltage-sense transformer should
be chosen such that the ratio is, for example, on the
order of 1000:1. A voltage-sense transformer with
a 1000:1 turns ratio will provide a 120 mV (rms)
signal to the CS5460A’s differential voltage channel inputs, when the power line voltage is at the
nominal level of 120 VAC. Therefore, a brief 8kV
surge would be reduced to a 8V surge across R
V+.
What happens when 8 volts (common-mode) is
present across one of the analog input pins of the
CS5460A? The Vin+/Vin- and Iin+/Iin- pins of the
CS5460A are equipped with internal protection diodes. If a voltage is presented to any of these pins
that is larger than approximately ±7V (with respect
to VA- pin) these protection diodes will turn on inside the CS5460A. But in order to prevent excessive current levels from flowing through the
device, the value of R
V+ must be large enough that
when a 8V surge is present across the secondaries
of the voltage-sense transformer, the brief surge
current through R
100mA.Therefore, a minimum value for R
V+ should not be any greater than
V+
would be (8V - 7V) / 100mA = 10 Ω. This value
may be increased as needed, to easily obtain the desired cutoff frequency of the anti-aliasing filter on
the voltage channel (described later), and also to
provide some margin. But the designer should try
to avoid using values for the protection resistors
that are excessively high. A typical value for R
V+
would be 470 Ω.
The VIN- pin should also have a protection resistor
(called R
the value of R
V- in Figure 7). To maintain symmetry,
V- should be made equal to RV+.
For the current channel inputs (Iin+ and Iin-), if we
assume that the maximum current rating (I
max)for
this power line is 30A (RMS), then a suitable turns
ratio for the current-sense transformer might be
200:1. Since the maximum load for a 120 VAC
line rated at 30A would be 4 Ω (for unity power
factor), a brief 8kV surge across “L” and “N” could
generate as much as 2000A (RMS) of current
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CS5460A
through the primaries of the current-sense transformer. This can in turn generate as much as 10V
across the secondaries of the current-sense transformer. This voltage is high enough to turn on one
or more of the internal protection diodes located off
of the Iin+/Iin- pins. Therefore, the value of the
protection resistor that will limit the current flow to
less than 100 mA would be (10V - 7V) / 100 mA =
30 Ω. In order to provide some margin and to use
the same resistor values that are used on the
Vin+/Vin- pins, we could use 470 Ω as a lower limit for the R
I+ and RI- resistors shown in Figure 7.
Referring to the circuit implementations shown in
Figures 6, 8, and 9, note that when resistor-divider
configurations are used to provide the voltage
channel sense voltage, the VIN+ pin does not need
an additional, separate, dedicated protection resistor. This is because the resistive voltage-divider
already provides the series resistance that is needed
for this protection resistance (from R1 and R2).
(And note in Figure 8 that this is true for both the
VIN+ pin and the VIN- pin.) In Figure 7, a voltage
transformer is used as the voltage sensor. When
any type of transformer is used as the sensor device
for voltage (or current) channel, a dedicated protection resistor R
the VIN+ pin, and similarly, a resistor (R
V+ should be installed in series with
V-) should
be installed in series to the VIN- input pin.
Additional considerations/techniques regarding the
protection of the analog input pins against sudden
high-frequency, high-level voltage/current surges
are discussed in Section 4.14.
4.13 Input Filtering
Figure 6 shows how the analog inputs can be connected for a single-ended input configuration. Note
here that the Vin- and Iin- input pins are held at a
constant dc common-mode level, and the variation
of the differential input signal occurs only on the
Vin+ and Vin- pins. The common-mode level on
the Vin-/Iin- pins is often set at (or very near) the
CS5460A’s common-mode ground reference po-
tential. (The common-mode ground reference potential is defined by the voltage at the VA- pin.)
But this is not required--the dc reference level of
the Vin-/Iin- pins can be set to any potential between [VA-] and [(VA+) - 250mV]. In Figure 6,
observe the circuitry which has been placed in front
of the current channel input pins, as one example.
The anti-aliasing filter can be constructed by calculating appropriate values for R
CI-. The sensor voltage that is created by the volt-
=
age drop across R
SHUNT is fed into the Iin+ pin,
I+ =RI-,CIdiff, and CI+
while the voltage at the Iin- pin is held constant.
Figure 7 shows a differential bipolar input configuration. Note in Figure 7 that the “+” and “-” input
pins for the voltage/current channels are equally
referenced above and below the CS5460A’s
ground reference voltage. Such a differential bipolar input configuration can be used because the
CS5460A voltage/current channel inputs are able
to accept input voltage levels as low as -250 mV
(common-mode) below the VA- pin ground reference, which is defined by the voltage at the VApin. (In fact, if desired, the center-tapped reference
of these differential input pairs could be connected
to a DC voltage of, for example, +2V, because +2V
is within the available common-mode range of
[VA-] and [VA+ - 250mV]. But this configuration
may not be so practical for most metering applications.) In the differential bipolar input configuration, the voltage signals at the Vin- and Iin- pins
will fluctuate in similar fashion to the Vin+/Iin+
pins, except the voltages at the “-” pins will be 180
degrees out of phase with respect to the voltage signals at the “+” pins. Therefore the signal paths to
the “+” and “-” pins play an equal role in defining
the differential voltage input signal.Because of
this, the protection resistors placed on Vin-/Iinpins will play an equally important role as the resistors on the Vin+/Iin+ pins, in defining the differential responses of the voltage/current channel input
anti-aliasing filters. These resistors also serve as
46DS487PP4
CS5460A
the current-limit protection resistors (mentioned
earlier).
Before determining a typical set of values for R
V-,CV+,CV-,CVdiff,RI+,RI-,CI+,CI-, and CIdiff in
R
V+,
Figure 7, several other factors should be considered:
1. Values for the above resistors/capacitors should
be chosen with the desired differential-mode (and
common-mode) lowpass cutoff frequencies in
mind. In general, the differential cutoff frequencies should not be less than 10 times the cut-off frequencies of the internal voltage/current channel
filters, which can be estimated by studying
Figure 4 and Figure 5. From these figures, we see
that the internal voltage channel cutoff frequency is
at ~1400 Hz while the current channel cutoff frequency is at ~1600 Hz. If the cutoff frequency of
the external anti-aliasing filter is much less than
10x these values (14000 Hz and 16000 Hz), then
some of the harmonic content that may be present
in the voltage/current signals will be attenuated by
the voltage/current channel input anti-aliasing filters, because such R-C filters will begin to roll off
at a frequency of 1/10th of the filter’s -3dB cutoff
frequency. If the designer is not interested in metering energy that may be present in the higher harmonics (with respect to the fundamental power line
frequency) then the differential-mode cutoff frequencies on the voltage/current input networks can
be reduced. However, relaxing the metering bandwidth is usually unacceptable, as most modern
power meters are required to register energy out to
the 11th harmonic (at a minimum).
2.The first-order time-constants of the overall
voltage and current channel sensor networks
should be set such that they are equal (within reason), or at least close in magnitude.If the
time-constants of the voltage/current sensor networks are not well-matched, then the phase relationshipbetweenthevoltage-senseand
current-sense signals will suffer an undesirable
shift. In this situation, the real (true) power/energy
measurements reported by the CS5460A can contain significant error, because the power factor of
the sensed voltage and current signals will be significantly different than the actual power factor of
the power line voltage/current waveforms.
Note also that in addition to the time-constants of
the input R-C filters, the phase-shifting properties
of the voltage/current sensors devices may also
contribute to the overall time-constants of the voltage/current input sensor networks. For example,
current-sense transformers and potential transformers can impose phase-shifts on the sensed current/voltage waveforms. Therefore, this possible
source of additional phase-shift caused by sensor
devices may also need to be considered as the designer selects the final R and C values for the voltage/current anti-aliasing filters.The designer
should also note that as an alternative to, or in addition to the fine adjustment of the R and C values
of the two anti-alias filters, the designer may also
be able to adjust the CS5460A’s phase compensation bits (see Phase Compensation), in order to
more closely match the overall time-constants of
the voltage/current input networks. But regardless
of whether the phase compensation bits are or are
not used to help more closely match the time-constants, this requirement of equal time-constants
must ultimately be considered when the designer
selects the final R and C values that will be used for
the input filters. (Of course, this factor may not
turn out to be so important if the designer is confident that the mis-match between the voltage/current channel time-constants will not cause enough
error to violate the accuracy requirements for the
given power/energy metering application.)
3. Referring to the specs in Section 1, note that the
differential input impedance across the current
channel input pins is only 30 kΩ, which is signifi-
cantly less than the corresponding impedance
across the voltage channel input pins (which is 1
MΩ).While the impedance across the voltage
DS487PP447
CS5460A
channel is usually high enough to be ignored, the
impedance across the current channel inputs may
need to be taken into account by the designer when
the desired cutoff frequencies of the filters (and the
time-constants of the overall input networks) are
computed. Also, because of this rather low input
impedance across the current channel inputs, the
designer should note that the as the values for R
and/or RI- are increased, the interaction of the current channel’s input impedance can begin to cause
a significant voltage drop situation within the current channel input network. If this is not taken into
account, values may be chosen for R
I+ =RI- that are
large enough to cause a discrepancy between the
expected (theoretical) sensor gain and the actual
sensor gain of the current sensor network, which
may not be anticipated by the designer. Also, if this
voltage drop effect is not considered, the designer
may select values for R
I+ and RI that are slightly
larger than they should be, in terms of maximizing
the available dynamic range of the current channel
input. And for the very same reason, the line-current-to-sensor-output-voltage conversion factor of
the current sensor may not be optimized if this voltage division is not considered by the designer,
when (for example) the designer is selecting a value for the burden resistor for a given current transformer. This issue should be considered, although
the user should note that a slight voltage drop only
causes a slight loss in available dynamic range, and
the effects of this voltage drop on the actual current
channel sensor gain can be removed during gain
calibration of the current channel.
4. Referring to Figures 6 - 9, the designer may decide to use only some of the capacitors/resistors
shown in these example circuit diagrams. However, note that the all of the filter capacitors C
C
I+,CI-,CVdiff, and CIdiff can, in some situations,
V+,CV-,
help to improve the ability of both input networks
to attenuate very high-frequency RFI that can enter
into the CS5460A’s analog input pins. Therefore,
during layout of the PCB, these capacitors should
be placed in close proximity to their respective input pins.
If any/all of the common-mode connected capacitors (C
V+,CV-,CI+,CI-) are included in the input
networks, their values should be selected such that
they are at least one order of magnitude smaller
than the value of the differential capacitors (C
I+
Idiff). This is done for at least two reasons:
and C
a) The value tolerance for most types of commercially available surface-mount capacitors is not
small enough to insure appreciable value matching,
between the value of C
tween the value of C
V+ vs. CV-,aswellasbe-
V+ vs. CV-. Such value mis-
matchcanadverselyaffectthedesired
differential-mode response of the voltage/current
input networks.By keeping the values of these
common-mode capacitors small, and allowing the
value of the C
Vdiff, and CIdiff to dominate the differ-
ential 1st-order time-constant of the input filter networks, this undesirable possibility of frequency
response variation can be minimized.
b) The common-mode rejection performance of the
CS5460A is very good within the frequency range
over which the CS5460A performs A/D conversions. Addition of such common-mode caps can
actually often degrade the common-mode rejection
performance of the entire voltage/current input networks. Therefore, choosing relatively small values
for (CV+,CV-,CI+,CI-) will provide necessary com-
mon-mode rejection at the much higher frequencies, and this will also allow the CS5460A to
realize its relatively good CMRR performance in
the frequency-range of interest.
We start with the current channel. [Note that for
the purposes of this discussion, we assume that the
phase-shifts caused by the voltage-sense transformer and current-sense transformer in Figure 7
are negligible (or even equal), although such an assumption should definitely not be made in a real-life practical meter design situation.]Using
commonly available values for our components, if
Vdiff,
48DS487PP4
CS5460A
we set RI+ =RI- = 470 Ω, then a value of CIdiff =18
nF and a value of 0.22 nF for C
I- and CI- will yield
a -3dB cutoff frequency of 15341 Hz for the current
channel. Then, for the voltage channel, if we also
set R
V+ =RV- = 470 Ω,CVdiff =18nF,andCV- =CV-
= 0.22 nF (same as current channel), the -3dB cutoff frequency of the voltage channel’s input filter
will be 14870 Hz. The difference in the two cutoff
frequencies is due to the difference in the input impedance between the voltage/current channels.
If we were concerned about the effect that the difference in these two cutoff frequencies (and therefore the mis-match between the time-constants of
the overall voltage/current input networks) would
have on the accuracy of the power/energy registration, the designer might take the trouble to use a
non-standard resistor value for R
V+ =RV- of (for ex-
ample) 455 Ω. This would shift the (differential)
-3dB cutoff frequency of the voltage channel’s input filter (at the voltage channel inputs) to ~15370
Hz, which would cause the first-order time-constant values of the voltage/current channel input filters to be more equal.
As was mentioned earlier, in addition to or as an alternative to slightly modifying the value of RI+ =
I- or RV+ =RV-, the designer can often obtain clos-
R
er agreement between the voltage/current channel
time-constants by adjusting the phase compensation bits, which can often allow the designer to
avoid the requirement to use less commonly-available resistor/capacitor values (such as R
I+ =RI- =
455 Ω). Suppose that we do not slightly alter the
values of R
V+ =RV-, so that the values of the R’s
and C’s of both channels is again the same (470 Ω).
In this case, we can estimate the first-order
time-constants of the two R-C filters by taking the
reciprocal of the -3dB cutoff frequencies (when expressed in rads/s).If we subtract these two
time-constants, we can conclude that after the voltage/current signals pass through their respective
anti-aliasing filters, the sensed voltage signal will
be delayed ~0.329 µs more than the current signal.
If we assume that we are metering a 60 Hz power
system, this implies that the input voltage-sense
signal will be delayed ~0.007 degrees more than
the delay imposed on the input current-sense signal. Also, we note that when the PC[6:0] bits are
set to their default setting of “0000000”, the internal filtering stages of the CS5460A will impose an
additional delay on the (fundamental frequency
component of the) voltage signal of 0.0215 degrees, with respect to the current signal. (Again,
note that we are assuming a 60 Hz power system).
The total difference between the delay on the voltage-sense fundamental and the current-sense fundamental will therefore be ~0.286 degrees. But if
we were to set the phase compensation bits to
1111111, the CS5460A will delay the voltage
channel signal by an additional -0.04 degrees,
which is equivalent to shifting the voltage signal
forward by 0.04 degrees. The total phase shift on
the voltage-sense signal (with respect to the fundamental frequency) would then be ~0.011 degrees
ahead of the current-sense signal, which would
therefore provide more closely-matched delay values between the voltage-sense and current-sense
signals. Adjustment of the PC[6:0] bits therefore
can provide an effective way to more closely match
the delays of the voltage/current sensor signals, allowing the designer to use commonly available R
and C component values in both of these filters.
As a final note, the reader should realize that the
above situation is rather hypothetical. For example,
if we assume that the tolerances of the R and C
components that are used to build the two R-C filters is ±0.1%, then either time-constant could vary
by as much as much as ~±2.07 µ s, which means
that the difference between the delays of the voltage-sense and current-sense signals that is caused
by these filters could vary by as much as ~±4.1 µs,
which is equivalent to a phase shift of ~±0.089 degrees (at 60Hz). This in turn implies that our decision to adjust the PC[6:0] bits (to shift the voltage
signal forward by 0.04 degrees) could actually
DS487PP449
CS5460A
cause the voltage signal to be shifted by as much as
~0.100 degrees ahead of the current signal.We
can see that the component value tolerance may
cause even more discrepancy between the two signal delays than if we had decided to leave the
PC[6:0] bits in their “0000000” setting. Thus, adjustment of the PC[6:0] bits to more closely match
the two time-constants/delays may only be useful if
a precise calibration operation can be performed on
each individual power meter, during final calibration/test of the meter. Indeed, such variation in the
R and C component values demonstrates an even
more important reason for the designer to take advantage of the CS5460A’s phase compensation
feature, as can be seen when one compares the effect that component value tolerance has on channel
phase-matching to the relatively slight difference in
phase-match that is calculated if one assumes zero-value tolerance for the R and C values.
4.14 Protection Against High-Voltage
and/or High-Current Surges
In many power distribution systems, it is very likely that the power lines will occasionally carry brief
but large transient spikes of voltage/current. Two
common sources of such high-energy disturbances
are 1) a surge in the line during a lightning storm,
or 2) a surge that is caused when a very inductive
or capacitive load on the power line is suddenly
turned on (“inductive kick”). In these situations,
the input protection resistors and corresponding input filter capacitors (discussed in the previous sections) may not be sufficient to protect the CS5460A
from such high-frequency voltage/current surges.
The surges may still be strong enough to cause permanent damage to the CS5460A. Because of this,
the designer should consider adding certain additional components within the voltage/current channel input circuitry, which can help to protect the
CS5460A from being permanently damaged by the
surges.
Referring to Figure 24, the addition of capacitors
C1 and C2 can help to further attenuate these
high-frequency power surges, which can greatly
decrease the chances that the CS5460A will be
damaged. Typical values for C1 and C2 may be on
the order of 10pF, although the exact value is related to the reactive and resistive properties of the user’s voltage and current sensor devices.In
addition, diodes D1 - D4 can help to quickly clamp
a high voltage surge voltage presented across the
voltage/current inputs, before such a surge can
damage the CS5460A. An example of a suitable
diode part number for this application is BAV199,
which has the ability to turn on very quickly (very
small turn-on time). A fuse could potentially serve
this purpose as well (not shown). R3 and R4 can
provide protection on the “-” sides of the two input
pairs. Set R3 = R1 and R4 = R5. Finally, placing
50-Ω resistors in series with the VA+ and VD+
pins is another technique that has sometimes proven to be effective in protecting the CS5460A from
such high-level, high-frequency voltage/current
surges. However, these 50-Ω resistors may not be
necessary if the protection on the analog input
channels is sufficient, and this is not the most attractive solution, because these resistors will dissipate what can be a significant amount of power,
and they will cause an undesirable voltage drop
which decreases the voltage level presented to the
VA+ and VD+ supply pins.
4.15 Improving RFI Immunity
During EMC acceptance testing of the user’s power metering assembly, the performance of the
CS5460A’s A/D converters can be adversely affected by external radio frequency interference
(RFI). Such external RFI can be coupled into the
copper traces and/or wires on the designer’s PCB.
If RFI is coupled into any of the traces which tie
into the CS5460A’s Vin+/Vin- or Iin+/Iin- input
pins, then errors may be present in the CS5460A’s
power/energy registration results.
50DS487PP4
CS5460A
When such degradation in performance is detected,
the user may improve the CS5460A’s immunity to
RF disturbance by configuring the “+” and “-” inputs of the voltage/current channel inputs such that
they are more symmetrical. This is illustrated in
Figure 24 with the addition of resistors R3 and R4,
as well as capacitors C5 and C6. Note that the input
circuitry placed in front of the voltage/current
channel inputs in Figure 24 represents a single-end-ed input configurations (for both channels). Therefore, these extra resistors and components may not
necessarily be needed to achieve the simple basic
anti-aliasing filtering on the inputs. However, the
addition of these extra components can create more
symmetry across the ‘+’ and ‘-’ inputs of the voltage/current input channels, which can often help to
reduce the CS5460A’s susceptibility to RFI. The
value of C5 should be the same as C3, (and so the
designer may have to re-calculate the desired value
of C3, since the addition of C5 will change the
overall differential-/common-mode frequency responses of the input filter.) A similar argument can
be made for the addition of C6 (to match C8) on the
current channel’s input filter. Finally, addition of
capacitors C4 and C7 can also sometimes help to
improve CS5460A’s performance in the presence
of RFI. All of these input capacitors (C3 - C8)
should be placed in very close proximity to the ‘+’
and ‘-’ pins of the voltage/current input pins in order to maximize their ability to protect the input
pins from high-frequency RFI. In addition to or as
an alternative to these capacitors, addition of inductors L1 - L4 can sometimes help to suppress any incoming RFI. Note that the additional components
just discussed can sometimes actually degrade the
CS5460A’s immunity to RFI. The exact configuration that works best for the designer can vary significantly, according to the user’s exact PCB
layout/orientation.Finally, note that inside the
CS5460A, the Vin+, Vin-, Iin+, and Iin- pins have
all been buffered with ~10pF of internal capacitance (to VA-) in attempt to improve the device’s
immunity to external RFI.
N
120 Vrms
C2
To Service
R
L
Ω
14
10
PFMON
CPUCLK
RESET
10 k
Ω
0.1 µF
5050
3
8
MODENC
17
2
1
XOUT
4.069 MHz
24
XIN
19
INT
7
SDO
23
SCLK
6
CS
5
SDI
20
22
EDIR
21
EOUT
L
Ω
500
470 nF
R1R2
L1
R3
C1
R4
R
SHUNT
R5
D1D2
L2
L3
D3
L4
100 µF
D4
5.1 Volt
C3
C8
0.1 µF
500
C5
Ω
0.1 µF
VA+VD+
CS5460A
9
VIN+
C4
10
VIN-
15
IIN-
C6
C7
16
IIN+
12
VREFIN
11
VREFOUT
VA-DG ND
134
Ω
5k
10 k 10 k47 k 47 k20 k 20 k
To reduce
EMI susc eptibility
1k
1k
+5 V
+5 V
1k
1k
1k
1k
For I nput S urge
Protection
NC
+5 V
Figure 24. Input Protection for Single-Ended Input Configurations, using resistive divider and current
shunt resistor. Note that the digital interface is isolated using opto-isolators.
SCLK
SDO
CS
INT
SDI
RST
GND
DS487PP451
4.16 PCB Layout
For optimal performance, the CS5460A should be
placed entirely over an analog ground plane with
both the VA- and DGND pins of the device connected to the analog plane.
Note:Refer to the CDB5460A Evaluation Board for
suggested layout details, as well as
Applications Note 18 for more detailed layout
guidelines. Before layout, please call for our
Free Schematic Review Service.
CS5460A
52DS487PP4
5. REGISTER DESCRIPTION
CS5460A
Current
Channel
Voltage
Channel
AC Off set Register (1 x 24)
AC Off set Register (1 x 24)
Power Off set Register (1 x 24)
Timebase Cal. Regis ter (1 x 24)
Offset Re gister (1 × 24)DCGain Registe r (1 × 24)AC/DC
Offset Re gister (1 × 24 )DC
Pulse-Rate Register (1 × 24)
Control Register (1 x 24)
Configuration Register (1 × 24)
Gain R egister (1 × 24 )AC/DC
Cycle-Counter Registe
Stat us Registe r (1 × 24)
Mask R egist er (1 × 24)
r(1× 24)
Sign ed Output Regis ters (4 × 24)
(I,V,P,E)
Unsigned Output Registers (2 × 24)
(I, V)
RMS RMS
24-Bit
Serial Interface
Transm it Buffer
Command Word
Stat e Machine
Receive Bu ffer
Figure 25. CS5460A Register Diagram
Note:1.** “default” => bit status after software or hardware reset
2. Note that all registers can be read from, and written to.
5.1 Configuration Register
Address: 0
2322212019181716
PC6PC5PC4PC3PC2PC1PC0Gi
15141312111098
EWAResResSI1SI0EODDL1DL0
76543210
RSVHPFIHPFiCPUK3K2K1K0
SDI
CS
SDO
SCLK
INT
Default** = 0x000001
K[3:0]Clock divider. A 4 bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. Note that a value of “0000” will set K to 16 (not zero).
iCPUInverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = normal operation (default)
1 = minimize noise when CPUCLK is driving rising edge logic
IHPFControl the use of the High Pass Filter on the Current Channel.
0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used.
(default)
1 = High-pass filter is enabled.
VHPFControl the use of the High Pass Filter on the voltage Channel.
0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used.
(default)
1 = High-pass filter enabled
DS487PP453
CS5460A
RSStart a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is
automatically returned to 0 by the reset cycle.
DL0When EOD = 1, EDIR
Default = '0'
DL1When EOD = 1, EOUT
Default = '0'
EODAllows the EOUT
also be accessed using the Status Register.
0 = Normal operation of the EOUT
1 = DL0 and DL1 bits control the EOUT
SI[1:0]Soft interrupt configuration. Select the desired pin behavior for indication of an interrupt.
00 = active low level (default)
01 = active high level
10 = falling edge (INT is normally high)
11 = rising edge (INT is normally low)
ResReserved. These bits must be set to zero.
EWAAllows the output pins of EOUT
ing an external pull-up device.
0 = normal outputs (default)
1 = only the pull-down device of the EOUT
GiSets the gain of the current PGA
0 = gain is 10 (default)
1 = gain is 50
becomes a user defined pin. DL0 sets the value of the EDIR pin.
becomes a user defined pin. DL1 sets the value of the EOUT pin.
and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can
and EDIR pins. (default)
and EDIR pins.
and EDIR ofmultiplechipstobeconnectedinawire-AND,us-
and EDIR pins are active
PC[6:0]Phase compensation. A 2’s complement number used to set the delay in the voltage channel.
When MCLK=4.096 MHz and K=1, the phase adjustment range is about -2.8 to +2.8 degrees
and each step is about 0.04 degrees (this assumes that the power line frequency is 60 Hz). If
(MCLK / K) is not 4.096 MHz, the values for the range and step size should be scaled by the
factor 4.096MHz / (MCLK / K).
Default setting is 0000000 = 0.0215 degrees phase delay (when MCLK = 4.096 MHz).
54DS487PP4
CS5460A
5.2 Current Channel DC Offset Register and Voltage Channel DC Offset Register
Address:1 (Current Channel DC Offset Register)
3 (Voltage Channel DC Offset Register)
MSBLSB
0
-(2
)2-12
Default** = 0.000
The DC offset registers are initialized to zero on reset, allowing the device to function and perform measurements. The register is loaded after one computation cycle with the current or voltage offset when the proper input
is applied and the DC Calibration Command is received. DRDY will be asserted at the end of the calibration.
The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range ± full scale. The numeric format of this register is two’s complement notation.
5.3 Current Channel Gain Register and Voltage Channel Gain Register
Address:2 (Current Channel Gain Register)
MSBLSB
1
2
0
2
-2
-3
2
-4
2
-5
2
-6
2
4 (Voltage Channel Gain Register)
-1
2
-2
2
-3
2
-4
2
-5
2
-7
2
2
.....
-6
.....
-17
2
-16
2
-18
2
-17
2
-19
2
-18
2
-20
2
-19
2
-21
2
-20
2
-22
2
-21
2
-23
2
-22
2
Default** = 1.000
The gain registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. The
gain registers hold the result of either the AC or DC gain calibrations, whichever was most recently performed.
If DC calibration is performed, the register is loaded after one computation cycle with the system gain when the
proper DC input is applied and the Calibration Command is received. If AC calibration is performed, then after
~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register) the register(s) is loaded
with the system gain when the proper AC input is applied and the Calibration Command is received. DRDY will
be asserted at the end of the calibration. The register may be read and stored so the register may be restored
with the desired system offset compensation. The value is in the range 0.0 ≤ Gain < 4.0.
5.4 Cycle Count Register
Address: 5
MSBLSB
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
2
.....
6
2
5
2
4
2
3
2
2
2
1
2
Default** = 4000
The Cycle Count Register value (denoted as ‘N’) specifies the number of A/D conversion cycles per computationcycle. For each computation cycle, the updated results in the RMS and Energy Registers are computed using
the most recent set of N continuous instantaneous voltage/current samples. When the device is commanded
to operate in ’continuous computation cycles’ data acquisition mode, the computation cycle frequency is
(MCLK/K)/(1024∗N) where MCLK is master clock input frequency (into XIN/XOUT pins), K is the clock divider
value (as specified in the Configuration Register), and N is Cycle Count Register value.
0
2
DS487PP455
CS5460A
5.5 Pulse-Rate Register
Address: 6
MSBLSB
18
2
17
2
16
2
15
2
Default** = 32000.00Hz
14
2
13
2
12
2
11
2
.....
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT
pin. Each EOUT
pulse represents a predetermined magnitude of real (billable) energy. The register’s smallest valid value is 2
butcanbein2-5increments.
5.6 I,V,P,E Signed Output Register Results
Address: 7 - 10
MSBLSB
0
-(2
)2-12
These signed registers contain the last value of the measured results of I, V, P, and E. The results are in the
range of -1.0 ≤ I, V, P, E < 1.0. The value is represented in two's complement notation, with the binary point
place to the right of the MSB (which is the sign bit). I, V, P, and E are output results registers which contain
signed values. Note that the I, V, and P Registers are updated every conversion cycle, while the E Register is
only updated after each computation cycle. The numeric format of this register is two’s complement notation.
5.7 I
RMS,VRMS
Address: 11,12
MSBLSB
-1
2
-2
2
These unsigned registers contain the last value of the calculated results of I
the range of 0.0 ≤ I
theleftoftheMSB.I
-2
-3
2
-4
2
-5
2
-6
2
Unsigned Output Register Results
-3
2
-4
2
RMS,VRMS
RMS
2
and V
-5
-6
2
-7
2
< 1.0. The value is represented in binary notation, with the binary point place to
are output result registers which contain unsigned values.
RMS
-7
2
2
.....
-8
.....
-17
2
-18
2
-18
2
-19
2
-19
2
-20
2
RMS
-20
2
-21
2
and V
-21
2
-22
2
. The results are in
RMS
-22
2
-23
2
-4
-23
2
-24
2
5.8 Timebase Calibration Register
Address: 13
MSBLSB
0
2
56DS487PP4
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
.....
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
2
Default** = 1.000
The Timebase Calibration Register is initialized to 1.0 on reset, allowing the device to function and perform computations. The register is user loaded with the clock frequency error to compensate for a gain error caused by
the crystal/oscillator tolerance. The value is in the range 0.0 ≤ TBC < 2.0.
CS5460A
5.9 Power Offset Register
Address:14
MSBLSB
0
-(2
)2-12
Default** = 0.000
This offset value is added to each power value that is computed for each voltage/current sample pair before
being accumulated in the Energy Register. The numeric format of this register is two’s complement notation.
This register can be used to offset contributions to the energy result that are caused by undesirable sources of
energy that are inherent in the system.
5.10 Current Channel AC Offset Register and Voltage Channel AC Offset Register
Address:16 (Current Channel AC Offset Register)
MSBLSB
-13
2
-14
2
Default** = 0.000
-2
-3
2
-4
2
-5
2
-6
2
-7
2
17 (Voltage Channel AC Offset Register)
-15
2
-16
2
-17
2
-18
2
-19
2
-20
2
.....
.....
-17
2
-30
2
-18
2
-31
2
-19
2
-32
2
-20
2
-33
2
-21
2
-34
2
-22
2
-35
2
-23
2
-36
2
The AC offset registers are initialized to zero on reset, allowing the device to function and perform measurements. First, the ground-level input should be applied to the inputs. Then the AC Offset Calibration Command
is should be sent to the CS5460A. After ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register), the gain register(s) is loaded with the square of the system AC offset value. DRDY will be
asserted at the end of the calibration. The register may be read and stored so the register may be restored with
the desired system offset compensation. Note that this register value represents the square of the AC current/voltage offset.
5.11 Status Register and Mask Register
Address:15 (Status Register)
26 (Mask Register)
2322212019181716
DRDYEOUTEDIRCRDYMATHResIORVOR
15141312111098
PWORIRORVROREOREOORResID3ID2
76543210
ID1ID0WDTVODIODLSD0
Default** = Binary: 00000000000000xxxx000001 (Status Register){x = state depends on device revision}
Binary: 000000000000000000000000 (Mask Register)
The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit
to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user
can write logic ‘1’ values back to the Status Register to selectively clear only those bits that have been resolved/registered by the system MCU, without concern of clearing any newly set bits. Even if a status bit is
masked to prevent the interrupt, the corresponding status bit will still be set in the Status Register so the user
can poll the status.
IC
DS487PP457
CS5460A
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will
allow the corresponding bit in the Status Register to activate the INT
pin when the status bit becomes active.
IC
LSDLow Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh-
IODModulator oscillation detect on the current channel. Set when the modulator oscillates due to
VODModulator oscillation detect on the voltage channel. Set when the modulator oscillates due to
WDTWatch-Dog Timer. Set when there has been no reading of the Energy Register for more than 5
Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command.
Can be deactivated only by sending a port initialization sequence to the serial port (or by executing a software/hardware reset). When writing to the Status Register, this bit is ignored.
old (PMLO), with respect to VA- pin. For a given part, PMLO can be as low as 2.3 V. LSD bit
cannot be permanently reset until the voltage at PFMON pin rises back above the high-voltage
threshold (PMHI), which is typically 100mV above the device’s low-voltage threshold. PMHI will
never be greater than 2.7 V.
an input above Full Scale. Note that the level at which the modulator oscillates is significantly
higher than the current channel’s Differential Input Voltage Range.
an input above Full Scale. Note that the level at which the modulator oscillates is significantly
higher than the current channel’s Differential Input Voltage Range.
Note:The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the
power line. This event should not be confused with a DC overload situation at the
inputs, when the IOD and VOD bits will re-assert themselves even after being
cleared, multiple times.
seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy Register, then write
to the Status Register with this bit set to logic '1'. When MCLK / K is not 4.096 MHz, the time
duration is 5 * [4.096 MHz / (MCLK / K)] seconds.
ID3:0Revision/Version Identification.
EOORThe internal EOUT
ergy Accumulation Register is different than the Energy Register available through the serial
port. This register cannot be read by the user. Assertion of this bit can be caused by having
an output rate that is too small for the power being measured. The problem can be corrected
by specifying a higher frequency in the Pulse-Rate Register.
EOREnergy Out of Range. Set when the Energy Register overflows, because the amount of energy
that has been accumulated during the pending computation cycle is greater than the register’s
highest allowable positive value or below the register’s lowest allowable negative value.
VRORRMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the
RMS Voltage Register.
IRORRMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the
RMS Current Register.
PWORPower Calculation Out of Range. Set when the magnitude of the calculated power is too large
to fit in the Instantaneous Power Register.
VORVoltage Out of Range.
IORCurrent Out of Range. Set when the magnitude ofthecalibratedcurrentvalueistoolargeor
too small to fit in the Instantaneous Current Register.
MATHGeneral computation Indicates that a divide operation overflowed. This can happen normally
in the course of computation. If this bit is asserted but no other bits are asserted, then there is
no error, and this bit should be ignored.
Energy Accumulation Register went out of range. Note that the EOUT En-
58DS487PP4
CS5460A
CRDYConversion Ready. Indicates a new conversion is ready. This will occur at the output word rate,
which is usually 4 kHz.
EDIRSet whenever the EOUT bit asserted (see below) if the accumulated energy is negative.
EOUTIndicates that enough positive/negative energy has been reached within the internal EOUT
ergy Accumulation Register (not accessible to user) to mandate the generation of one or more
pulses on the EOUT
negative energy or positive energy. (The sign is determined by the EDIR bit, described above).
This EOUT bit is cleared automatically when the energy rate drops below the level that produc-
es a 4 KHz EOUT pin rate. The bit can also be cleared by writing to the Status Register. This
status bit is set with a maximum frequency of 4 KHz (when MCLK/K is 4.096 MHz). When
MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate that one would expect
to get with MCLK/K = 4.096 MHz by a factor of 4.096 MHz / (MCLK/K) to get the actual
pulse-rate.
DRDYData Ready. When running in ’single computation cycle’ or ’continuous computation cycles’
data acquisition modes, this bit will indicate the end of computation cycles. When running cal-
ibrations, this bit indicates that the calibration sequence has completed, and the results have
been stored in the offset or gain registers.
pin (if enabled, see Configuration Register). The energy flow may indicate
5.12 Control Register
Address: 28
2322212019181716
ResResResResResResResRes
15141312111098
ResResResResResResResSTOP
76543210
ResMECHResINTLSYNCNOCPUNOOSCSTEP
En-
Default** = 0x000000
STOP1 = used to terminate the new EEBOOT sequence.
ResReserved. These bits must be set to zero.
MECH1 = widens EOUT
INTL1 = converts the INT
SYNC1 = forces internal A/D converter clock to synchronize to the initiation of a conversion command.
NOCPU1 = converts the CPUCLK output to a one-bit output port. Reduces power consumption.
NOOSC1 = saves power by disabling the crystal oscillator for external drive.
STEP1 = enables stepper-motor signals on the EOUT
DS487PP459
and EDIR pulses for mechanical counters.
output to open drain configuration.
/EDIR pins.
6. PIN DESCRIPTION
Crystal OutXOUT
CPU Clock OutputCPUCLK
Positive Digital SupplyVD+
Digital GroundDGND
Serial Clock InputSCLK
Serial Data OutputSDO
Chip SelectCS
Mode SelectMODE
Differential Voltage InputVIN+
Differential Voltage InputVIN-
Voltage Reference OutputVREF OUT
Voltage Reference InputVREFIN
XINCrystal In
1
2
3
4
5
6
7
817
9
10
11
1213
24
SDISerial Data Input
23
EDIR
22
EOUT
21
INT
20
RESET
19
NCNo Connect
18
PFMONPower Fail Monitor
IIN+Differential Current Input
16
IIN-Differential Current Input
15
VA+Positive Analog Supply
14
VA-Analog Ground
CS5460A
Energy Direction Indicator
Energy Output
Interrupt
Reset
Clock Generator
Crystal Out
1,24XOUT, XIN - A gate inside the chip is connected to these pins and can be used with a
Crystal In
CPU Clock Output
2CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
Control Pins and Serial Data I/O
Serial Clock Input
Serial Data Output
Chip Select
Mode Select
Interrupt
Energy Output
Energy Direction
5SCLK - A clock signal on this pin determines the input and output rate of the data for the
6SDO - SDO is the output pin of the serial data port. Its output will be in a high impedance
7CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO
8MODE - When at logic high, the CS5460A can perform the auto-boot sequence with the
20INT - When INT goes low it signals that an enabled event has occurred. INT is cleared
21EOUT - The energy output pin output a fixed-width pulse rate output with a rate (pro-
22
Indicator
Serial Data Input
23SDI - the input pin of the serial data port. Data will be input at a rate determined by SCLK.
Measurement and Reference Input
Differential
9,10VIN+, VIN- - Differential analog input pins for voltage channel.
Voltage Inputs
crystal to provide the system clock for the device. Alternatively, an external (CMOS
compatible clock) can be supplied into XIN pin to provide the system clock for the device.
SDI and SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time
signals. The SCLK pin will recognize clocks only when CS
state when CS
pin to a high impedance state. CS
aid of an external serial EEPROM to receive commands and settings. When at logic low,
the CS5460A assumes normal “host mode” operation. This pin is pulled down to logic
low if left unconnected, by an internal pull-down resistor to DGND.
(logic 1) by writing the appropriate command to the CS5460A.
grammable) proportional to real (billable) energy.
EDIR
- The energy direction indicator indicates if the measured energy is negative.
is high.
should be changed when SCLK is low.
is low.
60DS487PP4
CS5460A
Vol tage
11VREFOUT - The on-chip voltage reference is output from this pin. The voltage reference
Reference Output
Vol tage
12VREFIN - The voltage input to this pin establishes the voltage reference for the on-chip
Reference Input
Differential
15,16IIN+, IIN- - Differential analog input pins for current channel.
Current Inputs
Power Supply Connections
Positive
Digital Supply
Digital Ground
Negative
13VA- - The negative analog supply pin must be at the lowest potential.
Analog Supply
Positive
14VA+ - The positive analog supply is nominally +5 V ±10% relative to VA-.
Analog Supply
Power Fail Monitor
17PFMON - The power fail Monitor pin monitors the analog supply. Typical threshold level
RESET19
has a nominal magnitude of 2.5 V and is reference to the VA- pin on the converter.
modulator.
3VD+ - The positive digital supply is nominally +5 V ±10% relative to DGND.
4DGND - The common-mode potential of digital ground must be equal to or above the
common-mode potential of VA-.
(PMLO) is 2.45 V with respect to the VA- pin. If PFMON voltage threshold is tripped, the
LSD (low-supply detect) bit is set in the Status Register. Once the LSD bit has been set,
it will not be able to be reset until the PFMON voltage increases ~100 mV (typical) above
the PMLO voltage. Therefore, there is hysteresis in the PFMON function.
Reset - When reset is taken low, all internal registers are set to their default states.
Other
No Connection18NC - No connection. Pin should be left floating.
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
62DS487PP4
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