Cirrus Logic CS5460A User Manual

CS5460A

PGA
x10,x50

VA+ VD+

IIN+

IIN-

VIN+

VIN-

VREFIN

VREFOUT

VA- XIN XOUT CPUCLK DGND

CS

SDO

SDI

SCLK
INT

EOUT

Digital

Filter

High Pass

Filter

Voltage

Reference

System

Clock

/K

Clock

Generator

Serial

Interface

Power

Calculation

Engine

(Energy

I*V

I,V )

RMS RMS

Energy-to-

Pulse

Converter

Power

Monitor

PFMON

x1

x10

4 Order



Modulator

th

RESET

Digital

Filter

Calibration

SRAM

EDIR

High Pass

Filter

2 Order
Modulator

nd

WatchDog

Timer

MODE

Control /



Single Phase, Bi-directional Power/Energy IC

Features

 Energy Data Linearity: ±0.1% of Reading

over 1000:1 Dynamic Range.

 On-Chip Functions: (Real) Energy, I  V,

I

and V

RMS

Conversion

 Smart “Auto-boot” Mode from Serial

EEPROM Enables Use without MCU.

 AC or DC System Calibration
 Mechanical Counter/Stepper Motor Driver
 Meets Accuracy Spec for IEC 687/1036, JIS
 Typical Power Consumption <12 mW
 Interface Optimized for Shunt Sensor
 V vs. I Phase Compensation
 Ground-Referenced Signals with Single

Supply

 On-chip 2.5 V Reference (MAX 60 ppm/°C

drift)

 Simple Three-wire Digital Serial Interface
 Watch Dog Timer
 Power Supply Monitor
 Power Supply Configurations

VA+ = +5 V; VA- = 0 V; VD+ = +3.3 V to +5 V

, Energy-to-Pulse

RMS

Description

The CS5460A is a highly integrated power mea­surement solution which combines two 
Analog-to-digital Converters (ADCs), high-speed
power calculation functions, and a serial interface
on a single chip. It is designed to accurately mea­sure and calculate: Real (True) Energy,
Instantaneous Power, I
phase 2- or 3-wire power metering applications.
The CS5460A interfaces to a low-cost shunt resis­tor or transformer to measure current, and to a
resistive divider or potential transformer to mea­sure voltage. The CS5460A features a
bi-directional serial interface for communication
with a microcontroller and a pulse output engine for
which the average pulse frequency is proportional
to the real power. The CS5460A has on-chip func­tionality to facilitate AC or DC system-level
calibration.

The “Auto-boot” feature allows the CS5460A to
function ‘stand-alone’ and to initialize itself on sys­tem power-up. In Auto-boot Mode, the CS5460A
reads the calibration data and start-up instructions
from an external EEPROM. In this mode, the
CS5460A can operate without a microcontroller, in
order to lower the total bill-of-materials cost.

RMS

, and V

RMS

for single

Cirrus Logic, Inc.

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2011

(All Rights Reserved)

APR ‘11

DS487F5

1

TABLE OF CONTENTS

1. CHARACTERISTICS & SPECIFICATIONS ............................................................................. 5

ANALOG CHARACTERISTICS................................................................................................5

VREFOUT REFERENCE OUTPUT VOLTAGE.......................... ... ... ... ... .... ... ... ... .... ... ... ... ... .... . 7

5V DIGITAL CHARACTERISTICS............................................................................................ 7

3.3 V DIGITAL CHARACTERISTICS........................................................................................ 8

ABSOLUTE MAXIMUM RATINGS ...........................................................................................8

SWITCHING CHARACTERISTICS .......................................................................................... 9

2. OVERVIEW ............................................................................................................................. 12

2.1 Theory of Operation ................................................................ ... ... ... ................................12

2.1.1 DS Modulators ................................ ... ... .... ... .......................................... ... ... ... ... 12

2.1.2 High-rate Digital Low-pass Filters ....................................................................... 12

2.1.3 Digital Compensation Filters ......... ... ... ... .... ... ... ... ............................................. ... 12

2.1.4 Digital High-pass Filters ...................................................................................... 12

2.1.5 Overall Filter Response ....................... ................ ................ ................. ............... 13

2.1.6 Gain and DC Offset Adjustment .............................. ... ... ... ................................... 13

2.1.7 Real Energy and RMS Computations .................................................................13

2.2 Performing Measurements .................................. .... ... ... ... .... ... ... ... ... ................................ 13

2.2.1 CS5460A Linearity Performance .......................................................... ... ... ... ......15

2.2.2 Single Computation Cycle (C=0) ......................................................................... 15

2.2.3 Continuous Computation Cycles (C=1) .. .... ... ... ............................................. ... ... 16

2.3 Basic Application Circuit Configurations ..........................................................................16

3. FUNCTIONAL DESCRIPTION ...............................................................................................21

3.1 Pulse-Rate Output .............................................. .............................................. ...............21

3.2 Pulse Output for Normal Format, Stepper Motor Format and Mechanical Counter Format 22

3.2.1 Normal Format .......... .... .......................................... ... ... ... ... .... ... ... ......................22

3.2.2 Mechanical Counter Format ................................................................................23

3.2.3 Stepper Motor Format .........................................................................................23

3.3 Auto-boot Mode Using EEPROM .....................................................................................24

3.3.1 Auto-boot Configuration ......... ... .... ... ... ... .... .........................................................24

3.3.2 Auto-boot Data for EEPROM ..............................................................................25

3.3.3 Application Note AN225 ... ... ... ... .... ... ... ... .... ... ... ............................................. ... ... 26

3.4 Interrupt and Watchdog Timer ............................ .... ... ... ... .... ... ... ...................................... 26

3.4.1 Interrupt ............................... ... ... .... ... ... ... .... .......................................... ... ... ... ... ... 26

3.4.1.1 Clearing the Status Register ...............................................................26

3.4.1.2 Typical use of the INT pin ...................................................................26

3.4.1.3 INT Active State ..................................................................................26

3.4.1.4 Exceptions ........... ... .......................................... ... .... ... ... ... .... ... ............26

3.4.2 Watch Dog Timer ................................................................................................26

3.5 Oscillator Characteristics .................... ... .... ... ... ... .... ... ... ............................................. ... ...27

3.6 Analog Inputs ................ ... ... ... .... ... ... .......................................... ... ... .... ... ... ... .... ...............27

3.7 Voltage Reference ........................... ... ... .... ............................................. .........................27

3.8 Calibration . ... .... ... ... ... .... ... ... .......................................... ... .... ... ... ... ... .... ............................27

3.8.1 Overview of Calibration Process .........................................................................27

3.8.2 The Calibration Registers .................................................................................... 28

3.8.3 Calibration Sequence ............................. .... ............................................. ............28

3.8.4 Calibration Signal Input Level .............................................................................29

3.8.5 Calibration Signal Frequency ..............................................................................29

3.8.6 Input Configurations for Calibrations ...................................................................29

3.8.7 Description of Calibration Algorithms .................................................................. 30

3.8.7.1 AC Offset Calibration Sequence .........................................................30

3.8.7.2 DC Offset Calibration Sequence ......................................................... 31

3.8.7.3 AC Gain Calibration Sequence ...........................................................31

CS5460A

2 DS487F5

CS5460A

3.8.7.4 DC Gain Calibration Sequence ......................................................... 31

3.8.8 Duration of Calibration Sequence ....................................................................... 31

3.9 Phase Compensation ......... ... .... ... ... ............................................. ... .... ............................ 31

3.10 Time-Base Calibration Register ..................................................................................... 32

3.11 Power Offset Register ................................................................................................... 32

3.12 Input Protection - Current Limit ...................................................................................... 32

3.13 Input Filtering ................................................................................................................. 34

3.14 Protection Against High-voltage and/or High-current Surges ............................... ......... 37

3.15 Improving RFI Immunity ................................................................................................ 38

3.16 PCB Layout ................................................................................................................... 38

4. SERIAL PORT OVERVIEW .................................................................................................... 38

4.1 Commands (Write Only) ......................................... ............................................. ... ... ... ... 39

4.2 Serial Port Interface ............................ ... .............................................. ... ... ...................... 42

4.3 Serial Read and Write ........................... .... ... ... ... .... ... ... ... .... ............................................ 42

4.3.1 Register Write ........................ ... .... ... ... ............................................. ................... 42

4.3.2 Register Read ........ ... .... ... ... ... ... .......................................... .... ... ... ... .... ... ... ......... 42

4.4 System Initialization ...................... ... ... ............................................................................. 42

4.5 Serial Port Initialization .............................. ... ... ... .... ......................................................... 43

4.6 CS5460A Power States ................................................................................................... 43

5. REGISTER DESCRIPTIONS ................................................................................................. 44

5.1 Configuration Register............ .... ... ... ... ... .... ... ... .......................................... ... .... ... ... ... ... ...44

5.2 Current Channel DC Offset Register and Voltage Channel DC Offset Register .............. 46

5.3 Current Channel Gain Register and Voltage Channel Gain Register............................... 46

5.4 Cycle Count Register........................................................................................................46

5.5 Pulse-Rate Register ................... ... ... ... ... .... ... ... ................................................................47

5.6 I,V,P,E Signed Output Register Results ........................................................................... 47

5.7 IRMS, VRMS Unsigned Output Register Results............................................................. 47

5.8 Timebase Calibration Register ............................................. ... ... ... ... .... ............................ 47

5.9 Power Offset Register ...................................................................................................... 48

5.10 Current Channel AC Offset Register and Voltage Channel AC Offset Register............. 48

5.11 Status Register and Mask Register................................................................................ 48

5.12 Control Register.............................................................................................................. 50

6. PIN DESCRIPTIONS .............................................................................................................. 51

7. PACKAGE DIMENSIONS ...................................................................................................... 53

8. ORDERING INFORMATION ................................................................................................. 54

9. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ............................ 54

10. REVISION HISTORY ... ... .... ... ... ... .... ... ... ................................................................................ 54

DS487F5 3

LIST OF FIGURES

Figure 1. CS5460A Read and Write Timing Diagrams..................................................................10

Figure 2. CS5460A Auto-Boot Sequence Timing..........................................................................11

Figure 3. Data Flow....................................................................................................................... 13

Figure 4. Voltage Input Filter Characteristics ................................................................................ 14

Figure 5. Current Input Filter Characteristics ................................................................................14

Figure 6. Typical Connection Diagram (One-Phase 2-Wire, Direct Connect to Power Line)........17

Figure 7. Typical Connection Diagram (One-Phase 2-Wire, Isolated from Power Line)...............18

Figure 8. Typical Connection Diagram (One-Phase 3-Wire).........................................................19

Figure 9. Typical Connection Diagram (One-Phase 3-Wire - No Neutral Available).....................20

Figure 10. Time-plot representation of pulse output for a typical burst of pulses (Normal Format)23

Figure 11. Mechanical Counter Format on EOUT and EDIR ........................................................23

Figure 12. Stepper Motor Format on EOUT and EDIR .................................................................24

Figure 13. Typical Interface of EEPROM to CS5460A..................................................................24

Figure 14. Timing Diagram for Auto-Boot Sequence ....................................................................25

Figure 15. Oscillator Connection...................................................................................................27

Figure 16. System Calibration of Gain. ......................................................................................... 30

Figure 17. System Calibration of Offset. ....................................................................................... 30

Figure 18. Calibration Data Flow................................................................................................... 30

Figure 19. Example of AC Gain Calibration ..................................................................................31

Figure 20. Input Protection for Single-Ended Input Configurations...............................................37

Figure 21. CS5460A Register Diagram......................................................................................... 44

CS5460A

LIST OF TABLES

Table 1. Differential Input Voltage vs. Output Code......................................................................14

Table 2. Available range of ±0.1% output linearity,

with default settings in the gain/offset registers. ...........................................................15

Table 3. Default Register Values upon Reset Event.....................................................................43

4 DS487F5

CS5460A

1. CHARACTERISTICS & SPECIFICATIONS ANALOG CHARACTERISTICS

(TA= -40 °C to +85 °C; VA+ = VD+ = +5 V ±10%; VREFIN = +2.5 V; VA- = AGND = 0 V; MCLK = 4.096 MHz,
K = 1; N = 4000 ==> OWR = 4000 Sps.)(See Notes 1, 2, 3, 4, and 5.)

Parameter Symbol Min Typ Max Unit

Accuracy (Both Channels)

Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB
Offset Drift (Without the High Pass Filter) - 5 - nV/°C

Analog Inputs (Current Channel)

Maximum Differential Input Voltage Range (Gain = 10)
{(V

IIN+) - (VIIN-)} (Gain = 50)

Total Harmonic Distortion THDI 80 - - dB
Common Mode + Signal on IIN+ or IIN- (Gain = 10 or 50) -0.25 - VA+ V
Crosstalk with Voltage Channel at Full Scale (50, 60 Hz) - - -115 dB
Input Capacitance (Gain = 10)

(Gain = 50)

Effective Input Impedance (Note 6)

(Gain = 10)

(Gain = 50)

Noise (Referred to Input) (Gain = 10)

(Gain = 50)

Accuracy (Current Channel)

Bipolar Offset Error (Note 1) VOS
Full-Scale Error (Note 1) FSE

Analog Inputs (Voltage Channel)

Maximum Differential Input Voltage Range {(V

VIN+) - (VVIN-)} VIN --500mV

Total Harmonic Distortion THDV 62 - - dB
Common Mode + Signal on VIN+ or VIN- VA- - V A+ V
Crosstalk with Current Channel at Full Scale (50, 60 Hz) - - -70 dB
Input Capacitance C
Effective Input Impedance (Note 6) Z
Noise (Referred to Input) - - 250 µV

Accuracy (Voltage Channel)

Bipolar Offset Error (Note 1) VOS
Full-Scale Error (Note 1) FSE

IN -

I

-

C

in -

-

Z

inI

ZinI

-

-

-

-

I - ±0.001 - %F.S.

I - ±0.001 - %F.S.

inV -0.2-pF
inV -5-M

V - ±0.01 - %F.S.

V - ±0.01 - %F.S.

25
25

30
30

-

-

-

-

500
100

-

-

-

-

20

4

mV
mV

µV
µV

P-P
P-P

pF
pF

k
k

rms
rms

P-P

rms

Notes:

1. Bipolar Offset Errors and Full-Scale Gain Errors for the current and voltage channels refer to the respective Irms
Register and Vrms Register output, when the device is operating in ‘continuous computation cycles’ data acquisition
mode, after offset/gain system calibration sequences have been executed. These specs do not apply to the error
of the Instantaneous Current/Voltage Register output.

2. Specifications guaranteed by design, characterization, and/or test.

3. Analog signals are relative to VA- and digital signals to DGND unless otherwise noted.

4. In requiring VA+ = VD+ =5 V ±10%, note that it is allowable for VA+, VD+ to differ by as much as ±200 mV, as long
as VA+ > VD+.

5. Note that “Sps” is an abbreviation for units of “samples per second”.

6. Effective Input Impedance (Zin) is determined by clock frequency (DCLK) and Input Capacitance (IC).
Zin = 1/(IC*DCLK/4). Note that DCLK = MCLK / K.

DS487F5 5

CS5460A

PSRR 20

0.150V
V

eq

------------------ -







log=

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Unit

Dynamic Characteristics

Phase Compensation Range (Voltage Channel, 60 Hz) -2.4 - +2.5 °
High Rate Filter Output Word Rate (Both Channels) OWR - DCLK/1024 - Sps
Input Sample Rate DCLK = MCLK/K - DCLK/8 - Sps
Full Scale DC Calibration Range (Note 7) FSCR 25 - 100 %F.S.
Channel-to-Channel Time-Shift Error

(when PC[6:0] bits are set to “0000000”)
High Pass Filter Pole Frequency -3 dB - 0.5 - Hz

Power Supplies

Power Supply Currents (Active State) I

I

(VD+ = 5 V)

D+

(VD+ = 3.3 V)

I

D+

Power Consumption Active State (VD+ = 5 V)
(Note 8) Active State (VD+ = 3.3 V)

Stand-By State

Sleep State

A+

PSCA
PSCD
PSCD

PC -

-

-

-

-

-

-

Power Supply Rejection Ratio (50, 60 Hz)
for Current Channel (Gain = 10)
(Note 9) (Gain = 50)

PSRR
PSRR

56
75

Power Supply Rejection Ratio (50, 60 Hz)
for Voltage Channel (Note 9) PSRR - 65 - dB

PFMON Power-Fail Detect Threshold (Note 10) PMLO 2.3 2.45 - V
PFMON “Power-Restored” Detect Threshold (Note 11) PMHI - 2.55 2.7 V

1.0 µs

1.3

2.9

1.7
21

11.6

6.75
10

-

-

25

-

-

-

mA
mA
mA

mW

-

-

-

mW
mW

µW

-

-

dB
dB

Notes: 7. The minimum FSCR is limited by the maximum allowed gain register value.

8. All outputs unloaded. All inputs CMOS level.

9. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV zero-to-peak sinewave
(frequency = 60 Hz) is imposed onto the +5V supply voltage at VA+ and VD+ pins. The “+” and “-” input
pins of both input channels are shorted to VA-. Then the CS5460A is commanded to ’continuous
computation cycles’ data acquisition mode, and digital output data is collected for the channel under
test. The zero-peak value of the digital sinusoidal output signal is determined, and this value is
converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the
channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as
Veq. PSRR is then (in dB):

10. When voltage level on PFMON is sagging, and LSD bit is 0, the voltage at which LSD bit is set to 1.

11. Assuming that the LSD bit has been set to 1 (because PFMON voltag e fell below PMLO), the n if/when
the PFMON voltage starts to rise again, PMHI is the volta ge level (on PFMON pin) at which the LSD bit
can be permanently reset back to 0 (without instantaneously changing back to 1). Attempts to reset the
LSD bit before this condition is true will not be successful. This condition indicates that power has been
restored. Typically, for a given sample, the PMHI voltage will be ~100 mV above the PMLO voltage.

6 DS487F5

CS5460A

(VREFOUTMAX - VREFOUTMIN)

VREFOUT

AVG TAMAX - T

A

MIN

1

(())

1.0 x 10

()

6

T

VREFOUT

=

VREFOUT REFERENCE OUTPUT VOLTAGE

Parameter Symbol Min Typ Max Unit

Reference Output

Output Voltage REFOUT +2.4 - +2.6 V
VREFOUT Temperature Coefficient (Note 12) T
Load Regulation (Output Current 1µA Source or Sink) V

Reference Input

Input Voltage Range VREFIN +2.4 +2.5 +2.6 V
Input Capacitance - 4 - pF
Input CVF Current - 25 - nA

Notes: 12. The voltage at VREFOUT is measured across the temperature range. From these measurements the

following formula is used to calculate the VREFOUT Temperature Coefficient:.

5V DIGITAL CHARACTERISTICS

(TA= -40 °C to +85 °C; VA+ = VD+ = 5 V ±10% VA-, DGND = 0 V) (See Notes 3, 4, and 13)

VREFOUT -3060ppm/°C

R

-610mV

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage

All Pins Except XIN, SCLK and RESET

XIN

SCLK and RESET

Low-Level Input Voltage

All Pins Except XIN, SCLK, and RESET

XIN

SCLK and RESET

High-Level Output Voltage (except XOUT) I
Low-Level Output Voltage (except XOUT) I

=+5mA V

out

=-5mA V

out

Input Leakage Current (Note 14) I
High Impedance State Leakage Current I
Digital Output Pin Capacitance C

V

IH

V

IL

OH
OL
in

OZ

out

0.6 VD+

(VD+) - 0.5

0.8VD+

-

-

-

-

-

-

-

-

-

0.8

1.5

0.2VD+

(VD+) - 1.0 - - V

--0.4V

-±1±10µA

--±10µA

-5-pF

13. Note that the 5 V characteristics are guaranteed by characterization. Only the more rigorous 3.3 V
digital characteristics are actually verified during production test.

14. Applies to all INPUT pins except XIN pin (leakage current < 50 µA) and MODE pin (leakage current <
25 µA).

-

-

-

V
V
V

V
V
V

DS487F5 7

CS5460A

3.3 V DIGITAL CHARACTERISTICS

(TA=-40°C to +85°C; VA+=5V±10%, VD+=3.3V±10%; VA-, DGND = 0 V) (See Notes 3, 4, and 13)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage

All Pins Except XIN, XOUT, SCLK, and RESET

XIN

SCLK and RESET

Low-Level Input Voltage

All Pins Except XIN, XOUT, SCLK, and RESET

XIN

SCLK and RESET

High-Level Output Vo ltage (except XIN, XOUT)I
Low-Level Output Voltage (except XIN, XOUT) I

=+5mA V

out

=-5mA V

out

Input Leakage Current (Note 14) I
3-State Leakage Current I
Digital Output Pin Capacitance C

V

IH

V

IL

OH
OL

in

OZ

out

0.6 VD+

(VD+) - 0.5

0.8VD+

-

-

-

-

-

-

-

-

-

-

-

-

0.48

0.3

0.2VD+

(VD+) - 1.0 - - V

--0.4V

-±1±10µA

--±10µA

-5-pF

V
V
V

V
V
V

Notes: 15. All measurements performed under static conditions.

16. If VD+ = 3 V and if XIN input is generated using crystal, then XIN frequency must remain between

2.5 MHz - 5.0 MHz. If using oscillator, full XIN frequency range is available, see Switching
Characteristics.

ABSOLUTE MAXIMUM RATINGS

(DGND = 0 V; See Note 17) WARNING: Operation at or beyond these limits may result in permanent damage to
the device. Normal operation is not guaranteed at these extremes.

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Notes 18 and 19)

Positive Digital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies(Note 20, 21, and 22) I
Output Current I
Power Dissipation (Note 23) P

Analog Input Voltage All Analog Pins V
Digital Input Voltage All Digital Pins V
Ambient Operating Temperature T
Storage Temperature T

VD+

VA+

VA-

IN

OUT

D --500mW

INA
IND

A

stg

-0.3

-0.3

+0.3

-

-

-

+6.0
+6.0

-6.0

--±10mA

--±25mA

(VA-) - 0.3 - (VA+) + 0.3 V

DGND - 0.3 - (VD+) + 0.3 V

-40 - 85 °C

-65 - 150 °C

V
V
V

Notes: 17. All voltages with respect to ground.

18. VA+ and VA- must satisfy {(VA+) - (VA-)}  +6.0 V.

19. VD+ and VA- must satisfy {(VD+) - (VA-)}  +6.0 V.

20. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins.

21. Transient current of up to 100 mA will not cause SCR latch-up.

22. Maximum DC input current for a power supply pin is ±50 mA.

23. Total power dissipation, including all input currents and output currents.

8 DS487F5

CS5460A

SWITCHING CHARACTERISTICS

(TA= -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels:
Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF))

Parameter Symbol Min Typ Max Unit

Master Clock FrequencyCrystal/Internal Gate Oscillator (Note 24) MCLK 2.5 4.096 20 MHz
Master Clock Duty Cycle 40 - 60 %
CPUCLK Duty Cycle (Note 25) 40 60 %
Rise Times Any Digital Input Except SCLK (Note 26)

SCLK

Any Digital Output

Fall Times Any Digital Input Except SCLK (Note 26)

SCLK

Any Digital Output

Start-up

Oscillator Start-Up Time XTAL = 4.096 MHz (Note 27) t

Serial Port Timing

Serial Clock Frequency SCLK - - 2 MHz
Serial Clock Pulse Width High

Pulse Width Low

SDI Timing

CS

Falling to SCLK Rising t
Data Set-up Time Prior to SCLK Rising t
Data Hold Time After SCLK Rising t
SCLK Falling Prior to CS

Disable t

SDO Timing

CS Falling to SDI Driving t
SCLK Falling to New Data Bit t

Rising to SDO Hi-Z t

CS

Auto-boot Timing

Serial Clock Pulse Width High

Pulse Width Low

MODE setup time to RESET
RESET
CS
SCLK falling to CS
CS

rising to CS falling t

falling to SCLK rising t

rising t

rising to driving MODE low (to end auto-boot sequence). t

Rising t

SDO guaranteed setup time to SCLK rising t

Notes: 24. Device parameters are specified with a 4.096 MHz clock, yet, clocks between 3 MHz to 20 MHz can be

used. However, for input frequencies over 5 MHz, an external oscillator must be used.

25. If external MCLK is used, then duty cycle must be between 45% and 55% to ma intain this specification.

26. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.

t

rise

t

fall

ost

t
t

t

10

t

11
12
13
14
15
16
17

-

-

-

-

-

-

50

50

-

-

-

-

1.0

100

-

1.0

100

-

µs
µs
ns

µs
µs
ns

-60-ms

1
2

3
4
5
6

7
8
9

200
200

50 - - ns

50 - - ns
100 - - ns
100 - - ns

-2050ns

-2050ns

-2050ns

-

-

8
8

-

-

ns
ns

MCLK
MCLK

50 ns

48 MCLK
100 8 MCLK

16 MCLK

50 ns
100 ns

DS487F5 9

CS5460A

CS

SCLK

MSB MSB - 1

LSB

t

2

t

1

t

3

SDI

MSB MSB - 1

LSB

Command Time 8 SCLKs

LSB

t

6

MSB MSB - 1

LSB

MSB MSB - 1

High Byte Mid Byte Low Byte

t

t

45

SDI Write Timing (Not to Scale)

CS

SDO

SCLK

MSB MSB- 1

LSB

t

2

t

1

t

8

t

7

SDI

MSB MSB - 1

LSB

Command Time 8 SCLKs

LSB

t

9

MSB MSB - 1

LSB

MSB MSB - 1

High Byte Mid Byte

Low Byte

M

u

s

t

s

t

r

o

b

e

"

S

Y

N

C

0

"

c

o

m

m

a

n

d

o

n

S

D

I

w

h

e

n

r

e

a

d

i

n

g

e

a

c

h

b

y

t

e

o

f

d

a

t

a

f

r

o

m

S

D

O

.

SDO Read Timing (Not to Scale)

Figure 1. CS5460A Read and Write Timing Diagrams

10 DS487F5

CS5460A

RES

SDI

SCLK

t

8

t

14

t

13

t

1

1

t

10

SDO

CS

t

5

t

4

Data from EEPROM

(Output)

(Output)

(Output)

(Input)

MODE

(Input)

t

12

t

15

t

16

STOP

BIT

LAST 8 BITS

(Input)

t

17

Figure 2. CS5460A Auto-boot Sequence Timing

DS487F5 11

CS5460A

2. OVERVIEW

The CS5460A is a CMOS monolithic power mea­surement device with a real power/energy compu­tation engine. The CS5460A combines two
programmable gain amplifiers, two  modulators,
two high rate filters, system calibration, and
rms/power calculation functions to provide instan­taneous voltage/current/power data samples as
well as periodic computation results for real (bill­able) energy, V
modate lower cost metering applications, the
CS5460A can also generate pulse-train signals on
certain output pins, for which the number of pulses
emitted on the pins is proportional to the quantity of
real (billable) energy registered by the device.

The CS5460A is optimized for power measure­ment applications and is designed to interface to a
shunt or current transformer to measure current,
and to a resistive divider or potential transformer to
measure voltage. To accommodate various input
voltage levels, the current channel includes a pro­grammable gain amplifier (PGA) which provides
two full-scale input levels, while the voltage chan­nel’s PGA provides a single input voltage range.
With a single +5 V supply on VA+/-, both of the
CS5460A’s input channels can accomodate com­mon mode + signal levels between -0.25 V and
VA+.

The CS5460A includes two high-rate digital filters
(one per channel), which decimate/integrate the
output from the 2  modulators. The filters yield
24-bit output data at a (MCLK/K)/1024 output word
rate (OWR). The OWR can be thought of as the ef­fective sample frequency of the voltage channel and
the current channel.

To facilitate communication to a microcontroller,
the CS5460A includes a simple three-wire serial
interface which is SPI™ and Microwire™ compati­ble. The serial port has a Schmitt Trigger input on
its SCLK (serial clock) and RESET
slow rise time signals.

RMS

, and I

. In order to accom-

RMS

pins to allow for

2.1 Theory of Operation

A computational flow diagram for the two data
paths is shown in Fig. 3. The reader should refer to
this diagram while reading the following data pro­cessing description, which is covered
block-by-block.

2.1.1  Modulators

The analog waveforms at the voltage/current chan­nel inputs are subject to the gains of the input
PGAs (not shown in Figure 3). These waveforms
are then sampled by the delta-sigma modulators at
a rate of (MCLK/K)/8 Sps.

2.1.2 High-rate Digital Low-pass Filters

The data is then low-pass filtered, to remove
high-frequency noise from the modulator output.
Referring to Figure 3, the high rate filter on the volt­age channel is implemented as a fixed Sinc
The current channel uses a Sinc
lows the current channel to make accurate mea­surements over a wider span of the total input
range, in comparison to the accuracy range of the
voltage channel. (This subject is discussed more in
Section 2.2.1)

Also note from Figure 3 that the digital data on the
voltage channel is subjected to a variable time-de­lay filter. The amount of delay depends on the val­ue of the seven phase compensation bits (see
Phase Compensation). Note that when the phase
compensation bits PC[6:0] are set to their default
setting of “0000000” (and if MCLK/K = 4.096 MHz)
then the nominal time delay that is imposed on the
original analog voltage input signal, with respect to
the original analog current input signal, is ~1.0
This translates into a delay of ~0.0216degrees at
60 Hz.

4

filter, which al-

2

filter.

µs.

2.1.3 Digital Compensation Filters

The data from both channels is then passed
through two FIR compensation filters, whose pur­pose is to compensate for the magnitude roll-off of
the low-pass filtering operation (mentioned earli­er).

2.1.4 Digital High-pass Filters

Both channels provide an optional high-pass filter
(denoted as “HPF” in Figure 3) which can be en­gaged into the signal path, to remove the DC con­tent from the current/voltage signal before the
RMS/energy calculations are made. These filters
are activated by enabling certain bits in the Config­uration Register.

If the high-pass filter is engaged in only one of the
two channels, then the all-pass filter (see “APF” in

12 DS487F5

CS5460A

VOLTAGE



SINC

2

+

x

V*

gn

x

V

*

CURRENT

SINC

4

+

x

I*

gn

x

x

TBC *

DELAY

REG

DELAY

REG

FIR HPF

APF

Configuration Register *

PC[6:0] Bits

x

I*

RMS

N

V*

RMS

N





4096

EtoF

E*

E
E

out
dir

PULSE-RATE*

* DENOTES REGISTER NAME



HPF

APF

FIR

SINC

2

I

*

P

*

N

SINC

2

-

-

I

ACoff

*

I

DCoff

*

V

ACoff

*

V

DCoff

*

+

P

off

*

÷

N

÷

N

Figure 3. Data Flow.

Figure 3) will be enabled on the other channel; in
order to preserve the relative phase relationship
between the voltage-sense and current-sense in­put signals. For example, i f the HPF is engaged for
the voltage channel, but not the current channel,
then the APF will be engaged in the current channel,
to nullify the additional phase delay introduced by
the high-pass filter in the current channel.

2.1.5 Overall Filter Response

When the CS5460A is driven with a 4.096 MHz
clock (K = 1), the composite magnitude response
(over frequency) of the voltage channel’s input fil­ter network is shown in Figure 4, while the com­posite magnitude response of the current
channel’s input filter network is given in Figure 5.
Note that the composite filter response of both
channels scales with MCLK frequency and K.

2.1.6 Gain and DC Offset Adjustment

After filtering, the instantaneous voltage and cur­rent digital codes are subjected to offset/gain ad­justments, based on the values in the DC offset
registers (additive) and the gain registers (multipli­cative). These registers are used for calibration of
the device (see Section 3.8, Calibration). After off­set and gain, the 24-bit instantaneous data sample
values are stored in the Instantaneous Voltage and
Current Registers.

2.1.7 Real Energy and RMS Computations

The digital instantaneous voltage and current data
is then processed further. Referring to Figure 3, the

DS487F5 13

instantaneous voltage/current data samples are
multiplied together (one multiplication for each pair
of voltage/current samples) to form instantaneous
(real) power samples. After each A/D conversion
cycle, the new instantaneous power sample is
stored in the Instantaneous Power Register.

The instantaneous power samples are then
grouped into sets of N samples (where N = value in
Cycle Count Register). The cumulative sum of
each successive set of N instantaneous power is
used to compute the result stored in the Energy
Register, which will be proportional to the amount
of real energy registered by the device during the
most recent N A/D conversion cycles. Note from
Figure 3 that the bits in this running energy sum
are right-shifted 12 times (divided by 4096) to
avoid overflow in the Energy Register. RMS calcu­lations are also performed on the data using the
last N instantaneous voltage/current samples, and
these results can be read from the RMS Voltage
Register and the RMS Current Register.

2.2 Performing Measurements

To summarize Section 2.1, the CS5460A performs
measurements of instantaneous current and in­stantaneous voltage, and from this, performs com­putations of the corresponding instantaneous
power, as well as periodic calculations of real en­ergy, RMS current, and RMS voltage. These mea­surement/calculation results are available in the
form of 24-bit signed and unsigned words. The
scaling of all output words is normalized to unity

full-scale. Note that the 24-bit signed output words

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

Frequency (Hertz)

Gain (dB)

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Figure 4. Voltage Input Filter Characteristics

-2.5

-2

-1.5

-1

-0.5

0

0.5

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Gain (d B)

Frequency (Hertz)

Figure 5. Current Input Filter Characteristics

are expressed in two’s complement format. The
24-bit data words in the CS5460A output registers
represent values between 0 and 1 (for unsigned
output registers) or between -1 and +1 (for signed
output registers). A register value of 1 represents
the maximum possible value. Note that a value of

1.0 is never actually obtained in the registers of the
CS5460A. As an illustration, in any of the signed
output registers, the maximum register value is
[(2^23 - 1) / (2^23)] = 0.999999880791. After each
A/D conversion, the CRDY bit will be asserted in
the Status Register, and the INT

pin will also be­come active if the CRDY bit is unmasked (in the
Mask Register). The assertion of the CRDY bit in­dicates that new instantaneous 24-bit voltage and
current samples have been collected, and these
two samples have also been multiplied together to
provide a corresponding instantaneous 24-bit pow­er sample.

Table 1 conveys the typical relationship between
the differential input voltage (across the “+” and “-”
input pins of the voltage channel input) and the cor­responding output code in the Instantaneous Volt­age Register. Note that this table is applicable for
the current channel if the current channel’s PGA
gain is set for the “10x” gain mode.

CS5460A

Output Code

Input Voltage (DC)

+250 mV

14.9 nV to 44.7 nV

-14.9 nV to 14.9 nV

-44.7 nV to -14.9 nV

-250 mV

T ab le 1. Differential Inpu t Voltage vs. Output Code

The V

RMS

, I

RMS

(hexidecimal)

7FFFFF 8388607

000001 1
000000 0

FFFFFF -1

800000 -8388608

, and energy calculations are up­dated every N conversions (which is known as 1
“computation cycle”), where N is the value in the
Cycle Count Register. At the end of each computa­tion cycle, the DRDY bit in the Mask Register will
be set, and the INT

pin will become active if the

DRDY bit is unmasked.
DRDY is set only after each computation cycle has

completed, whereas the CRDY bit is asserted after
each individual A/D conversion. Bits asserted by
the CS5460A must be cleared before being assert­ed again. If the Cycle Count Register value (N) is
set to 1, all output calculations are instantaneous,
and DRDY will indicate when instantaneous calcu­lations are finished, just like the CRDY bit. For the
RMS results to be valid, the Cycle-Count Register
must be set to a value greater than 10.

The computation cycle frequency is derived from
the master clock, and has a value of
(MCLK/K)/(1024*N). Under default conditions, with

Output Code

(decimal)

14 DS487F5

CS5460A

Energy Vrms Irms

Range (% of FS)

0.1% - 100% 50% - 100%

0.2% - 100%

Max. Differential

Input

not applicable

V-channel:

±250 mV

I-channel:

±250

mV 10x

±50

mV 50x

Linearity

0.1% of
reading

0.1% of
reading

0.1% of
reading

Table 2. Available range of ±0.1% output linearity, with

default settings in the gain/offset registers.

a 4.096 MHz clock at XIN, and K = 1, instanta­neous A/D conversions for voltage, current, and
power are performed at a 4000 Sps rate, whereas
I

RMS

, V

, and energy calculations are per-

RMS

formed at a 1 Sps rate.

2.2.1 CS5460A Linearity Performance

Table 2 lists the range of input levels (as a percent­age of full-scale) over which the (linearity + varia­tion) of the results in the Vrms, Irms and Energy
Registers are guaranteed to be within
reading after the completion of each successive
computation cycle. Note that until the CS5460A is
calibrated (see Calibration) the accuracy of the
CS5460A with respect to a reference line-voltage
and line-current level on the power mains is not
guaranteed to within

±0.1%. After both channels of

the device are calibrated for offset/gain, the ±0.1%
of reading spec will also reflect accuracy of the
Vrms, Irms, and Energy Register results. Finally,
observe that the maximum (full-scale) differential
input voltage for the voltage channel (and current
channel, when its PGA is set for 10x gain) is
250 mV (nominal). If the gain registers of both

channels are set to 1 (default) and the two DC
offset registers are set to zero (default), then a
250mV DC signal applied to the voltage/current
inputs will measure at (or near) the maximum
value of 0.9999... in the RMS Current/Voltage
Registers. Remember that the RMS value of a

250 mV (DC) signal is also 250 mV. However, for
either input channel, it would not be practical to in­ject a sinusoidal voltage with RMS value of
250 mV. This is because when the instantaneous
value of such a sine wave is at or near the level of
its positive/negative peak regions (over each cy-

±0.1 % of

cle), the voltage level of this signal would exceed
the maximum differential input voltage range of the
input channels. The largest sine wave voltage sig­nal that can be presented across the inputs, with
no saturation of the inputs, is:
250 mV / sqrt(2) = ~176.78 mV (RMS),
which is ~70.7% of full-scale. This would imply that
for the current channel, the (linearity+variation) tol­erance of the RMS measurements for a purely si­nusoidal 60 Hz input signal could be measured to
within

±0.1% of reading over a magnitude range of

0.2% - 70.7% of the maximum full-scale differen­tial input voltage level.

The range over which the (linearity + variation) will
remain within ±0.1% can often be increased by se­lecting a value for the Cycle-Count Register such
that the time duration of one computation cycle is
equal to (or very close to) a whole-number of pow­er-line cycles (and N must be greater than or equal
to 4000). For example, with the cycle count set to
4200, the ±0.1% of reading (linearity + variation)
range for measurement of a 60 Hz sinusoidal cur­rent-sense voltage signal can be increased beyond
the range of 0.2% - 70.7%. The accuracy range
will be increased because (4200 samples / 60 Hz)
is a whole number of cycles (70). Note that this in­crease in the measurement range refers to an ex­tension of the low end of the input scale (i.e., this
does not extend the high-end of the range above
100% of full-scale). This enables accurate mea­surement of even smaller power-line current lev­els, thereby extending the load range over which
the power meter can make accurate energy mea­surements. Increasing the accuracy range can be
beneficial for power metering applications which
require accurate power metering over a very large
load range.

DS487F5 15

2.2.2 Single Computation Cycle (C=0)

Note that ‘C’ refers to the value of the C bit, con­tained in the ‘Start Conversions’ command (see
Section 4.1). This commands instructs the
CS5460A to perform conversions in ‘single compu­tation cycle’ data acquisition mode. Based on the
value in the Cycle Count Register, a single compu­tation cycle is performed after a ‘Start Conversions’
command is sent to the serial interface. After the
computations are complete, DRDY is set. 32
SCLKs are then needed to read out a calculation

CS5460A

result from one of several result registers. The first
8 SCLKs are used to clock in the command to de­termine which register is to be read. The last 24
SCLKs are used to read the desired register. After
reading the data, the serial port remains in the ac-
tive state, and waits for a new command to be is­sued. (See Section 3 for more details on reading
register data from the CS5460A).

2.2.3 Continuous Computation Cycles (C=1)

When C = 1, the CS5460A will perform conversions
in ‘continuous computation cycles’ data acquisition
mode. Based on the information pro vided in the Cy­cle Count Register, computation cycles are repeat­edly performed on the voltage and current cha nnels
(after every N conversions). Computation cycles
cannot be started/stopped on a ‘per-channel’ basis.
After each computation cycle is completed, DRDY
is set. Thirty-two SCLKs are then needed to read a
register. The first 8 SCLKs are used to clock in the
command to determine which results register is to
be read. The last 24 SCLKs are used to read out the
24-bit calculation result. While in this acquisition
mode, the designer/programmer may choose to ac­quire (read) only those calculations required for
their particular application, as DRDY repeatedly in­dicates the availability of new data. No te again that
the MCU firmware must reset the DRDY bit to “0”
before it can be asserted again.

Referring again to Figure 3, note that within the
Irms and Vrms data paths, prior to the square-root
operation, the instantaneous voltage/current data
is low-pass filtered by a Sinc
is decimated to every Nth sample. Because of the

2

Sinc

filter operation, the first output for each chan­nel will be invalid (i.e. all RMS calculations are in­valid in the ‘single computation cycle’ data
acquisition mode and the first RMS calculation re­sults will be invalid in the ‘continuous computation
cycles’ data acquisition mode). However, all ener­gy calculations will be valid since energy calcula­tions do not require this Sinc

If the ’Start Conversions’ command is issued to the
CS5460A (see Section 4.1, Commands (Write On-
ly)), and if the ‘C’ bit in this command is set to a val­ue of ‘1’, the device will remain in its active state.
Once commanded into continuous computation

2

filter. Then the data

2

operation.

cycles data acquisition mode, the CS5460A will
continue to perform A/D conversions on the volt­age/current channels, as well as all subsequent
calculations, until:

1) the ‘Power-Up/Halt’ command is received
through the serial interface, or

2) loss of power, or

3) the RS bit in the Configuration Register is as­serted (‘software reset’), or

4) the /RESET pin is asserted and then de-assert­ed (‘hardware reset’).

2.3 Basic Application Circuit

Configurations

Figure 6 shows the CS5460A connected to a ser­vice to measure power in a single-phase 2-wire
system operating from a single power supply. Note
that in this diagram the shunt resistor used to mon­itor the line current is connected on the “Line” (hot)
side of the power mains. In most residential power
metering applications, the power meter’s cur­rent-sense shunt resistor is intentionally placed on
the ‘hot’ side of the power mains in order to help
detect any attempt by the subscriber to steal pow­er. In this type of shunt-resistor configuration, note
that the common-mode level of the CS5460A must
be referenced to the hot side of the power line. This
means that the common-mode potential of the
CS5460A will typically oscillate to very high posi­tive voltage levels, as well as very high negative
voltage levels, with respect to earth ground poten­tial. The designer must therefore be careful when
attempting to interface the CS5460A’s digital out­put lines to an external digital interface (such as a
LAN connection or other communication network).
Such digital communication networks may require
that the CMOS-level digital interface to the meter is
referenced to an earth-ground. In such cases, the
CS5460A’s digital serial interface pins must be iso-
lated from the external digital interface, so that
there is no conflict between the ground references
of the meter and the external interface. The
CS5460A and associate circuitry should be en­closed in a protective insulated case when used in
this configuration, to avoid risk of harmful electric
shock to humans/animals/etc.

Figure 7 shows how the same single-phase
two-wire system can be metered while achieving

16 DS487F5

CS5460A

VA+ VD+

0.1 µF100 µF

500



470 nF

500

N

R

1

R

2

10



14

VIN+

9

VIN-

IIN-

10

15

16

IIN+

PFMON

CPUCLK

XOUT

XIN

Optional

Clock

Source

Serial

Data

Interface

RESET

17
2
1

24

19

CS

7

SDI

23

SDO

6

SCLK

5

INT

20

EDIR

EOUT

0.1 µF

VREFIN

12

VREFOUT

11

VA- DGND

13 4

3

To Service

2.5 MHz to
20 MHz

0.1 µF

C

10 k



5k



L

R

Shunt

V+

*

* Refer to Input Protection

CS5460A

*

** Refer to Input Filtering

R

V-

*

R

I-

*

R

I+

*

C

I+

*

*

ISOLATION

120 VAC

Mech. Counter
Stepper Motor

or

22

21



+

NOTE: Current channel

input measures voltage
(just like voltage input).

C

V-

**

C

I-

**

C

**

Vdiff

C

**

Idiff

Figure 6. Typical Connection Diagram (One-Phase 2-Wire, Direct Connect to Power Line)

complete isolation from the power lines. This isola­tion is achieved using three transformers. One
transformer is a general-purpose voltage trans­former, used to supply the on-board DC power to
the CS5460A. A second transformer is a high-pre­cision, low-impedance voltage transformer (often
called a ‘potential transformer’) with very little
roll-off/phase delay, even at the higher harmonics.
A current transformer is then used to sense the line
current. A burden resistor placed across the sec­ondary of the current transformer creates the cur­rent-sense voltage signal, for the CS5460A’s
current channel inputs. Because the CS5460A is

not directly connected to the power mains, isola­tion is not required for the CS5460A’s digital inter­face.

Figure 8 shows the CS5460A configured to mea­sure power in a single-phase 3-wire system. In
many 3-wire residential power systems within the
United States, only the two Line terminals are
available (neutral is not available). Figure 9 shows
how the CS5460A can be configured to meter a
3-wire system when no neutral is available.

DS487F5 17