Cirrus Logic CS5333-KZ, CS5333 Datasheet

CS5333

24-Bit, 96 kHz Stereo A/D Converter

Features

l 24-bit conversion l Supports 96 kHz sample rates l 98 dB dynamic range at 3 V supply l -88 dBFS THD+N l 1.8 to 3.3 volt supply l 16-Pin TSSOP package l Low power consumption

– 11 mW at 1.8 V

l Internal high pass filter to remove DC offsets l Linear phase digital anti-alias filter

I I

VL RSTVA

Description

The CS5333 is a highly integr ated, 24-b it, 96 kHz audi o ADC providing stereo ana log-to-di gital conver ters usin g delta-sigma conversion techniques. This device includes line level inputs in a 16-pin TSSOP package.

The CS5333 is based on d elta- sigma mo dulati on all owing infinite adjustment of the sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency.

The CS5333 operates from a +1.8 V to +3.3 V supply . These features are ideal fo r set-top boxes, A/V receivers, DVD-karaoke players or any system which requires optimal performance in a minimum of space.

ORDERING INFORMATION

CS5333-KZ -10 to 70° C 16-pin TSSOP CDB5333 Evaluation Board

TST

LP Filter

GND VQ

AINL

S/H

AINR

S/H

Advance Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

DAC

Comparator

MCLK

Digital Decimation

Filter

Digital Decimation

Filter

FILT + REF_GND

HPF

DIV DIF

Serial Port

SDATA

LRCK

SCLK

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

DEC ‘00

DS520PP1

1. CHARACTERISTICS/SPECIFICATIONS .................................................................................4

ANALOG CHARACTERISTICS................................................................................................ 4

ANALOG CHARACTERISTICS................................................................................................ 5

POWER AND THERMAL CHARACTERISTICS . ....... ............................................. ..................6

DIGITAL CHARACTERISTICS................................................................................................. 7

ABSOLUTE MAXIMUM RATINGS ...........................................................................................7

RECOMMENDED OPERATING CONDITIONS.......................................................................7

SWITCHING CHARACTERISTICS . ...... ....... ............................................. ...............................8

2. TYPICAL CONNECTION DIAGRAM .................................................................................... 10

3. PIN DESCRIPTION ............................................................................................................... 11

4. APPLICATIONS ......................................................................................................................13

4.1 Grounding and Power Supply Decoupling .......................................................................13

4.2 Oversampling Modes ....................................................................................................... 13

4.3 Recommended Power-up Sequence ............................................................................... 13

4.4 Master/Slave Mode ..........................................................................................................13

5. PARAMETER DEFINITIONS ..................................................................................................17

6. REFERENCES ........................................................................................................................ 17

7. PACKAGE DIMENSIONS ....................................................................................................... 18

CS5333

Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Preliminary product inf o rmation describes products whi c h are i n production, but for whi ch f ul l char act er iza t i on da t a i s not yet available. Advance p rodu ct i nformation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warran t y , pa tent infringement, an d limitation of liability. No re s p onsibility is assumed b y Cirrus Logic, Inc. for the use of this informa tion, including use of this inf orma t i on as the basis for manu f acture or sale of a ny i tems, nor for infr ingements of paten t s or other rights o f thir d parti es . This document is the property of Cirrus Logic, Inc. a nd by furni shing th is i nformati on, Cir rus L ogic, In c. grant s no l icense, express or i mpli ed under any patent s, mask work righ ts, copyrights, trademarks, trad e secrets o r ot her i ntellect ual pro pert y right s of Cirrus L ogic, I nc. Ci rrus L ogic, In c., cop yright owner of the in forma tion co ntaine d herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is gi ven for simi lar inf ormat ion con tai ned on a ny Cirru s Logic we bsite or disk. T his consent does not extend to othe r copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com

2 DS520PP1

LIST OF FIGURES

Figure 1. SCLK to LRCK and SDATA, Slave Mode........................................................................ 9

Figure 2. SCLK to LRCK and SDATA, Master Mode...................................................................... 9

Figure 3. Typical Connection Diagram................ ...... ....... ...... ...... ....... ...... .................................... 10

Figure 4. Base-Rate Stopband Rejection...................................................................................... 14

Figure 5. Base-Rate Transition Band............................................................................................ 14

Figure 6. Base-Rate Transition Band (Detail) ............................................................................... 14

Figure 7. Base-Rate Passband Ripple.......................................................................................... 14

Figure 8. High-Rate Stopband Rejection ............................................ .......................................... 14

Figure 9. High-Rate Transition Band................... ............................................. .............................14

Figure 10. High-Rate Transition Band (Detail).............................................................................. 15

Figure 11. High-Rate Passband Ripple......................................................................................... 15

Figure 12. Line Input Test Circuit.................................................................................................. 15

Figure 13. CS5333 - Serial Audio Format 0.................................................................................. 16

Figure 14. CS5333 - Serial Audio Format 1.................................................................................. 16

LIST OF TABLES

Table 1. Common Clock Frequencies........................................................................................... 11

Table 2. Digital Interface Format - DIF.......................................................................................... 12

CS5333

DS520PP1 3

1. CHARACTERISTICS/SPECIFICATIONS

CS5333

ANALOG CHARACTERISTICS (T

GND = 0 V; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)

Parameter Symbol

= 25° C; GND = 0 V Logic "1" = VL = 1.8 V; Logic "0" =

Base-rate Mode High-rate Mode

UnitMin Typ Max Min Typ Max

Analog Input Characteristics for VA = 1.8 V

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 1)

-1 dB

-20 dB

-60 dB

THD+N

TBD TBD9188

-88

-68

-28

TBD

TBD TBD9491

-88

-68

-31

TBD

dB dB

dB dB dB

Analog Input Characteristics for VA = 3.0 V

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 1)

-1 dB

-20 dB

-60 dB

THD+N

TBD TBD9693

-88

-68

-33

TBD

TBD TBD9895

-85

-65

-35

TBD

dB dB

dB dB dB

Analog Input Characteristics for VA = 1.8 or 3.0 V

Interchannel Isolation 1 kHz - 90 - - 90 - dB Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Offset Error with High Pass Filter - - 0 - - 0 LSB Full Scale Input Voltage TBD VA÷3.6 TBD TBD VA÷3.6 TBD Vrms Voltage Common Mode VA÷2 VA÷2 V Gain Drift - 100 - - 1 00 - ppm/°C Input Resistance 10 - - 10 - - kΩ Input Capacitance - - 15 - - 15 pF

Notes: 1. Referenced to typical full-scale differential input voltage.

4 DS520PP1

CS5333

ANALOG CHARACTERISTICS (Continued)

Base-rate Mode High-rate Mode

Parameter Symbol

A/D Decimation Filter Characteristics (Note 2)

Passband (Note 3) 0 - 23.5 0 - 47.5 kHz Passband Ripple -0.08 - +0.17 -0.09 - 0 dB Stopband (Note 3) 27.5 - - 64.1 - - kHz Stopband Attenuation (Note 4) -60.3 - - -48.4 - - dB Group Delay (Fs = Output Sample Rate) (Note 5) t

Group Delay Variation vs. Frequency ∆t

- 10/Fs - - 2.7/Fs - s

- - 0.03 - - 0.007 µs

High Pass Filter Characteristics

Frequency Response -3 dB (Note 3)

-0.1 dB Phase Deviation @ 20 Hz (Note 3) - 10 - - 10 - Degr ee Passband Ripple (Note 2) - - 0.17 - - 0.09 dB

Notes: 2. Filter response is guaranteed by design.

3. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the

0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs.

4. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection

of input signals which are multiples of the sampling frequency (n x 6.144 MHz ±21.8 kHz where n = 0,1,2,3...).

5. Group delay for Fs = 48 kHz, t

= 15/48 kHz = 312µs.

3.7

24.2

3.7

24.2

UnitMin Typ Max Min Typ Max

DS520PP1 5

POWER AND THERMAL CHARACTERISTICS

Base-rate Mode High-Rate Mode

Parameters Symbol Min Typ Max Min Typ Max Units

Power Supplies

Power Supply Current- VA=1.8 V Normal Operation VL=1.8 V

Power Supply Current- VA=1.8 V Power Down Mode (Note 7) VL=1.8 V

Power Supply Current- VA=3.0 V Normal Operation VL=3.0 V

Power Supply Current- VA=3.0 V Power Down Mode VL=3.0 V

Total Power Dissipation- All Supplies=1.8 V Normal Operation All Supplies=3.0 V

Package Thermal Resistance θ Power Supply Rejection Ratio (1 kHz)

(Note 6) (60 Hz)

Notes: 6. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 3.

7. Power Down Mode is defined as reset active with MCLK being applied. To lower power consumption further, remove MCLK.

D_IO

PSRR -

6.0

150

100

0 9

260 250

11 28

TBD TBD

7.6

300

250

11.5 520

500

14.536TBD

-75- -75-°C/Watt 60

60 40

CS5333

TBDmWmW

µA µA

µA

µA µA

µA

dB dB

6 DS520PP1

CS5333

DIGITAL CHARACTERISTICS (T

= 25° C; VL = 1.7 V - 3.6 V; GND = 0 V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage V Low-Level Output Voltage V

Leakage Current I

OH OL

0.7•VL - - V

- - 0.3•VL V

0.7•VL - - V

- - 0.3•VL V

--±10µA

Input Capacitance - 8 - pF

ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supplies: Positive Analog

Digital I/O Input Current, Any Pin Except Supplies I Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T

VA VL

IND

stg

-0.3

-±10mA

4.0

V V

-0.3 VL+0.4 V

-55 125 °C

-65 150 °C

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

Ambient Temperature T DC Power Supplies: Positive Analog

Digital I/O

VA VL

-10 - 70 °C

1.7

3.6

V V

DS520PP1 7

CS5333

SWITCHING CHARACTERISTICS (T

Logic 1 = VL, C

= 20 pF)

= -10 to 70° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,

Parameters Symbol Min Typ Max Units

Input Sample Rate Base Rate Mode

High Rate Mode

Fs Fs

100

kHz

kHz MCLK Pulse Width High MCLK/LRCK = 1024 8 - - ns MCLK Pulse Width Low MCLK/LRCK = 1024 8 - - ns MCLK Pulse Width High MCLK/LRCK = 768 10 - - ns MCLK Pulse Width Low MCLK/LRCK = 768 10 - - ns MCLK Pulse Width High MCLK/LRCK = 512 15 - - ns MCLK Pulse Width Low MCLK/LRCK = 512 15 - - ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - - ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - - ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - - ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - - ns

Master Mode

SCLK Falling to LRCK Edge t SCLK Falling to SDATA Valid t

slrd sdo

-20 - 20 ns 0 - 20 ns

SCLK Duty Cycle 40 50 60 %

Slave Mode

LRCK Duty Cycle - 50 - % SCLK Pulse Width Low t SCLK Pulse Width High t SCLK Period Base Rate Mode

High Rate Mode

sclkl

sclkh

sclkw

20 - - ns 20 - - ns

---------------------128()Fs

------------------

64()Fs

ns ns

SCLK Falling to LRCK Edge t SCLK Falling to SDATA Valid Base Rate Mode

High Rate Mode

t t

slrd dss

dss

-20 - 20 ns

(512)Fs

(256)Fs

ns ns

8 DS520PP1

CS5333

SCLK

LRCK

SDATA

SCLK

sclkh

sclkl

slrd

dss

MSB

Figure 1. SCLK to LRCK and SDATA, Slave Mode

sclkw

slrd

LRCK

sdo

SDATA

MSB MSB-1

Figure 2. SCLK to LRCK and SDATA, Master Mode

DS520PP1 9

2. TYPICAL CONNECTION DIAGRAM

1.8 to 3.3 V Supply

1.8 to 3.3 V

Supply

1.0 µF

150

Ω

0.47 µ F

* **

0.1 µF

0.01 µF *

0.01 µF

AINL

AINR

CS5333

FILT+

REF_GND

RST

DIF

DIV

1.0 µF

9 8

CS5333

1.0 µF

Mode

Configuration

* All capacitors located on the analog input lines should be of the type COG or equivalent.

**Optional if analog input circuit is biased within

±5% of CS5333 nominal bias voltage

MCLK LRCK

SCLK

SDATA

GND6TST

Figure 3. Typical Connection Diagram

2 7 3 4

Digital

Audio

Source

Ω

47k

Connect to:

• VL for Master Mode

• GND for Slave Mode

10 DS520PP1

3. PIN DESCRIPTION

CS5333

Interface Power VL RST Reset

Master Clock MCLK VQ Quiescent Voltage

Serial Clock SCLK AIN L Left Channel Analog Input

Serial Data Output SDATA AIN R Right Channel Analog Input

Analog Power VA REF_GND Reference Ground

Ground G ND FILT+ Positive Voltage Reference

Left Right Clock LRCK TST Test Input

MCLK Divide DIV DIF Digital Interface Format

Interface Power 1 VL ( Master Clock 2 MCLK (

Serial Clock 3 SCLK (

Serial Audio Data Out (M/S select)

Analog Power 5 VA ( Ground 6 GND (

4 SDATA (

Input

) - Digital interface power supply. Typically 1.8 to 3.3 VDC.

Input

) - The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Base Rate Mode (BRM) and 128x, 192x, 256x, 384x the input sample rate in High Rate Mode (HRM). Table 1 illustrates several standard audio sample rates and the required master clock frequencies.

Input/Output

The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF pin.

Output

First: two’s complem ent M SB-fir st s eria l da t a is outp ut on this pi n. The dat a is c lo cked ou t of SDOUT via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF pin. Second: Master/Slave mo de sele cti on is determined, at startup, by a 47kOhm pullup/pulldown on this line. A pullup to VL selects Master mode and a pulldown to GND selects Slave mode.

Input

) - Analog power supply. Typically 1.8 to 3.3 VDC.

Input

) - Ground Reference.

1 2

2 3

3 4

4 5

5 6

6 7

7 8

) - Clocks the individual bits of the serial data out of the SDOUT pin.

) - This pin serves two functions.

16 15

15 14

14 13

13 12

12 11

11 10

MCLK (MHz)

Sample

Rate

(kHz)

32 4.0960 6.1440 8.1920 12.2880 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 5.6448 8.4672 11.2896 1 6.9344 11.2896 16.9344 22.5792 32.7680 45.1584 48 6.1440 9.2160 12.2880 18.4320 12.2880 18.4320 24.5760 36.8640 49.1520 64 8.1920 12.2880 16.3840 24.5760 - - - - -

88.2 11.2896 16.9344 22.5792 33.8688 - - - - 96 12.2880 18.4320 24.5760 36.8640 - - - - -

128x 192x 256x* 384x* 256x 384x 512x 768x* 1024x*

HRM BRM

* DIV= Hi

Table 1. Common Clock Frequencies

DS520PP1 11

CS5333

Left/Right Clock 7 LRCK (

MCLK Divide Enable

Digital Interface Format

8 DIV (

9 DIF (

Input/Output

output on the serial au dio d ata line SDOUT. The frequency of th e L eft/Right clock must be at the input sample rate. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF pin.

Input

) - This pin serves different functions in Master and Slave modes. In Master mode: When high, the chip will enter High Rate Mode; When this pin is low, the chip will enter Base Rate Mode. In Slave mode: When high, MCLK is divided internally by 2; When low, MCLK is not changed.

Input

) - The required relation ship between the Left/Right cl ock, seria l clock and seria l

DIF DESCRIPTION

0 1 Left Justified, up to 24-bit data

Table 2. Digital Interface Format - DIF

Test Input 10 TST ( Positive V ol tage

Reference

Reference Ground 12 REF_GND (

Analog Inputs 13,14 AINR, AINL (

Quiescent Voltage 15 VQ (

Reset 16 RST (

11 FILT+ (

Input

) - Must be connected directly to ground.

Output)

required from FILT+ to ground, as shown in Figure 3. The recommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intende d to supply external current. FILT+ has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance.

nected to ground.

istics specification table.

Output

) - Filter connection for internal A/D converter quiescent reference voltage. A capacitor must be connected from VQ to ground. VQ is not intended to supply external current. VQ has a typi cal sourc e impeda nce of 25 0 kΩ and any current drawn from this pin will alter device performance.

Input

) - When low the device enters a low power mode and the part is in reset.

When high, the part returns to normal operation within 1024 LRCK cycles.

) - The Left/Right clock determines which channel is currently being

data is defined by the Digital Interface Format.

S, up to 24-bit data

- Positive reference for internal sampling circuits. An external capacitor is

Input

) - Ground reference for the internal sampling circuits. Must be con-

Input

) - The full scale analog input level is specified in the Analog Character-

12 DS520PP1

CS5333

4. APPLICATIONS

4.1 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS5333 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 3 show the recommended power arrangement with VA and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible.

4.2 Oversampling Modes

The CS5333 operates in one of two oversampling modes. Base Rate Mode supports input sample rates up to 50 kHz while High Rate Mode supports input sample rates up to 100 kHz. See Table 1 for more details.

4.3 Recommended Power-up Sequence

the power-up sequence. This power-up sequence takes approximately 1024 LRCK cycles to complete.

4.4 Master/Slave Mode

In Master, Base Rate Mode (Pull-up on SDATA, DIV=0), the CS5333 requires a 256x MCLK and provide a 64x SCLK. In Master, High Rate Mode (Pull-up on SDATA, DIV=1), the CS5333 requires a 128x MCLK and provide a 64x SCLK. The various clocking ratios required in Slave Mode (Pulldown on SDATA) are listed under the description of MCLK, on page 11.

1) Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, VQ will remain low.

2) Bring RST high. The device will remain in a

low power state with VQ low and will initiate

DS520PP1 13

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency (normalized to Fs)

Amplitude dB

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0 0.1 0 .2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (normalized to Fs)

Amplitude dB

CS5333

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100 0 0.1 0.2 0.3 0.4 0 .5 0.6 0.7 0.8 0.9 1

Frequency (normalized to Fs)

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

Frequency (normalized to Fs)

Figure 4. Base-Rate Stopband Rejection Figure 5. Base-Rate Transition Band

0.3

0.25

0.2

0.15

0.1

0.05 0

-0.05

-0.1

Amplitude dB

-0.15

-0.2

-0.25

-0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0. 35 0.4 0.45 0.5

Frequency (normalized to Fs)

Figure 6. Base-Rate Transition Band (Detail) Figure 7. Base-Rate Passband Ripple

14 DS520PP1

Figure 8. High-Rate Stopband Rejection Figure 9. High-Rate Transition Band

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100

0.4 0.43 0.4 6 0 .49 0 .52 0.55 0 .58 0 .61 0. 64 0.67

Frequency (normalized to Fs)

CS5333

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency (normalized to Fs)

Amplitude dB

0.3

0.25

0.2

0.15

0.1

0.05 0

-0.05

-0.1

Amplitude dB

-0.15

-0.2

-0.25

-0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency (normalized to Fs )

Figure 10. H i gh-Rate Transition Band (Detail) Figure 11. H i gh-Rate Passband Ripple

150

DS520PP1 15

Ω

0.47 µF

0.01 µF

Figure 12. Line Input Test Circuit

AINx

GND

CS5333

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

I2S, up to 24-Bit Data. Data Valid on Rising Edge of SCLK

Figure 13. CS5333 - Serial Audio Format 0

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

Left Justified, up to 24-Bit Data. Data Valid on Rising Edge of SCLK.

LSB

MSB

-1 -2 -3 -4

MSB

-1 -2 -3 -4

Right Channel

+3 +2 +1

+5 +4

Right Channel

+3 +2 +1

+5 +4

LSB

Figure 14. CS5333 - Serial Audio Format 1

16 DS520PP1

5. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

CS5333

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

6. REFERENCES

1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2. CDB5333 Evaluation Board Datasheet.

DS520PP1 17

7. PACKAGE DIMENSIONS

16L TSSOP (4.4 mm BODY) PACKAGE DRAWING

CS5333

TOP VIEW

SIDE VIEW

SEATING

PLANE

INCHES MILLIMETERS

END VIEW

NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10 A1 0.002 0.004 0.006 0.05 -- 0.15 A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.193 0.1969 0.201 4.90 5.00 5.10 1

E 0.248 0.2519 0.256 6.30 6.40 6.50 E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.065 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

∝

0° 4° 8° 0° 4° 8°

∝

JEDEC #: MO-153

Controlling Dimension is Millimeters

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips

18 DS520PP1

• Notes •

Cirrus Logic CS5333-KZ, CS5333 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Description

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

ANALOG CHARACTERISTICS (T

DIGITAL CHARACTERISTICS (T

ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.)

RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.)

SWITCHING CHARACTERISTICS (T

Figure 1. SCLK to LRCK and SDATA, Slave Mode

Figure 2. SCLK to LRCK and SDATA, Master Mode

2. TYPICAL CONNECTION DIAGRAM

Figure 3. Typical Connection Diagram

3. PIN DESCRIPTION

Table 1. Common Clock Frequencies

Table 2. Digital Interface Format - DIF

4. APPLICATIONS

4.1 Grounding and Power Supply Decoupling

4.2 Oversampling Modes

4.3 Recommended Power-up Sequence

4.4 Master/Slave Mode

Figure 4. Base-Rate Stopband Rejection Figure 5. Base-Rate Transition Band

Figure 6. Base-Rate Transition Band (Detail) Figure 7. Base-Rate Passband Ripple

Figure 8. High-Rate Stopband Rejection Figure 9. High-Rate Transition Band

Figure 10. H i gh-Rate Transition Band (Detail) Figure 11. H i gh-Rate Passband Ripple

Figure 12. Line Input Test Circuit

Figure 13. CS5333 - Serial Audio Format 0

Figure 14. CS5333 - Serial Audio Format 1

5. PARAMETER DEFINITIONS

6. REFERENCES

7. PACKAGE DIMENSIONS