Cirrus Logic CS22220 Datasheet
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CS22220 Data Sheet
Wireless PCMCIA Controller
1 Description
The Cirrus Logic CS22220 Wireless Network Controller enables high performance, 11 Megabits per
second digital wireless data connectivity for PCMCIA, mobile, embedded systems and other cost
sensitive applications.
The CS22220 is a highly integrated single-chip PCMCIA solution for wireless networks supporting
video, audio, voice, and data traffic. The programmable controller executes Cirrus Logic’s
Whitecap™2 networking protocol that provides Wi-Fi™ (802.11b) compliance as well as multimedia
and quality of service (QoS) support. The device includes several high performance components
including an ARM7TDMI RISC processor core, a Forward Error Correction (FEC) codec and a
wireless radio MAC supporting up to11 Mbps throughput. The CS22220 utilizes state of the art
0.18um CMOS process and is housed in a 208 FPBGA compact (15mm x 15mm) package, which
has low-lead inductance suitable for highly integrated radio applications. The core is powered at 1.8
V with 3.3V (5.0V tolerant) I/O to reduce overall power consumption. In addition, the CS22220
supports low power management for the host and radio interfaces.
The CS22220 is designed to be an integral part of a PC card (PCMCIA 2.1/JEIDA 4.2). The
PCMCIA host interface also supports both little endian and big endian protocol for easy interfacing
to popular microprocessors in embedded system applications.
PCMCIA Host or Embedded CPU
Networking Data
802.11b compatible
2.4 GHz
Digital Radio
PHY Transceiver
2.4 GHz Direct Sequence
S
read Spectru
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11 Mbps
Wireless
Baseband I/F
Figure 1. Example System Block Diagram
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CS22220
Wireless
PCMCIA
Controller
System Memory
SDRAM (Up to 4MB)
SRAM (Up to 256KB)
Boot ROM/Flash
(Upto1MB)
2 Features
Embedded ARM Core and System Support Logic
• High performance ARM7TDMI RISC processor core up to 77MHz
• 4KB integrated, one-way set associative, unified, write through cache
• Individual interrupt for each functional block
• Two 23-bit programmable (periodic or one-shot) general purpose timers
• 8 Dword (32-bits) memory write and read buffers for high system performance
• Abort cycle detection and reporting for debugging
• ARM performance monitoring function for system fine-tuning
• Programmable performance improvement logic based on system configuration
Enhanced Memory Controller Unit
• Programmable memory controller unit supporting SDRAM /async SRAM/Boot ROM/Flash
interface
• 16-bit data bus with 12-bit address supporting up to 4MB up to 103 MHz (100/133MHz SDRAM)
• 8-bit data bus with addressing support up to 1MB of boot ROM/Flash.
• Programmable SDRAM timing and size parameters such as CAS latencies and number of
banks, columns, and rows
• Flexible independent DMA engines for PCMCIA and digital radio functional units
FEC codec
• High performance Reed-Solomon coding for error correction (255:239 block coding)
• Reduces error probability of a typical 10e-3 error rate environment to 10e-9
• Programmable rate FEC engine to optimize channel efficiency
• Low latency, fully pipelined hardware encoding and decoding. Supports byte-wise single cycle
throughput up to 77MHz, with a sustain rate of 77MBps.
• Double buffering (63 Dword read/write buffer) to enhance system performance
Digital Radio MAC Interface
• Glue-less interface to 802.11b baseband transceivers
• Up to 11Mbps data rates
• 32 Dword transmit/receive FIFO
• Supports clear channel assessment (CCA)
Power Management
• Host (PCMCIA) ACPI compliant
• Programmable sleep timer for ARM core and system low power management
• Independent power management control for individual functional units
• Supports variable rate radio transmit, receive, and standby radio power modes
Clock and PLL Interface
• Single 44MHz crystal oscillator reference clock
• Internal PLL to generate internal and on board clocks
PCMCIA Interface
• 16 bit PCMCIA I/O target device supporting memory map or program I/O using 11 address bits
• Independent DMA controller to transfer data between PCMCIA and main memory
• Fully compliant with PCMCIA 2.1/JEIDA 4.2 standard
• Supports big endian and little endian (default) data formats
• Supports custom mode for embedded applications where the interface becomes a generic
memory address/data interface
Chip Processing and Packaging
• 208 FPBGA package and 0.18um state of the art CMOS process
• 1.8 V core for low power consumption. 3.3V I/O - 5V tolerant I/O
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IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet
available. "Advance" product information describes products that are in development and subject to development changes.
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and
reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind
(express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of
sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation
of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the
basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the
property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask
work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the
information contained herein and gives consent for copies to be made of the information only for use within your organization
with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as
copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or
technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be
exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the
Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade
Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH,
PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS").
CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFESUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN
SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product
names in this document may be trademarks or service marks of their respective owners.
Use of this product in any manner that complies with the MPEG-2 video standard as defined in ISO
documents IS 13818-1 (including annexes C, D, F, J, and K), IS 13818-2 (including annexes A, B,
C, and D, but excluding scalable extensions), and IS 13818-4 (only as it is needed to clarify IS
13818-2) is expressly prohibited without a license under applicable patents in the MPEG-2 patent
portfolio, which license is available from MPEG LA, L.L.C. 250 Steele Street, Suite 300, Denver,
Colorado 80296.
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3 Functional Description
Figure 2. Block Diagram of Major Functional Units
System Memory
Memory/Boot ROM
Controller
Arbiter
DMA
PCMCIA
PCMCIA
Controller
w/DMA Ctrl
Sleep
Timer
FEC codec
Read/Write Buffer
ARM 7TDMI
Interrupt
controller
System Control Bus
Timer
(2)
4KB
Cache
Clock/PLL
Crystal or
Oscillator
DMA
Radio MAC
w/ DMA Ctrl
JTAG/Test Interface
Digital Radio
Interface
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3.1 Embedded ARM Core and System Support Logic
The processing elements of the CS22220 include the ARM7TDMI core and its associated
system control logic. The ARM processor and system controller consists of a memory
management unit, 4-KB write through cache controller, 20 IRQ and 4 FIRQ interrupt
controller, and 2 general purpose timers. The ARM processor and integrated system
support logic provide the necessary execution engine to support a real time multi-tasking
operating system, the network protocol stack, and firmware services.
Memory Management Unit
ARM instructions and data are fetched from system memory a cache-line (4/8 – Dwords
/Programmable) at a time when caching is turned on. During a cache line fill, critical word
data, i.e., the access that caused the miss, is forwarded to the ARM and also written into
the data RAM cache. The non-critical words in the line fetched following the critical word
are then written to the cache on a Dword basis, as they become available.
Memory writes are posted to dual 4-Dwords (32-bit) memory write posting buffers. Write
posts use the sequential addressing feature on the memory bus. With dual buffering an out
of sequence write will post to one write buffer while the other buffer is flushed to memory.
There is one 8Dword Read Buffer in the MEM block. The buffer is used for both cacheable
and non-cacheable memory space.
Interrupt Controller
The interrupt controller provides two interrupt channels to the ARM processor. One
interrupt channel is presented to the ARM on its nFIQ, and the other channel is presented
on its nIRQ pin. These are referred to as the FIQ channel and the IRQ channel. Both
channels operate in identical but independent fashion. The FIQ channel has a higher
priority on the ARM processor than the IRQ channel.
The interrupt controller includes a CONTROL register for each logical interrupt in the ARM
Complex. The CONTROL register serves the following main purposes:
• Provides the mapping between the EXT_INT inputs (physical interrupts) and the logical
interrupt
• Selects the particular type of signaling expected on the EXT_INT inputs: level, edge,
active level high/low etc.
• Enable or disable a logical interrupt
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3.2 Digital Radio Interface
The CS22220 digital radio MAC I/F supports multiple radio baseband and RF interfaces.
The baseband registers can be programmed during the configuration time using the control
port interface. The MAC also provides the capability of programming the signal, service and
length on per packet basis without ARM intervention. This significantly improves the
performance of the system.
There are three primary digital interface ports for the CS22220 that are used for
configuration and during normal operation.
These ports are:
• The Control Port, which is used to configure, set power consumption modes, write
and/or read the status of the radio base band registers.
• The TX Port, which is used to output the data that needs to be transmitted from the
network processor.
• The RX Port, which is used to input the received demodulated data to the network
processor
3.3 FEC Codec
The FEC codec performs Reed-Solomon coding to protect the data before it is transmitted
to a noisy channel. It is a similar code as employed by the digital broadcast industry, such
as ITU-T J.83 for DVB. The RS(255, 8) code implemented by the CS22220 can reduce
error probability to 1/10e-9 in a typical 1/10e-3 error rate environment. The
encoder/decoder can be programmed to vary the coding block length (N) and correctable
error (t) to optimize the tradeoff between channel utilization and data protection. The range
of N iscurrentlysettobefrom20to255,andthet is 8. The symbol size is fixed at 8 bits.
Coding parameters can be set real time, allowing maximum flexibility for the system to
adjust the FEC setting, such as block size, in order to optimize channel efficiency. The
encoder also has a very low latency of two cycles. Both the encoder and decoder are fully
pipelined in structure to achieve single cycle throughput. The FEC can be disabled in
firmware.
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3.4 Programmable Memory Controller
The CS22220 incorporates a general-purpose memory controller. The memory controller
supports both SDRAM/async SRAM memory interface and a FLASH memory interface.
In the RAM configuration, the system memory interface supports up to 4-Mbyte of 16-bit
SDRAM running at frequency up to 103 MHz (using 133MHz SDRAM) single-state access
cycles or 256KB of 16 bit async SRAM. The memory controller provides programming of
SDRAM parameters such as CAS latency, refresh rate and etc; these registers are located
in miscellaneous configuration registers. The CS22220 memory controller supports the
power saving feature of the SDRAM by toggling the clock enable (CKE) signal. When there
are no pending memory requests from any internal requester, the CS22220 will keep CKE
low to cause the SDRAM to stay in power down mode. Once a memory request is active,
the CS22220 will assert CKE high to cause the SDRAM to come out of power down mode.
Typically, this can reduce memory power consumption by up to 50%.
In ROM configuration, firmware for CS22220 is stored in non-volatile memory and is
accessed through the boot ROM interface. The maximum addressable ROM space
supported is 1MB. ROM read/write and output enable are shared with RAM control pins.
3.5 PCMCIA Interface
The PC-Card interface implemented in Cirrus Logic CS22220 is fully compliant with
PCMCIA 2.1/JEIDA 4.2. The interface supports 16 data bits PCMCIA program I/O and
memory mapped accesses using 11 address bits. PCMCIA interface allows laptop users to
connect to home network to access data and multimedia streams with ease. The interface
provides both memory and I/O access.
The PCMCIA interface incorporates an independent DMA controller to transfer data to/from
the main memory. The ARM has the flexibility in controlling how often it is interrupted and
simplifies the packet transmit/receive protocol. The DMA controller is programmed during
power up.
The CS22220 PCcard interface incorporates a custom mode, which can be used for
embedded applications, by bypassing the standard PC card Pnp configuration
requirements. This interface thus becomes a generic asynchronous 16 bit data interface.
This mode is useful when interfacing the CS22220 wireless network controller directly to an
embedded micro-controller capable of supporting a 16 bit data bus.
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4 Pinout and Signal Descriptions
N
T
I
K
K
T
Figure 3. CS22220 Logical Pin Groupings
System
Memory
Interface
JTAG
Interface
Clock Interface
PLL Power
Interface
SMCLK
nSMCS[1:0]
nSMRAS
nSMCAS
nSMWE
SMDQM[1:0]
SMCKE
SMA[11:0]
SMD[15:0]
nBRCE
TDO
TD
TC
TMS
nTRST
XTRACL
XTALCLKI
XTALOU
PLLAGND
PLLAVCC
PLLDVCC
PLLDGND
PLLPLUS
NTES
nPERR, nSERR
CS22220
Controller
NPCE1
NPCE2
NPCOE
nPCWE
nPCREG
nPCIORD
PCIOWR
nPCINPACK
PCA[10:0]
PCD[15:0]
nPCIRQ
nPCSTSCHG
nPCWAIT
NIOIS16
EXT_RESET
TXCLK
TXPE
TXD
TXRDY
CCA
BBRNW
nRESETB
BBAS
nBBCS
TXPAPE
TXPEBB
RXPEBB
BBSCLK
BBSDX
SYNTHLE
nRPD
RXCLK
MDRDY
RXD
PCMCIA
Interface
Digital Radio
Interface
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This section provides detailed information on the CS22220 signals. The signal descriptions are
useful for hardware designers who are interfacing the CS22220 with other devices.
System Memory Interface
The system memory interface supports standard SDRAM interface, async SRAM and FLASH.
There are a total of 38 signals in this interface.
SMCLK Output
System mem clock for SDRAM. Currently the interface supports 100
MHz for a maximum bandwidth of 200Mbytes/sec.
nSMCS0 Output
Chip select bit 0. This signal is used to select or deselect the SDRAM for
command entry. When SMNCS is low it qualifies the sampling of
nSMRAS, nSMCAS and nSMWE. Also, used as testmode(2) when
NTEST pin is '0'.
nSMCS1 Output
Chip select bit 1.
nBRCE Output
Chip select for ROM access. This signal is used to select or deselect the
boot ROM memory.
nSMRAS Output
Row address select. Used in combination with nSMCAS, nSMWE and
nSMCS to specify which SDRAM page to open for access. Also used
during reset to latch in the strap value for clk_bypass; if set to a '1' implies
bypassing clock module; whatever clk is applied on the input clock is
used for memclk and ctlclk. Also shared as the ROMOE signal.
nSMCAS Output
Column address select. Used in combination with nSMRAS, nSMWE and
nSMCS to specify which piece of data to access in selected page. Also
used during reset to latch in the strap value for same_freq; if set to a '1'
implies internal mem_clk and arm_clk are running at the same frequency
and 180 degrees out of phase.
nSMWE Output
Write enable. Used in combination with nSMRAS, nSMCAS, and
nSMWE to specify whether the current cycle is a read or a write cycle.
Also used during reset to latch in the strap value for tst_bypass; if set to a
'1' implies PLL bypass. Also shared as the ROMWE to do flash
programming.
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SMDQM[1:0] Output
Data mask bit 1:0. These signals function as byte enable lines masking
unwanted bytes on memory writes. Also, used as testmode(1:0) when
NTEST pin is '0'.
SMCKE
Output
Clock enable. SMCKE is used to enable and disable clocking of internal
RAM logic.
SMA0 Output
Address bit0. The address bus specifies either the row address or
column address. Also, this is shared as boot-ROM address bit0. Also
used during reset to latch in the strap value for pccsel, if set to a '1'
implies pccard mode
SMA1 Output
Address bit1. Also, this is shared as boot-ROM address bit1. This pin
should be pull-down.
SMA2 Output
Address bit2. Also, this is shared as boot-ROM address bit2. This pin
should be pull-down.
SMA3 Output
Address bit3. Also shared as boot-ROM address bit3. This pin should be
pull-down.
SMA4 Output
Address bit4. Also shared as boot-ROM address bit4. Also used during
reset to latch in the strap value for romcfg; if set to a '1' implies pccard
configuration data should be downloaded from ROM.
SMA5 Output
Address bit5. Also shared as boot-ROM address bit5. Also used during
reset to latch in the strap value for test_rst_enb; if set to a '0' implies
normal operation mode.
SMA6 Output
Address bit6. Also shared as boot-ROM address bit6. Also used during
reset to latch in the strap value for freq_sel(0). Freq_sel(2:0) is used to
select the multiplication factor for the internal PLL (000=1x, and 111=8x).
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SMA7 Output
Address bit7. Also shared as boot-ROM address bit7. Also used during
reset to latch in the strap value for freq_sel(1). Freq_sel(2:0) is used to
select the multiplication factor for the internal PLL (000=1x, and 111=8x).
SMA8 Output
Address bit8. Also shared as boot-ROM address bit8. Also used during
reset to latch in the strap value for freq_sel(2). Freq_sel(2:0) is used to
select the multiplication factor for the internal PLL (000=1x, and 111=8x).
SMA9 Output
Address bit9. Also shared as boot-ROM address bit9. Also used during
reset to latch in the strap value for sdram_delay(0). Sdram_delay(2:0) is
used to select the delay factor for the internal memory clock (000=0ns,
and 111=1.75ns with each .25ns increments).
SMA10 Output
Address bit10. Also shared as boot-ROM address bit10. Also used during
reset to latch in the strap value for sdram_delay(1). Sdram_delay(2:0) is
used to select the delay factor for the internal memory clock (000=0ns,
and 111=1.75ns with each .25ns increments).
SMA11 Output
Address bit11. Also shared as boot-ROM address bit11. Also used during
reset to latch in the strap value for sdram_delay(2). Sdram_delay(2:0) is
used to select the delay factor for the internal memory clock (000=0ns,
and 111=1.75ns with each .25ns increments).
SMD[7:0] Bi-directional
Data bus. The data bus contains the data to be written to memory on a
writecycleandthereadreturndataonareadcycle.
SMD[15:8] Bi-directional
Shared data bus. The data bus contains the data to be written to RAM
memory on a write cycle and the read return data on a read cycle. Data
bit [15:8] is also shared as boot ROM address bit [19:12].
Digital Radio Interface
All radio input buffers are Schmitt triggered input buffers. There are total of 26 signals in this
interface.
TXCLK Input
Transmit clock is a clock input from the radio baseband processor. This
signal is used to clock out the transmit data on the rising edge of TXCLK.
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