Cirrus Logic CS22210 Datasheet

CS22210 Data Sheet

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m

Wireless PCI/USB Controller

1 Description

The Cirrus Logic CS22210 Wireless Network Controller enables high speed, 11 Mbps digital wireless
data connectivity for wireless data connectivity for PCI, mobile, embedded systems and other cost
sensitive applications.

The CS22210 is a highly integrated single-chip PCI / USB solution for wireless networks supporting video,
audio, voice, and data traffic. The programmable controller executes Cirrus Logic’s Whitecap™2
networking protocol that provides Wi-Fi™ (802.11b) compliance as well as multimedia and quality of
service (QoS) support. The device includes several high performance components including an
ARM7TDMI RISC processor core, a Forward Error Correction (FEC) codec and a wireless Radio MAC
supporting up to11 Mbps throughput. The CS22210 is designed to support both a standard PCI 2.1 or
PCI 2.2 compliant interface or USB 1.1 compliant device interface making it an ideal choice for cost
effective standalone and embedded high-speed wireless networking products.

The CS22210 utilizes state-of-the-art 0.18um CMOS process and is housed in a 208 MQFP package
designed to provide integrated low cost IEEE 802.11 standard compliant system solutions. The core is
powered at 1.8 V to reduce overall power consumption. In addition, the CS22210 supports various power
management modes for host, MAC, baseband, and radio interfaces.

Figure 1. Example System Block Diagram

PCIorUSBHost

Networking Data

802.11b compatible

2.4 GHz

Digital Radio

PHY Transceiver

2.4 GHz Direct Sequence
S

read Spectru

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11 Mbps
Wireless

Baseband I/F

CS22210

Wireless

Network

Controller

www.cirrus.com

System Memory
SDRAM (Up to 4MB)
SRAM (Up to 256KB)

Boot ROM/Flash

(Upto1MB)

2 Features

Embedded ARM Core and System Support Logic

• High performance ARM7TDMI RISC processor core at 77MHz

• 4KB integrated, one-way set associative, unified, write through cache

• Individual interrupt for each functional block

• Two 23-bit programmable (periodic or one-shot) general purpose timers

• 8 Dword (32-bits) memory write and read buffers for high system performance

• Abort cycle detection and reporting for debugging

• ARM performance monitoring function for system fine-tuning

• Programmable performance improvement logic based on system configuration

• Flexible independent DMA engines for PCI, USB and digital radio functional units

Enhanced Memory Controller Unit

• Programmable memory controller unit supporting SDRAM /async SRAM/boot ROM interface

• 16-bit data bus with 12-bit address supporting up to 4MB at up to 103MHz SDRAM

• 8-bit data bus with addressing support up to 1MB of boot ROM/Flash

• Programmable SDRAM timing and size parameters such as CAS latencies and number of banks

columns and rows

FEC codec

• High performance Reed-Solomon coding for error correction (255:239 block coding)

• Reduces symbol error probability of a typical 10e-3 error rate environment to 10e-9

• Programmable rate FEC engine to optimize channel efficiency

• Low latency, fully pipelined hardware encoding and decoding. Support byte wise single cycle throughput

up to 77MHz, with a sustain rate of 77MBps.

• Double buffering (64 Dword read/write buffer) to enhance system performance

• On the fly configuration of encoder and decoder

Digital Wireless Radio MAC

• Standard interface to 802.11b radio baseband transceiver

• 11Mbps data rate

• 32 Dword transmit/receive FIFO

• Supports clear channel assessment (CCA)

Power Management

• Host (PCI or USB) ACPI compliant

• Remote USB host wakeup

• Supports variable rate radio transmit, receive and standby radio power modes through two DACs

Clock and PLL Interface

• Single 44MHz crystal oscillator reference clock for PCI version; 48MHz reference clock required in USB
option

• Internal PLL to generate internal and on board clocks

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PCI Controller Interface

• 33MHz 5V/3.3V PCI 2.1 and PCI 2.2 compliant master/target 32-bit data interface

• ARM communication with PCI controller through simple mailbox scheme

• Generic PCI controller programming interface

• Flexible configuration programming via EEPROM

USB Controller Interface

• 12 Mbps USB 1.1 compliant device

• Supports 1 to 16 endpoints; endpoints can be bulk, isochronous or interrupt

• Variable endpoint buffer depths providing maximum flexibility for endpoint configurations

• Flexible configuration programming via EEPROM or firmware download

• Remote host wakeup

Chip Processing and Packaging

• 208 MQFP package and 0.18 um state of the art CMOS process

• 1.8 V core for low power consumption; 3.3V I/O and 5V tolerant

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available.
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and
its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is
subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to
obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this
information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other
rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or
implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the
copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your
organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as
copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or
technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken
out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of
the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the
PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL
INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT
DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT
THE CUSTOMER'S RISK.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this
document may be trademarks or service marks of their respective owners.

Use of this product in any manner that complies with the MPEG-2 video standard as defined in ISO
documents IS 13818-1 (including annexes C, D, F, J, and K), IS 13818-2 (including annexes A, B, C, and D,
but excluding scalable extensions), and IS 13818-4 (only as it is needed to clarify IS 13818-2) is expressly
prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is
available from MPEG LA, L.L.C. 250 Steele Street, Suite 300, Denver, Colorado 80296.

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3 Functional Description

y

y

Figure 2. Block Diagram of Major Functional Units

PCI
Interface

stem Memor

System Memory

S

Memory/Boot ROM

Controller

Arbiter

USB or PCI

Host Interface

12MHz

or

33 MHz

USB
Interface

Sleep

Timer

DMA
CTRL

Comm
Buffer

FEC

CODEC

Read/Write Buffer

ARM 7TDMI

Interrupt
controller

77MHz System Control Bus

Misc.

Config.

Timer

(2)

48MHz / 44 MHz

4KB
Cache

Clock/PLL

DMA

Dual Radio

MAC

W/ DMA Ctrl

JTAG/Test Interface

Radio
Interface

44MHz

Crystal

or

Oscillator

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3.1 Embedded ARM Core and System Support Logic

The processing elements of the CS22210 include the ARM7TDMI core and its associated
system control logic. The ARM processor and system controller consist of a memory
management unit, 4-KB write through cache controller, 20 IRQ and 4 FIRQ interrupt
controller, and 2 general purpose timers. The ARM processor and integrated system support
logic provide the necessary execution engine to support a real time multi-tasking operating
system, the network protocol stack, and firmware services. In addition, system performance
monitor logic is included to aid in system performance fine-tuning (e.g. cache hit, CPI
numbers).

Memory Management Unit

ARM instructions and data are fetched from system memory a cache-line (4/8 – Dwords
/Programmable) at a time when caching is turned on. During a cache line fill, critical word
data, i.e., the access that caused the miss, is forwarded to the ARM and also written into the
data RAM cache. The non-critical words in the line fetched following the critical word are then
written to the cache on a Dword basis, as they become available.

Memory writes are posted to dual 4-Dwords (32-bit) memory write posting buffers. Write
posts use the sequential addressing feature on the memory bus. With dual buffering an out of
sequence write will post to one write buffer while the other buffer is flushed to memory.

There is one 8Dword Read Buffer in the MEM block. The buffer is used for both cacheable
and non-cacheable memory space.

Interrupt Controller

The interrupt controller provides two interrupt channels to the ARM processor. One interrupt
channel is presented to the ARM on its nFIQ, and the other channel is presented on its nIRQ
pin. These are referred to as the FIQ channel and the IRQ channel. Both channels operate
in identical but independent fashion. The FIQ channel has a higher priority on the ARM
processor than the IRQ channel.

The interrupt controller includes a CONTROL register for each logical interrupt in the ARM
complex. The CONTROL register serves the following main purposes:

• Provides the mapping between the EXT_INT inputs (physical interrupts) and the logical
interrupt

• Selects the particular type of signaling expected on the EXT_INT inputs: level, edge,
active level high/low etc.

• Enables or disable a logical interrupt

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3.2 Digital Wireless Radio Interface

The CS22210 digital radio MAC I/F supports multiple radio baseband and RF interfaces. The
baseband registers can be programmed during the configuration time using the control port
interface. The MAC also provides the capability of programming the signal, service and
length on per packet basis without ARM intervention. This significantly improves the
performance of the system.

There are three primary digital interface ports for the CS22210 that are used for configuration
and during normal operation.

These ports are:

• The Control Port, which is used to configure, set power consumption modes, write and/or
read the status of the radio base band registers.

• The TX Port, which is used to output the data that needs to be transmitted from the
network processor.

• The RX Port, which is used to input the received demodulated data to the network
processor.

3.3 FEC Codec

The FEC codec performs Reed-Solomon code encoding to protect the data before it is
transmitted to a noisy channel. It is a similar code as employed by digital broadcast industry,
such as ITU-T J.83 for DVB. The RS(255, 239) code implemented by the SWG2710 can
reduce error probability to 1/10e-9 in a typical 1/10e-3 error rate environment. The
encoder/decoder can be programmed to vary the coding block length (N) and correctable
error (t) to optimize the tradeoff between channel utilization and data protection. The range of
N iscurrentlysettobefrom50to255,andthet is 8. The symbol size is fixed at 8 bits.

Coding parameters can be set real time, allowing maximum flexibility for the system to adjust
the FEC setting, such as block size, in order to optimize channel efficiency. The encoder also
has a very low latency of two cycles. Both the encoder and decoder are fully pipelined in
structure to achieve single cycle throughput. The FEC can be disabled in firmware.

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3.4 Programmable Memory Controller

The CS22210 incorporates a general purpose memory controller that supports a
SDRAM/async SRAM memory and FLASH memory interface.

In the RAM configuration, the system memory interface supports up to 16-Mbyte of 16-bit
SDRAM running at a frequency up to 103 MHz single-state access cycles or 256KB of 16 bit
async SRAM. The memory controller provides programming of SDRAM parameters such as
CAS latency, refresh rate etc; these registers are located in miscellaneous configuration
registers. When there are no pending memory requests from any internal requester, the
CS22210 will keep Clock Enable (CKE) signal low to cause the SDRAM to stay in power
down mode. Once a memory request is active, the CS22210 will assert CKE high to cause
the SDRAM to come out of power down mode. Typically, this can reduce memory power
consumption by up to 50%.

In ROM configuration, firmware for CS22210 is stored in non-volatile memory and is
accessed through the Boot ROM interface. The maximum addressable ROM space
supported is 1MB. ROM read/write and output enable are shared with RAM control pins. The
ROM can be re-flashed allowing for software upgrades.

3.5 PCI Controller Interface

Embedded in the CS22210 is a PCI 2.1 / PCI 2.2 fully compliant master/target 32 bit data
interface including power management support (PME signal). The communication buffer
logic was designed to be flexible and generic to both the PC software and ARM firmware.

The control communication between PCI and ARM uses a mailbox mechanism. The PCI
writes data into a Dword mailbox register whereby an interrupt is generated to the ARM. The
ARM reads this register to get the control information whereby an interrupt is generated to the
PCI. The same is true from the ARM writing to a ARM mailbox register.

PCI data transfer is supported by a DMA Control Block (DCB). The DCB is configured by the
ARM, allowing the ARM to control how often it is interrupted. PCI data transfers are done by
the PCI master and the DCB offloading CPU overhead.

3.6 USB Interface

Embedded within the CS22210 is a full speed USB 1.1 compliant device interface. The
device supports from 1 to 16 endpoints and is completely programmable via firmware
download or external EEPROM.

All “setup” commands are passed to the system processor for interpretation. The device also
contains a DMA engine to transfer arbitrary amounts of data to and from main memory before
interrupting the system processor.

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4 Pinout and Signal Descriptions

K

System
Memory
Interface

JTAG Interface

System and PCI Reset

Clock Interface

PLL Power
Interface

Figure 3. CS22210 Logical Pin Groupings (note: not all signals are shown)

SMCLK

nSMCS[1:0]

nSMRAS

nSMCAS

nSMWE

SMDQM[1:0]

SMCKE

SMA[11:0]

SMD[15:0]

nBRCE

nTRST

nRST

XTALCLKIN

XTALOUT

XTRACLK

PLLAGND

PLLAVCC

PLLDVCC

PLLDGND

PLLPLUS

USB_ENUM

TDO

TDI

TCK

TMS

nPERR, nSERR

CS22210

Wireless
Network

Controller

nSERR

nPERR

PCLK

AD[31:0]

nCBE[3:0]

IDSEL

nFRAME

nIRDY

nTRDY

nDEVSEL

nSTOP

NRST

NINTA

PME

nRST

nREQ

nGNT

PARX

SYNTH_LE1

SYNTH_LE2

TXCLK

TXPE

TXD

TXRDY

CCA

BBRNW

nRESETBB

BBAS

nBBCS

TXPAPE

TXPEBB

RXPEBB

BBSCLK

BBSDX

PCI Controller

Interface

Digital Wireless Radio

USB
Interface

DACAVCC & DACAGND

USBVPX

USBVMX

NTEST

nRPD

RXCL

MDRDY

RXD

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This section provides detailed information on the CS22210 signals. The signal descriptions are
useful for hardware designers who are interfacing the CS22210 with other devices.

System Memory Interface

The system memory interface supports standard SDRAM interface, async SRAM and FLASH.
There are total of 37 signals in this interface.

SMCLK Output

System mem clock for SDRAM. Currently the interface supports 103 MHz
for a maximum bandwidth of 200Mbytes/sec.

nSMCS0 Output

Chip select bit 0. This signal is used to select or deselect the SDRAM for
command entry. When SMNCS is low it qualifies the sampling of
nSMRAS, nSMCAS and nSMWE. Also used as testmode(2) when NTEST
pin is '0'.

nSMCS Output

Chip select bit 1.

nBRCE Output

Chip select for ROM access. This signal is used to select or deselect the
boot ROM memory.

nSMRAS Output

Row address select. Used in combination with nSMCAS, nSMWE and
nSMCS to specify which SDRAM page to open for access. Also used
during reset to latch in the strap value for clk_bypass; if set to a '1' implies
bypassing clock module; whatever clk is applied on the input clock is used
for memclk and ctlclk. Also shared as the ROMOE signal.

NSMCAS Output

Column address select. Used in combination with nSMRAS, nSMWE and
nSMCS to specify which piece of data to access in selected page. Also
used during reset to latch in the strap value for same_freq; if set to a '1'
implies internal mem_clk and arm_clk are running at the same frequency
and 180 degrees out of phase.

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nSMWE Output

Write enable is used in combination with nSMRAS, nSMCAS, and
nSMWE to specify whether the current cycle is a read or a write cycle.
Also used during reset to latch in the strap value for tst_bypass; if set to a
'1' implies PLL bypass. Also shared as the ROMWE to do flash
programming.

SMDQM[1:0] Output

Data mask bit 1:0. These signals function as byte enable lines masking
unwanted bytes on memory writes. Also used as testmode(1:0) when
NTEST pin is '0'.

SMCKE Output

Clock enable. SMCKE is used to enable and disable clocking of internal
RAM logic.

SMA0 Output

Address bit0. The address bus specifies either the row address or column
address. Also shared as boot-rom address bit0. This pin should be pull­down.

SMA1 Output

Address bit1. Also shared as boot-rom address bit1. Also used during
reset to latch in the strap value for pcisel; if set to a '1' implies pci mode.

SMA2 Output

Address bit2. Also shared as boot-rom address bit2. Also used during
reset to latch in the strap value for usbsel; if set to a '1' implies usb mode.

SMA3 Output

Address bit3. Also shared as boot-rom address bit3. This pin should be
pull-down.

SMA4 Output

Address bit4. Also shared as boot-rom address bit4. Also used during
reset to latch in the strap value for romcfg; if set to a '1' implies pci
configuration data should be downloaded from ROM.

SMA5 Output

Address bit5. Also shared as boot-rom address bit5. Also used during
reset to latch in the strap value for test_rst_enb; if set to a '0' implies
normal operation mode.

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