Cirrus Logic CS2100-OTP User Manual
Fractional-N Clock Multiplier
Hardware Configuration
Auxiliary
Output
6 to 75 MHz
PLL Output
Frequency Reference
3.3 V
Hardware
Control
8 MHz to 75 MHz
Low-Jitter Timing
Reference
Fractional-N
Frequency Synthesizer
Digital PLL &
Fractional N Logic
Output to Input
Clock Ratio
N
Timing Reference
PLL Output
Lock Indicator
50 Hz to 30 MHz
Frequency
Reference
CS2100-OTP
Features
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to 30
MHz Clock Source
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in High-
Resolution Mode
One-Time Programmability
– Configurable Hardware Control Pins
– Configurable Auxiliary Output
Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2100-OTP is an extremely versatile system
clocking device that utilizes a programmable phase lock
loop. The CS2100-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an external
noisy synchronization clock with frequencies as low as
50 Hz. The CS2100-OTP has many configuration options which are set once prior to runtime. At runtime
there are three hardware configuration pin s available for
mode and feature selection.
The CS2100-OTP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) and Automotive
(-40°C to +85°C) grades. Customer development kits
are also available for custom device prototyp ing, small
production programming, and device evaluation.
Please see “Ordering Information” on page 26 for complete details.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY '10
DS841F2
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DC ELECTRICAL CHARACTERISTICS . ... ... .... ... ... ... .... ... ... .................................................................. 6
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
PLL PERFORMANCE PLOTS ............................................................................................................... 8
4. ARCHITECTURE OVERVIEW ............................................................................................................... 9
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 9
4.2 Hybrid Analog-Digital Phase Locked Loop ......................................................................................9
5. APPLICATIONS ................................................................................................................................... 11
5.1 One Time Programmability ............................................................................................................ 11
5.2 Timing Reference Clock Input ..................... ................................................................................... 11
5.2.1 Internal Timing Reference Clock Divider .. ... .... ... ... ... .... ... ... ................................................... 11
5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 12
5.2.3 External Reference Clock (REF_CLK) .................................................................................. 12
5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 12
5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 13
5.4 Output to Input Frequency Ratio Configuration ............................................................................. 14
5.4.1 User Defined Ratio (RUD) ..................................................................................................... 14
5.4.2 Ratio Modifier (R-Mod) .......................................................................................................... 15
5.4.3 Effective Ratio (REFF) .......................................................................................................... 15
5.4.4 Ratio Configuration Summary ............................................................................................... 15
5.5 PLL Clock Output ........................................................................................................................... 16
5.6 Auxiliary Output ................. ... ... .... ... ... ....................................... ... ... ... .... ......................................... 17
5.7 Mode Pin Functionality ...................... ... ... ....................................... ... .... ... ... ... .... ... ... ...................... 17
5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 17
5.7.2 M2 Mode Pin Functionality .................................................................................................... 18
5.7.2.1 M2 Configured as Output Disable .............................................................................. 18
5.7.2.2 M2 Configured as R-Mod Enable .............. ... .... ... ... ....................................... ... ... ... ... 18
5.7.2.3 M2 Configured as AuxOutSrc Override ..................................................................... 18
5.8 Clock Output Stability Considerations ......... ... ... ... .... ... ... ... .... ...................................... ... .... ... ......... 19
5.8.1 Output Switching ................................................................................................................... 19
5.8.2 PLL Unlock Conditions .......................................................................................................... 19
5.9 Required Power Up Sequencing for Programmed Devices .................. ......................................... 19
6. PARAMETER DESCRIPTIONS ........................................................................................................... 20
6.1 Modal Configuration Sets ..................... ... ....................................... ... .... ... ... ... .... ... ... ...................... 20
6.1.1 R-Mod Selection (RModSel[1:0]) ........................ ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ...20
6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) .................... ......................................... 21
6.2 Ratio 0 - 3 ...................................... ... ... ... .... ... ... ....................................... ... ... ................................ 21
6.3 Global Configuration Parameters ................................................................................................... 21
6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 21
6.3.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 21
6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 22
6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 22
6.3.5 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 22
6.3.6 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 22
7. CALCULATING THE USER DEFINED RATIO .................................................................................... 23
7.1 High Resolution 12.20 Format .... ... ... ... ... .... ... ... ... .......................................................................... 23
7.2 High Multiplication 20.12 Format ................................................................................................... 23
8. PROGRAMMING INFORMATION ........................................................................................................ 24
CS2100-OTP
DS841F2 2
9. PACKAGE DIMENSIONS .................................................................................................................... 25
THERMAL CHARACTERISTICS ......................................................................................................... 25
10. ORDERING INFORMATION ........... ... ... ... ... .... ... ....................................... ... ... ... .... ... ... ... ... .... ... ......... 26
11. REVISION HISTORY ................................ ... .... ... ....................................... ... ... ... .... ... ... ... ................... 26
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 8
Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 8
Figure 4. CLK_IN Random Jitter Rejection and Tolerance .............. ... ...................................... .... ... ... ... .... .8
Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer .......................................................................9
Figure 6. Hybrid Analog-Digital PLL .......................................................................................................... 10
Figure 7. Internal Timing Reference Clock Divider ................................................................................... 11
Figure 8. REF_CLK Frequency vs a Fixed CLK_OUT .............................................................................. 12
Figure 9. External Component Requirements for Crystal Circuit .............................................................. 12
Figure 10. Low bandwidth and new clock domain .................................................................................... 13
Figure 11. High bandwidth with CLK_IN domain re-use ........................................................................... 13
Figure 12. Ratio Feature Summary ........................................................................................................... 16
Figure 13. PLL Clock Output Options ....................................................................................................... 16
Figure 14. Auxiliary Output Selection ........................... .......................................... ................................... 17
Figure 15. M2 Mapping Options ................................................................................................................ 18
Figure 16. Parameter Configuration Sets .................................................................................................. 20
CS2100-OTP
LIST OF TABLES
Table 1. Modal and Global Configuration ........................ .... ... ... ... .... ... ... ... ... .... ... ...................................... 11
Table 2. Ratio Modifier .............................................................................................................................. 15
Table 3. Example 12.20 R-Values ............................................................................................................ 23
Table 4. Example 20.12 R-Values ............................................................................................................ 23
DS841F2 3
CS2100-OTP
1
2
3
4
5
6
7
8
9
10
XTO
CLK_OUT
GND
VD
XTI/REF_CLK
M2
M1
M0
AUX_OUT
CLK_IN
1. PIN DESCRIPTION
Pin Name # Pin Description
VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.
GND 2 Ground (Input) - Ground reference.
CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.
AUX_OUT 4
CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference.
XTO
XTI/REF_CLK
M2 8 Mode Select (Input) - M2 is a configurable mode selection pin.
M1 9 Mode Select (Input) - M1 is a configurable mode selection pin.
M0 10 Mode Select (Input) - M0 is a configurable mode selection pin.
Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on configuration.
Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -
6
XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input
7
clock. REF_CLK is an input for an externally generated low-jitter reference clock.
4 DS841F2
2. TYPICAL CONNECTION DIAGRAM
2
1
GND
M2
M1
XTI/REF_CLK
Frequency Reference CLK_IN
XTO
CLK_OUT
AUX_OUT
0.1 µF
VD
+3.3 V
M0
Low-Jitter
Timing Reference
System Microcontroller
1 µF
1
or
2
REF_CLK
XTO
XTI
XTO
or
40 pF
x
40 pF
Crystal
To circuitry which requires
a low-jitter clock
N.C.
To other circuitry or
Microcontroller
Figure 1. Typical Connection Diagram
CS2100-OTP
CS2100-OTP
DS841F2 5
CS2100-OTP
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note 1)
Parameters Symbol Min Typ Max Units
DC Power Supply (Note 2) VD 3.1 3.3 3.5 V
Ambient Operating Temperature (Power Applied)
Commercial Grade
Automotive Grade
T
AC
T
AD
-10
-40
-
-
+70
+85
°C
°C
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits
may adversely affect device reliability.
2. CLK_IN must not be applied when these conditions are not met, including during power up. See section
5.9 on page 19 for required power up procedure.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply VD -0.3 6.0 V
Input Current I
Digital Input Voltage (Note 3)V
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
IN
IN
A
stg
-±10mA
-0.3 VD + 0.4 V
-55 125 °C
-65 150 °C
WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Notes: 3. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T
= -40°C to +85°C (Automotive Grade).
A
Parameters Symbol Min Typ Max Units
Power Supply Current - Unloaded (Note 4)I
Power Dissipation - Unloaded (Note 4)P
Input Leakage Current I
Input Capacitance I
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (IOH = -1.2 mA) V
Low-Level Output Voltage (I
= 1.2 mA) V
OH
D
D
IN
C
IH
IL
OH
OL
Notes: 4. To calculate the additional current consumption due to loading (per output pin), multiply clock output
frequency by load capacitance and power supply voltage.
For example,
f
CLK_OUT
(49.152 MHz) * CL (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to
these loading conditions on CLK_OUT.
-1218mA
-4060mW
--±10µA
-8-pF
70% - - VD
--30%VD
80% - - VD
--20%VD
6 DS841F2
CS2100-OTP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
= -40°C to +85°C (Automotive Grade); CL=15pF.
T
A
Parameters Symbol Conditions Min Typ Max Units
Crystal Frequency
Fundamental Mode XTAL
Reference Clock Input Frequency f
Reference Clock Input Duty Cycle D
Internal System Clock Frequency f
Clock Input Frequency f
Clock Input Pulse Width (Note 5)pw
PLL Clock Output Frequency f
PLL Clock Output Duty Cycle t
Clock Output Rise Time t
Clock Output Fall Time t
Period Jitter t
Base Band Jitter (100 Hz to 40 kHz) (Notes 6, 7) - 50 - ps rms
Wide Band JItter (100 Hz Corner) (Notes 6, 8) - 175 - ps rms
PLL Lock Time - CLK_IN (Note 9)t
PLL Lock Time - REF_CLK t
Output Frequency Synthesis Resolution (Note 10)f
f
XTAL
REF_CLK
REF_CLK
SYS_CLK
CLK_IN
CLK_IN
CLK_OUT
OD
OR
OF
JIT
LC
LR
err
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
8
16
32
8
16
32
-
18.75
-
37.5
-
-
-
-
50
18.75
37.5
75
45 - 55 %
8 18.75 MHz
50 Hz - 30 MHz
f
CLK_IN
f
CLK_IN
< f
> f
SYS_CLK
SYS_CLK
/96
/96
2
10
-
-
-
-
6-75MHz
Measured at VD/2 45 50 55 %
20% to 80% of VD - 1.7 3.0 ns
80% to 20% of VD - 1.7 3.0 ns
(Note 6) - 70 - ps rms
-
f
< 200 kHz
CLK_IN
> 200 kHz
f
CLK_IN
f
REF_CLK
= 8 to 75 MHz - 1 3 ms
High Resolution
High Multiplication
100
-
1
0
0
200
3
-
±0.5
-
±112
MHz
MHz
MHz
MHz
MHz
MHz
UI
ns
UI
ms
ppm
ppm
Notes: 5. 1 UI (unit interval) corresponds to t
6.
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.
SYS_CLK
or 1/f
SYS_CLK
.
7. In accordance with AES-12id-2006 section 3.4.2. Measurem ents are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
8. In accordance with AES-12id-2006 section 3.4.1. Measurem ents are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
9. 1 UI (unit interval) corresponds to t
CLK_IN
or 1/f
CLK_IN
.
10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
DS841F2 7
PLL PERFORMANCE PLOTS
1 10 100 1,000 10,000
0.1
1
10
100
1,000
10,000
Input Jitter Frequency (Hz)
Max Input Jitter Level (usec)
1 Hz Bandwidth
128 Hz Bandwidth
1 10 100 1000 10000
-60
-50
-40
-30
-20
-10
0
10
Input Jitter Frequency (Hz)
Jitter Transfer (dB)
1 Hz Bandwidth
128 Hz Bandwi dth
Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
Figure 4. CLK_IN Random Jitter Rejection and To lerance
0.01 0.1 1 10 100 1000
0.01
0.1
1
10
100
1000
Inpu t Jit ter Level ( nsec)
Output Jitt e r Level ( nsec)
1 Hz Bandwidt h
128 Hz Bandwidt h
Unlock
Unlock
Test Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; f
CLK_IN
= 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] =11.
f
CLK_OUT
CS2100-OTP
= 12.288 MHz;
8 DS841F2
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