Cirrus Logic CS2100-CP User Manual
Fractional-N Clock Multiplier
I²C / SPI
Auxiliary
Output
6 to 75 MHz
PLL Output
3.3 V
I²C/SPI
Software Control
8 MHz to 75 MHz
Low-Jitter Timing
Reference
Fractional-N
Frequency Synthesizer
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
N
Timing Reference
PLL Output
Lock Indicator
50 Hz to 30 MHz
Frequency
Reference
Frequency Reference
CS2100-CP
Features
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to 30
MHz Clock Source
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in High-
Resolution Mode
I²C™ / SPI™ Control Port
Configurable Auxiliary Output
Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2100-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2100-CP is based on a hybrid analog-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an external noisy synchronization clock at frequencies as low
as 50 Hz. The CS2100-CP supports both I²C and SPI
for full software control.
The CS2100-CP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) and Automotive
(-40°C to +85°C) grades. Customer development kits
are also available for device evaluation. Please see
“Ordering Information” on page 32 for complete details.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY '10
DS840F2
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 5
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7
RECOMMENDED OPERATING CONDITIONS .................................................................................... 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7
DC ELECTRICAL CHARACTERISTICS . ... ... .... ... ... ... .... ... ... ....................................... ... ... ... .... ... ... ... .... . 7
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8
PLL PERFORMANCE PLOTS ............................................................................................................... 9
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ........................ ... ...................... 10
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 11
4. ARCHITECTURE OVERVIEW ............................................................................................................. 12
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 12
4.2 Hybrid Analog-Digital Phase Locked Loop ....................................................................................12
5. APPLICATIONS ................................................................................................................................... 14
5.1 Timing Reference Clock Input ..................... ...................................... .... ... ... ... .... ... ... ... ... .... ............ 14
5.1.1 Internal Timing Reference Clock Divider .. ... .... ... ... ... .... ... ... ....................................... ... ... ... ... 14
5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 15
5.1.3 External Reference Clock (REF_CLK) .................................................................................. 15
5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 15
5.2.1 CLK_IN Skipping Mode ............ ... ... .... ... ... ... .... ... .......................................... ......................... 15
5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 17
5.3 Output to Input Frequency Ratio Configuration ............................................................................. 18
5.3.1 User Defined Ratio (RUD) ..................................................................................................... 18
5.3.2 Ratio Modifier (R-Mod) .......................................................................................................... 19
5.3.3 Effective Ratio (REFF) .......................................................................................................... 20
5.3.4 Ratio Configuration Summary ............................................................................................... 20
5.4 PLL Clock Output ........................................................................................................................... 21
5.5 Auxiliary Output ................. ... ... .... ... ... ....................................... ... ... ... ............................................. 21
5.6 Clock Output Stability Considerations ......... ... ... ... .... ... ... ... .... ...................................... ... .... ... ......... 22
5.6.1 Output Switching ................................................................................................................... 22
5.6.2 PLL Unlock Conditions .......................................................................................................... 22
5.7 Required Power Up Sequencing ................................................................. ... .... ... ... ... ... ................ 22
6. SPI / I²C CONTROL PORT ...................... ... ... .... ... ... ... ....................................... ... .... ... ......................... 22
6.1 SPI Control ........................ ... ....................................... ... ... .... ......................................................... 23
6.2 I²C Control .................. .... ... ... ... .... ... ....................................... ... ...................................................... 23
6.3 Memory Address Pointer ........................ .... ...................................... .... ... ... ... .... ... ......................... 25
6.3.1 Map Auto Increment .............................................................................................................. 25
7. REGISTER QUICK REFERENCE ........................................................................................................ 25
8. REGISTER DESCRIPTIONS ................................................................................................................ 26
8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 26
8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 26
8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 26
8.2 Device Control (Address 02h) ................. .............................................. ......................................... 26
8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 26
8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 26
8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 27
8.3 Device Configuration 1 (Address 03h) ........................................................................................... 27
8.3.1 R-Mod Selection (RModSel[2:0]) ........................ ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ...27
8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) .................... ......................................... 27
8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ............................ ............................ 28
8.4 Global Configuration (Address 05h) ............................................................................................... 28
8.4.1 Device Configuration Freeze (Freeze) ................................................................................ 28
CS2100-CP
2 DS840F2
8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 28
8.5 Ratio (Address 06h - 09h) .............................. ... ... .... ... ....................................... ... ... ... ... ................ 28
8.6 Function Configuration 1 (Address 16h) ............................... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 29
8.6.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 29
8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 29
8.6.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 29
8.7 Function Configuration 2 (Address 17h) ............................... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 30
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 30
8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 30
8.8 Function Configuration 3 (Address 1Eh) ........................................ ... .... ... ...................................... 30
8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 30
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 31
9.1 High Resolution 12.20 Format ....................................................... ... .... ......................................... 31
9.2 High Multiplication 20.12 Format ................................................................................................... 31
10. PACKAGE DIMENSIONS .................. ... ... ... .... ... ....................................... ... ... ... .... ... ... ...................... 32
THERMAL CHARACTERISTICS ......................................................................................................... 32
11. ORDERING INFORMATION .............. ... ... ... .... ... ... ... .... ... ....................................... ... ... ... ... .... ... ......... 33
12. REFERENCES ....................... ... ... .... ... ... ... ... .... ... ... ....................................... ... ... .... ... ... ...................... 33
13. REVISION HISTORY ............................. ... ... .... ... ....................................... ... ... ... .... ... ... ...................... 34
LIST OF FIGURES
CS2100-CP
Figure 1. Typical Connection Diagram ........................................................................................................ 6
Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 9
Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 9
Figure 4. CLK_IN Random Jitter Rejection and Tolerance .......... .... ... ...................................... .... ... ... ........9
Figure 5. Control Port Timing - I²C Format ................................................................................................ 10
Figure 6. Control Port Timing - SPI Format (Write Only) .......................................................................... 11
Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 12
Figure 8. Hybrid Analog-Digital PLL .......................................................................................................... 13
Figure 9. Internal Timing Reference Clock Divider ................................................................................... 14
Figure 10. REF_CLK Frequency vs. a Fixed CLK_OUT ........................................................................... 14
Figure 11. External Component Requirements for Crystal Circuit ............................................................ 15
Figure 12. CLK_IN removed for > 2
Figure 13. CLK_IN removed for < 2
Figure 14. CLK_IN removed for < t
Figure 15. Low bandwidth and new clock domain .................................................................................... 18
Figure 16. High bandwidth with CLK_IN domain re-use ........................................................................... 18
Figure 17. Ratio Feature Summary ........................................................................................................... 20
Figure 18. PLL Clock Output Options ....................................................................................................... 21
Figure 19. Auxiliary Output Selection ........................... .......................................... ................................... 21
Figure 20. Control Port Timing in SPI Mode ............................................................................................. 23
Figure 21. Control Port Timing, I²C Write .................................................................................................. 24
Figure 22. Control Port Timing, I²C Aborted Write + Read .......................................................................24
23
SysClk cycles ................................................................................ 16
23
SysClk cycles but > t
CS .................................................................................................................................. 17
CS .................................................................................. 16
LIST OF TABLES
Table 1. Ratio Modifier .............................................................................................................................. 19
Table 2. Example 12.20 R-Values ............................................................................................................ 31
Table 3. Example 20.12 R-Values ............................................................................................................ 31
DS840F2 3
CS2100-CP
1
2
3
4
5
6
7
8
9
10
XTO
CLK_OUT
GND
VD
XTI/REF_CLK
AD0/CS
SCL/CCLK
SDA/CDIN
AUX_OUT
CLK_IN
1. PIN DESCRIPTION
Pin Name # Pin Description
VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.
GND 2 Ground (Input) - Ground reference.
CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.
AUX_OUT
CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference.
XTO
XTI/REF_CLK
AD0/CS
SCL/CCLK
SDA/CDIN
4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on register configuration.
67Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -
XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input
clock. REF_CLK is an input for an externally generated low-jitter reference clock.
8 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C
Mode. CS is the chip select signal in SPI Mode.
9 Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI
mode.
10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data
line for the control port interface in SPI Mode.
4 DS840F2
2. TYPICAL CONNECTION DIAGRAM
2
1
GND
SCL/CCLK
SDA/CDIN
2 kΩ
XTI/REF_CLK
Frequency Reference CLK_IN
XTO
CLK_OUT
AUX_OUT
0.1 µF
VD
+3.3 V
Notes:
1. Resistors
required for I
2
C
operation.
2 kΩ
AD0/CS
Low-Jitter
Timing Reference
System MicroController
1 µF
Note
1
1
or
2
REF_CLK
XTO
XTI
XTO
or
40 pF
x
40 pF
Crystal
To circuitry which requires
a low-jitter clock
N.C.
To other circuitry or
Microcontroller
Figure 1. Typical Connection Diagram
CS2100-CP
CS2100-CP
DS840F2 5
CS2100-CP
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note 1)
Parameters Symbol Min Typ Max Units
DC Power Supply VD 3.1 3.3 3.5 V
Ambient Operating Temperature (Power Applied)
Commercial Grade
Automotive Grade
T
AC
T
AD
-10
-40
-
-
+70
+85
°C
°C
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits
may adversely affect device reliability.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply VD -0.3 6.0 V
Input Current I
Digital Input Voltage (Note 2)V
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
IN
IN
A
stg
-±10mA
-0.3 VD + 0.4 V
-55 125 °C
-65 150 °C
WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T
= -40°C to +85°C (Automotive Grade).
A
Parameters Symbol Min Typ Max Units
Power Supply Current - Unloaded (Note 3)I
Power Dissipation - Unloaded (Note 3)P
Input Leakage Current I
Input Capacitance I
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (I
Low-Level Output Voltage (I
= -1.2 mA) V
OH
= 1.2 mA) V
OH
D
D
IN
C
IH
IL
OH
OL
Notes: 3. To calculate the additional current consumption due to loading (per output pin), multiply clock output
frequency by load capacitance and power supply voltage.
For example,
f
CLK_OUT
(49.152 MHz) * CL (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to
these loading conditions on CLK_OUT.
-1218mA
-4060mW
--±10µA
-8-pF
70% - - VD
--30%VD
80% - - VD
--20%VD
6 DS840F2
CS2100-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
= -40°C to +85°C (Automotive Grade); CL=15pF.
T
A
Parameters Symbol Conditions Min Typ Max Units
Crystal Frequency
Fundamental Mode XTAL
Reference Clock Input Frequency f
Reference Clock Input Duty Cycle D
Internal System Clock Frequency f
Clock Input Frequency f
Clock Input Pulse Width (Note 4)pw
Clock Skipping Timeout t
Clock Skipping Input Frequency f
PLL Clock Output Frequency f
PLL Clock Output Duty Cycle t
Clock Output Rise Time t
Clock Output Fall Time t
Period Jitter t
Base Band Jitter (100 Hz to 40 kHz) (Notes 7, 8) - 50 - ps rms
Wide Band JItter (100 Hz Corner) (Notes 7, 9) - 175 - ps rms
PLL Lock Time - CLK_IN (Note 10)t
PLL Lock Time - REF_CLK t
Output Frequency Synthesis Resolution (Note 11)f
f
XTAL
REF_CLK
REF_CLK
SYS_CLK
CLK_IN
CLK_IN
CS
CLK_SKIP
CLK_OUT
OD
OR
OF
JIT
LC
LR
err
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
8
16
32
8
16
32
-
18.75
-
37.5
-
-
-
-
50
18.75
37.5
75
MHz
MHz
MHz
MHz
MHz
MHz
45 - 55 %
8 18.75 MHz
50 Hz - 30 MHz
f
CLK_IN
f
CLK_IN
< f
> f
SYS_CLK
SYS_CLK
/96
/96
2
10
-
-
-
-
(Notes 5, 6)20--ms
(Note 6) 50 Hz - 80 kHz
6-75MHz
Measured at VD/2 45 50 55 %
20% to 80% of VD - 1.7 3.0 ns
80% to 20% of VD - 1.7 3.0 ns
(Note 7) - 70 - ps rms
f
< 200 kHz
CLK_IN
f
> 200 kHz
CLK_IN
f
REF_CLK
= 8 to 75 MHz - 1 3 ms
High Resolution
High Multiplication
-
100
-
1
0
0
200
3
-
±0.5
-
±112
ms
ppm
ppm
UI
ns
UI
Notes: 4. 1 UI (unit interval) corresponds to t
5. t
represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
CS
SYS_CLK
or 1/f
SYS_CLK
.
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequency, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t
CS
.
6. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 14 for more information.
7.
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.
8. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Inte rval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
9. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Inte rval Error taken with 3rd
order 100 Hz Highpass filter.
10. 1 UI (unit inte rva l) co rr esponds to t
CLK_IN
or 1/f
CLK_IN
.
11. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
DS840F2 7
PLL PERFORMANCE PLOTS
1 10 100 1,000 10,000
0.1
1
10
100
1,000
10,000
Input Jitter Frequency (Hz)
Max Input Jitter Level (usec)
1 Hz Bandwidth
128 Hz Bandwidth
1 10 100 1000 10000
-60
-50
-40
-30
-20
-10
0
10
Input Jitter Frequency (Hz)
Jitter Transfer (dB)
1 Hz Bandwidth
128 Hz Bandwi dth
Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
Figure 4. CLK_IN Random Jitter Rejection and To lerance
0.01 0.1 1 10 100 1000
0.01
0.1
1
10
100
1000
Inpu t Jit ter Level ( nsec)
Output Jitt e r Level ( nsec)
1 Hz Bandwidt h
128 Hz Bandwidt h
Unlock
Unlock
Test Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; f
CLK_IN
= 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] =11.
f
CLK_OUT
CS2100-CP
= 12.288 MHz;
8 DS840F2
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT
t
buf
t
hdst
t
hdst
t
low
t
r
t
f
t
hdd
t
high
t
sud
t
sust
t
susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
VD
t
dpor
Figure 5. Control Port Timing - I²C Format
Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.
Parameter Symbol Min Max Unit
SCL Clock Frequency f
Bus Free-Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 12)t
SDA Setup Time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling t
Delay from Supply Voltage Stable to Control Port Ready t
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
ack
dpor
- 100 kHz
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
300 1000 ns
100 - µs
CS2100-CP
Notes: 12. Data must be held for sufficient time to bridge the transition time, t
, of SCL.
f
DS840F2 9
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
csh
t
spi
t
dpor
VD
Figure 6. Control Port Timing - SPI Format (Write Only)
Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
CCLK Edge to CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CS
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 14)t
Rise Time of CCLK and CDIN (Note 15)t
Fall Time of CCLK and CDIN (Note 15)t
Delay from Supply Voltage Stable to Control Port Ready t
Notes: 13.
Falling (Note 13)t
t
is only needed before first falling edge of CS after power is applied. t
spi
ccllk
spi
csh
css
scl
sch
dsu
dh
r2
f2
dpor
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. For f
< 1 MHz.
cclk
-6MHz
500 - ns
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
- 100 ns
- 100 ns
100 - µs
= 0 at all other times.
spi
CS2100-CP
10 DS840F2
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