Cirrus Logic CS1616 User Manual

CS1615

Mains

BR1

CS1615/16

FBAUX

GND

IAC

LED+

VDD

SOURCE

eOTP

NTC

LED-

FBSENSE

Sense

SGN D4CTRL1 CTRL2

CTRL1

CTRL2

C1 C2

rect

AUX

R4 R5

CS1616

Single Stage Dimmable Offline AC/DC

Controller for LED Lamps

Features

• Best-in-class Dimmer Compatibility

- Leading-edge (TRIAC) Dimmers

- Trailing-edge Dimmers

- Digital Dimmers (Dimmers with an Integrated Power Supply)

• Flicker-free Dimming

• 0% to 100% Smooth Dimming

• Primary-side Regulation (PSR)

• Active Power Factor Correction (PFC)

- >0.9 Power Factor

• Constant-current Output

- Flyback

- Buck-boost

• Tight LED Current Regulation: Better than ±5%

• Low THD: Less Than 20%

• Up to 90% Efficiency

• Fast Startup

• IEC61000-3-2 Compliant

• Meets NEMA SSL 6 Dimming Standard

- Closely Matches Incandescent S-curve

• Protection Features

- Output Open Circuit

- Output Short Circuit

- External Overtemperature Using NTC

Overview

The CS1615 and CS1616 are high-performance single stage dimmable offline AC/DC controllers. The CS1615/ 16 is a cost-effective solution that provides unmatched singleand multi-lamp dimmer-compatibility performance for dimmable LED applications. The CS1615 is designed for 120VAC line voltage applications, and the CS1616 is designed for 230VAC line voltage applications.

Across a broad range of dimmers, the CS1615/16 provides smooth flicker free dimming, and consistently dims to nearly zero light output, which closely matches the dimming performance of incandescent light bulbs. Cirrus Logic’s patent pending approach to dimmer compatibility provides full functionality on a wide range of dimmers, including leading-edge, trailing-edge, and digital dimmers.

Applications

• Retro-fit LED Lamps

• External LED Drivers

• LED Luminaries

• Commercial Lighting

Ordering Information

See page 14.

Cirrus Logic, Inc.

http://www.cirrus.com

JUN’13

DS961F1

1. INTRODUCTION

IAC

SOURCE

SGND

15k

ADC

ref

FBSENSE

DAC

Peak

Contr ol

GND

OLP

OCP

Blank

CLAMP

OCP( th)

OLP(th)

Pk_Max(th)

CLAMP

-V

SOURCE(th)

MUX

CONNECT

CONNECT(th)

CTRL2

CTRL1

eOTP

FBAUX

Zer o-cur rent

Detect

Output

Over voltag e

ZCD(th)

OVP(th)

VAUX

VDD

DD(on)

DD(off)

Volt age

Regul ator

POR

VDD

FSTA RT(th )

CS1615/16

Figure 1. CS1615/16 Block Diagram

A typical schematic using the CS1615/16 IC is shown on the previous page.

Startup current is provided from a patent-pending, external, highvoltage source-follower network. In addition to providing startup current, this unique topology is integral in providing compatibility with digital dimmers by ensuring V

power is always available

to the IC. During normal operation, an auxiliary winding on the flyback transformer or buck-boost inductor back-biases the source-follower circuit and provides steady-state operating current to the IC to improve system efficiency.

Rectified input voltage V and is used to control the adaptive dimmer-compatibility

is sensed as a current into pin IAC

rect

algorithm and to extract the phase of the input voltage for output dimming control. The SOURCE pin is used to provide a control signal for the high-voltage source-follower circuit during Leadingedge Mode and Trailing-edge Mode; it also provides the current during startup.

2 DS961F1

The digital dual-mode controller is implemented with peakcurrent mode primary-side regulation, which eliminates the need for additional components to provide feedback from the secondary and reduces system cost and complexity. Voltage across a user-selected resistor is sensed through pin FBSENSE to control the peak current of the primary-side inductor. Leadingedge and trailing-edge blanking on pin FBSENSE prevents false triggering. The required target LED current and average flyback transformer and buck-boost inductor input current are set by attaching resistors R CTRL2, respectively. The controller ensures half line-cycle averaged constant output current.

Pin FBAUX is used for zero-current detection to ensure quasi-resonant switching of the single stage output. When an external negative temperature coefficient (NTC) thermistor is connected to pin eOTP, the CS1615/16 monitors the system temperature, allowing the controller to reduce the output current of the system. If the temperature reaches a designated high set point, the IC is shut down and stops switching.

CTRL1

and R

on pins CTRL1 and

CTRL2

2. PIN DESCRIPTION

16 -lead SOIC and TSSOP

Zero-current DetectFBAUX

No ConnectNC

IC Supply Vol tageVDD

GD Gate Drive

eOTP External Over tem per atur e Pr otec ti on

FBSENSE Fl yback Curr ent Sense

GND Gr ound

LED Load Cur r entCTRL2

No Connect NC

IACRectifier Voltage Sense

Voltage Clam p C ur r ent Sour ce CLAMP

SGNDSource Gr ound

Source Switch SOURCE

NCNo Connect

No Connect NC

CTRL1Dimmer Hold Current

CS1615/16

Figure 2. CS1615/16 Pin Assignments

Pin Name Pin # I/O

Description

NC 1INNo Connect — Leave pin unconnected.

IAC 2IN

CLAMP 3OUT

Rectifier Voltage Sense — A current proportional to the rectified line voltage is fed

into this pin. The current is measured with an A/D converter.

Voltage Clamp Current Source — Connect to a voltage clamp circuit on the source-switched dimmer-compatibility circuit.

SGND 4PWRSource Ground — Common reference current return for the SOURCE pin.

SOURCE 5IN

Source Switch — Connected to the source of the source-switched external high-volt-

age FET.

NC 6INNo Connect — Connect this pin to VDD using a 47k pull-up resistor.

NC 7INNo Connect — Connect this pin to VDD using a 47kpull-up resistor.

CTRL1 8IN

Dimmer Hold Current — Connect a resistor to this pin to set the minimum input cur-

rent being pulled by the flyback / buck-boost stage.

CTRL2 9INLED Load Current — Connect a resistor to this pin to set the LED current.

eOTP 10 IN

External Overtemperature Protection — Connect an external NTC thermistor to this

pin, allowing the internal A/D converter to sample the change to NTC resistance.

Feedback Current Sense — The current flowing in the power FET is sensed across a

FBSENSE 11 IN

resistor. The resulting voltage is applied to this pin and digitized for use by the computational logic to determine the FET's duty cycle.

GND 12 PWR

Ground — Common reference. Current return for both the input signal portion of the

IC and the gate driver.

GD 13 OUT Gate Drive — Gate drive for the power FET.

IC Supply Voltage — Connect a storage capacitor to this pin to serve as a reservoir

VDD 14 PWR

for operating current for the device, including the gate drive current to the power transistor.

NC 15 - No Connect — Leave pin unconnected.

FBAUX 16 IN

Zero-current Detect — Connect to the flyback/buck-boost inductor auxiliary winding

for demagnetization current zero-crossing detection.

DS961F1 3

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 Electrical Characteristics

CS1615/16

Typical characteristics conditions:

=25°C, VDD=12V, GND=0V

•T

• All voltages are measured with respect to GND.

Minimum/Maximum characteristics conditions:

•TJ= -40°C to +125 °C, VDD= 11V to 17V, GND = 0 V

• Unless otherwise specified, all currents are positive when flowing into the IC.

Parameter Condition Symbol Min Typ Max Unit

VDD Supply Voltage

Operating Range

Turn-on Threshold Voltage

Turn-off Threshold Voltage (UVLO)

Zener Voltage

(Note 1)

After Turn-on

VDD Increasing

VDD Decreasing

=20mA

ST(th)

STP(th)

11 - 17 V

-8.5-V

-7.5-V

18.5 - 19.8 V

VDD Supply Current

Startup Supply Current

Operating Supply Current

(Note 2)

VDD<V

ST(th)

= 0.25nF, fsw70 kHz

--200A

-4.5-mA

Reference

Reference Current

CS1615 CS1616

rect

=200V =400V

ref

133 133

A A

Zero-current Detect

FBZCD Threshold V

FBZCD Blanking t

ZCD Sink Current

FBAUX Upper Voltage

(Note 3) I

=1mA

ZCD

FBZCD(th)

FBZCB

ZCD

-200-mV

-2-s

-2 - - mA

-VDD+0.6 - V

Current Sense

Max Peak Control Threshold V

Pk_Max(th)

Leading-edge Blanking t

LEB

-1.4-V

-550-ns

Delay to Output --100ns

Pulse Width Modulator

Minimum On Time - 0.55 - s

Maximum On Time - 12.8 - s

Minimum Switching Frequency t

Maximum Switching Frequency t

FB(Min)

FB(Max)

-6-kHz

-200-kHz

Gate Driver

Output Source Resistance Z

Output Sink Resistance Z

Rise Time

Fall Time

CL=0.25nF

OUT

-24-

-11-

--30ns

--20ns

4 DS961F1

CS1615/16

Parameter Condition Symbol Min Typ Max Unit

Flyback/Buck-boost Protections

Overcurrent Protection (OCP)

Overvoltage Protection (OVP)

Open Loop Protection (OLP)

(Note 4) V

(Note 5) V

(Note 4) V

OCP(th)

OVP(th)

OLP(th)

External Overtemperature Protection (eOTP)

Pull-up Current Source – Maximum I

Conductance Accuracy

Conductance Offset

(Note 6) --±5

(Note 6) -±250-nS

Current Source Voltage Threshold V

CONNECT

CONNECT(th)

Internal Overtemperature Protection (iOTP)

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

Notes: 1. The CS1615/ 16 has an internal shunt regulator that limits the voltage on the VDD pin. Shunt regulation voltage VZ is defined in

the VDD Supply Voltage section on page 4.

2. For test purposes, load capacitance C

3. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased does not exceed specification.

4. Protection is implemented using pin FBSENSE. See the CS1615/ 16 Block Diagram on page 2.

5. Protection is implemented using pin FBAUX. See the CS1615/ 16 Block Diagram on page 2

6. The conductance is specified in Siemens (S or 1/ ). Each LSB of the internal ADC corresponds to 250 nS or one parallel 4 M resistor. Full scale corresponds to 256 parallel 4M resistors or 15.625 k.

7. Specifications are guaranteed by design and are characterized and correlated using statistical process methods.

(Note 7) T

is connected to pin GD and is equal to 0.25nF.

SD(Hy)

-1.69-V

-1.25-V

-200-mV

-80-A

-1.25-V

-135-ºC

-14-ºC

DS961F1 5

+ 11 hidden pages