Cirrus Logic CS1613A User Manual

CS1610A/11A

T1

D8

C9

LED+

LED-

D7

R12

NTC

Z2C8

R11

D6

R8

R13

R

FBGA IN

Q4

CS1610A/11A

IAC

SOURCE

FBGAIN

FBAUX

BSTOUT

GNDSGND

13

16

5

4

IPK

CLAMP

GD

FBSENSE

eOTP

15

8

9

10

12

11

1

14

2

BSTAUX

VDD

R10

3

R

S

C

NTC

R9

R

IPK

BR1 BR1

AC

Mains

C7

L1

D2

BR1 BR 1

D5

L2

C2

R4

R6

R7

Q2

Z1 C4

C3

R2

D1

R1

C1

R5

C6

D4

D3

C5

Q1

R3

V

rect

V

BST

Q3

CS1612A/13A

TRIAC Dimmable LED Driver IC

Features & Description

• Best-in-class Dimmer Compatibility

- Leading-edge (TRIAC) Dimmers

- Trailing-edge Dimmers

- Center-cut Dimmers

- Digital Dimmers (with Integrated Power Supply)

• Up to 90% Efficiency

• Optimized for 25W Input Power

• Flicker-free Dimming

• 0% Minimum Dimming Level

• Quasi-resonant Second Stage with Constant-current Output

- Flyback and Buck

• Fast Startup

• Tight LED Current Regulation: Better than ± 5%

• Primary-side Regulation (PSR)

• >0.9 Power Factor

• IEC-61000-3-2 Compliant

• NEMA SSL6 Compatible

•Soft Start

• Protections:

- Output Open/Short

- Current-sense Resistor Open/Short

- External Overtemperature Using NTC

Overview

The CS1610A/1A/12A/13A is a digital control IC engineered to
deliver a high-efficiency, cost-effective, flicker-free, phase­dimmable, solid-state lighting (SSL) solution for the incandescent
lamp-replacement market. The CS1610A/11A is designed to
control a quasi-resonant flyback topology. The CS1612A/13A is
designed to control a buck topology. The CS1610A/12A and
CS1611A/13A are designed for 120VAC and 230VAC line
voltage applications, respectively.

The CS1610A/ 11A/12A /13A integrates a critical conduction
mode (CRM) boost converter that provides power factor
correction and dimmer compatibility with a constant output
current, quasi-resonant second stage. An adaptive dimmer
compatibility algorithm controls the boost stage and dimmer
compatibility operation mode to enable flicker-free operation to
<2 % output current with leading-edge, trailing-edge, center-cut,
and digital dimmers (dimmers with an integrated power supply).

Applications

• Dimmable Retrofit LED Lamps

• Dimmable LED Luminaries

• Offline LED Drivers

• Commercial Lighting

Ordering Information

See page 16.

Cirrus Logic, Inc.

http://www.cirrus.com

JUN’14

DS976F1

Copyright  Cirrus Logic, Inc. 2014

(All Rights Reserved)

1. INTRODUCTION

V

Z

POR

+

-

Volt age

Regul ator

14

VDD

11

FBSENSE

+

-

15

FBAUX

+

-

13

GD

2

IAC

DAC

+

-

Peak

Control

Second Stage ZC D

+

-

Output Open

12

GND

OLP

+

-

16

BSTOUT

MUX

OCP

+

-

1

BSTAUX

Boost ZC D

3

CLAMP

V

ST(th)

V

STP(th)

V

OCP(th)

V

FBZC D(th)

V

OVP (th)

V

OLP(th)

V

FBZC D(th)

V

Pk_Max(th)

9

4

SGND

5

SOURCE

+

-

+

-

I

CONNECT

V

CONNECT(th)

V

SOURCE(th )

10

FBGAIN

8

IPK

eOTP

15k

ADC

MUX

15k

I

ref

t

FBZC D

I

CLAMP

t

BSTZCD

I

SOURCE

VDD

VDD

Blank

3

Figure 1. CS1610A/11A/12A/13A Block Diagram

CS1610A/11A

CS1612A/13A

A typical schematic using the CS1610A /11A for flyback
applications is shown on the previous page.

Startup current is provided from a patent-pending, external,
high-voltage source-follower network. In addition to providing
startup current, this unique topology is integral in providing
compatibility with digital dimmers by ensuring VDD power is
always available to the IC. During steady-state operation, an
auxiliary winding on the boost inductor back-biases the
source-follower circuit and provides steady-state operating
current to the IC to improve system efficiency.

The rectified input voltage is sensed as a current into pin IAC
and is used to control the adaptive dimmer compatibility
algorithm and extract the phase of the input voltage for output
dimming control. During steady-state operation, the external
high-voltage, source-follower circuit is source-switched in
critical conduction mode (CRM) to boost the input voltage.
This allows the boost stage to maintain good power factor,
provides dimmer compatibility, reduces bulk capacitor ripple
current, and provides a regulated input voltage to the second
stage.

2 DS976F1

The output voltage of the CRM boost is sensed by the current
into the boost output voltage sense pin BSTOUT. The quasi­resonant second stage is implemented with peak-current
mode primary-side control, which eliminates the need for
additional components to provide feedback from the
secondary and reduces system cost and complexity.

Voltage across an external user-selected resistor is sensed
through pin FBSENSE to control the peak current through the
second stage inductor. Leading-edge and trailing-edge
blanking on pin FBSENSE prevents false triggering.

Pin FBAUX is used to sense the second stage inductor
demagnetization to ensure quasi-resonant switching of the
output stage.

When an external negative temperature coefficient (NTC)
thermistor is connected to the eOTP pin, the
CS1610A/11A/12A/13A monitors the system temperature,
allowing the controller to reduce the output current of the
system. If the temperature reaches a designated high set
point, the IC is shutdown and stops switching.

2. PIN DESCRIPTION

No Connect

Source Switch

Source Ground

Boost Zero-current Detect

Rectifier Voltage Sense

Boost Peak Current

NC

NCNo Connect

SOURCE

SGND

BSTAUX

eOTP External Overtemperature Protection

FBSENSE Second Stage Current Sense

GND Ground

GD Gate Driver

VDD

IC Supply Voltage

FBAUX

Second Stage Zero-current Detect

BSTOUT

Boost Output Voltage Sense

IAC

CLAMP

Voltage Clamp Current Source

16-lead SOICN

IPK

FBGAIN Second Stage Gain

7

6

5

4

3

2

1

10

11

12

13

14

15

16

8

9

Figure 2. CS1610A/11A/12A/13A Pin Assignments

CS1610A/11A

CS1612A/13A

Pin Name

BST AUX

IAC

CLAMP

SGND

SOURCE

NC
NC

IPK

FBGAIN

eOTP

FBSENSE

GND

GD

VDD

Pin # I/O

1IN

2IN

3OUT

4PWR

5IN

6IN

7IN

8IN

9IN

10 IN

11 IN

12 PWR

13 OUT

14 PWR

Description

Boost Zero-current Detect — Boost Inductor demagnetization sensing input for

zero-current detection (ZCD) information. The pin is connected to the PFC boost
inductor auxiliary winding through an external resistor divider.

Rectifier Voltage Sense — A current proportional to the rectified line voltage is fed

into this pin. The current is measured with an A/D converter.

Voltage Clamp Current Source — Connect to a voltage clamp circuit on the output

of the boost stage.

Source Ground — Common reference current return for the SOURCE pin.
Source Switch — Connected to the source of the boost stage external high-voltage

FET.

No Connect — Connect this pin to VDD using a pull-up resistor.
No Connect — Connect this pin to VDD using a pull-up resistor.
Boost Peak Current — Connect a resistor to this pin to set the peak current of the

boost circuit.

Second Stage Gain — Connect a resistor to this pin to set the switching frequency

gain for the second stage.

External Overtemperature Protection — Connect an external NTC thermistor to

this pin, allowing the internal A/D converter to sample the change to NTC resistance.

Second Stage Current Sense — The current flowing in the second stage FET is

sensed across a resistor. The resulting voltage is applied to this pin and digitized for
use by the second stage computational logic to determine the FET's duty cycle.

Ground — Common reference. Current return for both the input signal portion of the

IC and the gate driver.

Gate Driver — Gate drive for the second stage power FET.
IC Supply Voltage —

Connect a storage capacitor to this pin to serve as a reservoir for

operating current for the device, including the gate drive current to the power transistor

.

FBAUX

BSTOUT

DS976F1 3

Second Stage Zero-current Detect — Second stage inductor sensing input. The

15 IN

pin is connected to the second stage inductor’s auxiliary winding through an external
resistor divider.

16 IN

Boost Output Voltage Sense — A current proportional to the boost output is fed

into this pin. The current is measured with an A/D converter.

CS1610A/11A

CS1612A/13A

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 E lectrical Characteristics

Typical characteristics conditions:

=25°C, VDD=12V, GND=0V

•T

A

• All voltages are measured with respect to GND.

• Unless otherwise specified, all currents are positive
when flowing into the IC.

Parameter Condition Symbol Min Typ Max Unit

VDD Supply Voltage

Operating Range

Turn-on Threshold Voltage

Turn-off Threshold Voltage (UVLO)

Zener Voltage

(Note 1)

After Turn-on

VDD Increasing

VDD Decreasing

I

=20mA

DD

VDD Supply Current

Startup Supply Current

Operating Supply Current

(Note 2)

VDD<V

C

= 0.25nF, Fsw70 kHz

L

Reference

Reference Current

V

CS1610A/12A
CS1611A/13A

= 200 V

BST

V

= 400 V

BST

Boost

Maximum Switching Frequency f

Clamp Current I

Dimmer Attach Peak Current

CS1610A/12A
CS1611A/13A

108  V
207 V

line

line

DCM Delay in No-dimmer Mode

CS1610A
CS1611A/12A /13A

Boost Zero-Current Detect

BSTZCD Threshold V

BSTZCD Blanking t

ZCD Sink Current

BSTAUX Upper Voltage

(Note 3) I

I

=1mA

ZCD

Boost Protection

Boost Overvoltage Protection (BOP)

CS1610A/12A
CS1611A/13A

108  V
207 V

line

line

Clamp Turn On

CS1610A/12A
CS1611A/13A

108  V
207 V

line

line

Second Stage Current Sense

Sense Resistor Short Threshold V

Peak Control Threshold V

Leading-edge Blanking t

Delay to Output --100ns

Minimum/Maximum characteristics conditions:

= -40°C to +125 ° C, VDD= 11V to 17V, GND = 0 V

•T

J

ST(th)

V

V

ST(th)

V

STP(th)

V

I

DD

Z

ST

11 - 17 V

-9.0-V

-7.7-V

18.5 - 19.8 V

--650A

-4.0-mA

I

ref

-

-

BST(Max)

CLAMP

132
253

--200kHz

--3.7-mA

-

-

-

-

BSTZCD(th)

BSTZCD

ZCD

-200-mV

-3.5-s

-2 - - mA

-VDD+0.6 - V

132
253

132
253

V

BOP(th)

OLP(th)

Pk_Max(th)

LEB

-

-

-

-

-200-mV

-1.4-V

-550-ns

133
133

590
508

0.0

6.4

162
148

147
142

-

-

-

-

-

-

-

-

-

-

A
A

mA
mA

s
s

A
A

A
A

4 DS976F1

CS1610A/11A

CS1612A/13A

Parameter Condition Symbol Min Typ Max Unit

Second Stage Zero-current Detect

FBZCD Threshold V

FBZCD(th)

FBZCD Blanking

CS1610A/12A

t

FBZCB

CS1611A/13A

ZCD Sink Current

FBAUX Upper Voltage

(Note 3) I

I

=1mA

ZCD

ZCD

Second Stage Pulse Width Modulator

Minimum On Time - 0.55 - s

Maximum On Time

CS1610A/11A/13A
CS1612A

Minimum Switching Frequency t

Maximum Switching Frequency

(Note 4) t

FB(Min)

FB(Max)

Second Stage Gate Driver

Output Source Resistance Z

Output Sink Resistance Z

Rise Time

Fall Time

CL=0.25nF

CL=0.25nF

OUT

OUT

Second Stage Protection

Overcurrent Protection (OCP) V

Overvoltage Protection (OVP) V

Open Loop Protection (OLP) V

OCP(th)

OVP(th)

OLP(th)

External Overtemperature Protection (eOTP), Boost Peak Current, Second Stage Frequency Gain

Pull-up Current Source – Maximum I

Conductance Accuracy

Conductance Offset

(Note 5) --±5

(Note 5) -±250-nS

Current Source Voltage Threshold V

CONNECT

CONNECT(th)

Internal Overtemperature Protection (iOTP)

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

Notes: 1. The CS1610A/11A /12A/13A has an internal shunt regulator that limits the voltage on the VDD pin. VZ, the shunt regulation

voltage, is defined in the VDD Supply Voltage section on page 4.

2. For test purposes, load capacitance C

3. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased
does not exceed specification.

4. Switching period (T1

5. The conductance is specified in Siemens (S or 1/). Each LSB of the internal ADC corresponds to 250nS or one parallel 4 M
resistor. Full scale corresponds to 256 parallel 4M resistors or 15.625k.

6. Specifications are guaranteed by design and are characterized and correlated using statistical process methods.

(Note 6) T

(Note 6) T

is connected to pin GD and is equal to 0.25 nF.

L

SD

SD(Hy)

T2)  5 s. Period T1 and T2 are defined in the Control Parameters section on page 12.

-200-mV

-

-

2

2.8

-

-

-2 - - mA

-VDD+0.6 - V

-

-

8.8

12.0

-

-

-625-Hz

-200-kHz

-20.3-

-9.4-

--30ns

--20ns

-1.69-V

-1.25-V

-200-mV

-80-A

-1.25-V

-143-ºC

-12-ºC

s
s

s
s

DS976F1 5

CS1610A/11A

CS1612A/13A

3.2 Thermal Resistance

Symbol Parameter Value Unit





Junction-to-Ambient Thermal Impedance 2 Layer PCB

JA

Junction-to-Case Thermal Impedance 2 Layer PCB

JC

4 Layer PCB

4 Layer PCB

3.3 Absolute Maximum Ratings

Characteristics conditions:

All voltages are measured with respect to GND.

Pin Symbol Parameter Value Unit

14 V

1, 2, 5, 8, 9,
10,11,15,16

1, 2, 8, 9, 10,

11, 15, 16

13 V

13 I

5I

3I

-P

-T

-T

All Pins ESD

SOURCE

CLAMP

IC Supply Voltage 18.5 V

DD

Analog Input Maximum Voltage -0.5 to (V

Analog Input Maximum Current 5 mA

Gate Drive Output Voltage -0.3 to (VDD+0.3) V

GD

Gate Drive Output Current -1.0 / +0.5 A

GD

Current into Pin 1.1 A

Clamp Output Current 5 mA

Total Power Dissipation 400 mW

D

Junction Temperature Operating Range (Note 7) -40 to +125 °C

J

Storage Temperature Range -65 to +150 °C

Stg

Electrostatic Discharge Capability Human Body Model

Charged Device Model

135
129

50
43

DD

2000

500

°C/W
°C/W

°C/W
°C/W

+0.5) V

V
V

Note: 7. Long-term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at

the rate of 50 mW /°C for variation over temperature.

WARNING:

Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

6 DS976F1