Cirrus Logic CS1613 User Manual

CS1610/11

LED+

LED-

R12

NTC

Z2C8

R11

R13

FBGA IN

CS1610/11

IAC

SOURCE

FBGAIN

FBAUX

BSTOUT

GNDSGND

IPK

CLAMP

FBSENSE

eOTP

BSTAUX

VDD

R10

NTC

IPK

BR1 BR1

Mains

BR1 BR 1

Z1 C4

rect

BST

CS1612/13

TRIAC Dimmable LED Driver IC

Features & Description

• Best-in-class Dimmer Compatibility

- Leading-edge (TRIAC) Dimmers

- Trailing-edge Dimmers

- Digital Dimmers (with Integrated Power Supply)

• Up to 90% Efficiency

• Optimized for 25W Input Power

• Flicker-free Dimming

• 0% Minimum Dimming Level

• Quasi-resonant Second Stage with Constant-current Output

- Flyback and Buck

• Fast Startup

• Tight LED Current Regulation: Better than ± 5%

• Primary-side Regulation (PSR)

• >0.9 Power Factor

• IEC-61000-3-2 Compliant

•Soft Start

• Protections:

- Output Open/Short

- Current-sense Resistor Open/ Short

- External Overtemperature Using NTC

Overview

The CS1610/11/12 /13 is a digital control IC engineered to deliver a high-efficiency, cost-effective, flicker-free, phase-dimmable, solid-state lighting (SSL) solution for the incandescent lamp replacement market. The CS1610/11 is designed to control a quasi-resonant flyback topology. The CS1612/13 is designed to control a buck topology. The CS1610/12 and CS1611 /13 are designed for 120VAC and 230VAC line voltage applications, respectively.

The CS1610/11/12 /13 integrates a critical conduction mode (CRM) boost converter that provides power factor correction and dimmer compatibility with a constant output current, quasiresonant second stage. An adaptive dimmer compatibility algorithm controls the boost stage and dimmer compatibility operation mode to enable flicker-free operation to < 2% output current with leading-edge, trailing-edge, and digital dimmers (dimmers with an integrated power supply).

Applications & Description

• Dimmable Retrofit LED Lamps

• Dimmable LED Luminaries

• Offline LED Drivers

• Commercial Lighting

Ordering Information

See page 15.

Cirrus Logic, Inc.

http://www.cirrus.com

MAY’13

DS929F6

1. INTRODUCTION

POR

Volt age

Regul ator

VDD

FBSENSE

FBAUX

IAC

DAC

Peak

Cont rol

Second St age ZCD

Output O pen

GND

OLP

BSTOUT

MUX

OCP

Boost ZC D

CLAMP

ST(th)

STP(th)

OCP(th)

FBZC D(th)

OVP(th)

OLP(th)

Pk_Max(th)

SGND

SOURCE

CONNECT

CONNECT(th)

SOURCE(th)

FBGAIN

IPK

eOTP

15 k

ADC

MUX

15 k

ref

FBZC D

CLAMP

BS TZCD

SOURCE

BSTAUX

FBZC D(th )

VDD

Blank

Figure 1. CS1610/11/12/13 Block Diagram

CS1610/11/12/13

A typical schematic using the CS1610/11 for flyback applications is shown on the previous page.

Startup current is provided from a patent-pending, external, high-voltage, source-follower network. In addition to providing startup current, this unique topology is integral in providing compatibility with digital dimmers by ensuring V always available to the IC. During steady-state operation, an auxiliary winding on the boost inductor back-biases the source-follower circuit and provides steady-state operating

power is

current to the IC to improve system efficiency.

The rectified input voltage is sensed as a current into pin IAC and is used to control the adaptive dimmer compatibility algorithm and extract the phase of the input voltage for output dimming control. During steady-state operation, the external high-voltage, source-follower circuit is source-switched in critical conduction mode (CRM) to boost the input voltage. This allows the boost stage to maintain good power factor, provide dimmer compatibility, reduce bulk capacitor ripple current, and provide a regulated input voltage to the second stage.

2 DS929F6

The output voltage of the CRM boost is sensed by the current into the boost output voltage sense pin BSTOUT. The quasiresonant second stage is implemented with peak-current mode primary-side control, which eliminates the need for additional components to provide feedback from the secondary and reduces system cost and complexity.

Voltage across an external user-selected resistor is sensed through pin FBSENSE to control the peak current through the second stage inductor. Leading-edge and trailing-edge blanking on pin FBSENSE prevents false triggering.

Pin FBAUX is used to sense the second stage inductor demagnetization to ensure quasi-resonant switching of the output stage.

When an external negative temperature coefficient (NTC) thermistor is connected to the eOTP pin, the CS1610/11/12/13 monitors the system temperature, allowing the controller to reduce the output current of the system. If the temperature reaches a designated high set point, the IC is shut down and stops switching.

2. PIN DESCRIPTION

No Connect

Source Switch

Source Ground

Boost Zero-current Detect

Rectifier Voltage Sense

Boost Peak Current

NCNo Connect

SOURCE

SGND

BSTAUX

eOTP External Overtemperature Protection

FBSENSE Second Stage Current Sense

GND Ground

GD Gate Driver

VDD

IC Supply Voltage

FBAUX

Second Stage Zero-current Detect

BSTOUT

Boost Output Voltage Sense

IAC

CLAMP

Voltage Clamp Current Source

16-lead SOICN

IPK

FBGAIN Second Stage Gain

Figure 2. CS1610/11/12/13 Pin Assignments

CS1610/11/12/13

Pin Name

BST AUX

IAC

CLAMP

SGND

SOURCE

NC NC

IPK

FBGAIN

eOTP

FBSENSE

GND

VDD

Pin # I/O

1IN

2IN

3OUT

4PWR

5IN

6IN

7IN

8IN

9IN

10 IN

11 IN

12 PWR

13 OUT

14 PWR

Description

Boost Zero-current Detect — Boost inductor demagnetization sensing input for

zero-current detection (ZCD) information. The pin is connected to the PFC boost inductor auxiliary winding through an external resistor divider.

Rectifier Voltage Sense — A current proportional to the rectified line voltage is fed

into this pin. The current is measured with an A/D converter.

Voltage Clamp Current Source — Connect to a voltage clamp circuit on the output

of the boost stage.

Source Ground — Common reference current return for the SOURCE pin. Source Switch — Connected to the source of the boost stage external high-voltage

FET.

No Connect — Connect this pin to VDD using a pull-up resistor. No Connect — Connect this pin to VDD using a pull-up resistor. Boost Peak Current — Connect a resistor to this pin to set the peak current of the

boost circuit.

Second Stage Gain — Connect a resistor to this pin to set the switching frequency

gain for the second stage.

External Overtemperature Protection — Connect an external NTC thermistor to

this pin, allowing the internal A/D converter to sample the change to NTC resistance.

Second Stage Current Sense — The current flowing in the second stage FET is

sensed across a resistor. The resulting voltage is applied to this pin and digitized for use by the second stage computational logic to determine the FET's duty cycle.

Ground — Common reference. Current return for both the input signal portion of the

IC and the gate driver.

Gate Driver — Gate drive for the second stage power FET. IC Supply Voltage —

Connect a storage capacitor to this pin to serve as a reservoir for

operating current for the device, including the gate drive current to the power transistor

FBAUX

BSTOUT

DS929F6 3

15 IN

16 IN

Second Stage Zero-current Detect — Second stage inductor sensing input. The

pin is connected to the second stage inductor’s auxiliary winding through an external resistor divider.

Boost Output Voltage Sense — A current proportional to the boost output is fed

into this pin. The current is measured with an A/D converter.

CS1610/11/12/13

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 E lectrical Characteristics

Typical characteristics conditions:

•TA=25°C, VDD=12V, GND=0V

• All voltages are measured with respect to GND.

• Unless otherwise specified, all currents are positive when flowing into the IC.

Parameter Condition Symbol Min Typ Max Unit

VDD Supply Voltage

Operating Range

Turn-on Threshold Voltage

Turn-off Threshold Voltage (UVLO)

Zener Voltage

(Note 1)

After Turn-on

VDD Increasing

VDD Decreasing

=20mA

VDD Supply Current

Startup Supply Current

Operating Supply Current

(Note 5)

VDD<V

= 0.25nF, Fsw70 kHz

Reference

Reference Current

CS1610/12 CS1611/13

= 200 V

BST

= 400 V

BST

Boost

Maximum Switching Frequency f

Clamp Current I

Dimmer Attach Peak Current

CS1610/12 CS1611/13

108  V 207 V

line

DCM Delay in No-dimmer Mode

CS1610 CS1611/12/13

Boost Zero-current Detect

BSTZCD Threshold V

BSTZCD Blanking t

ZCD Sink Current

BSTAUX Upper Voltage

(Note 2) I

=1mA

ZCD

Boost Protection

Boost Overvoltage Protection (BOP)

CS1610/12 CS1611/13

108  V 207 V

line

Clamp Turn On

CS1610/12 CS1611/13

108  V 207 V

line

Second Stage Current Sense

Sense Resistor Short Threshold V

Peak Control Threshold V

Leading-edge Blanking t

Delay to Output --100ns

Minimum/Maximum characteristics conditions:

•TJ= -40°C to +125 ° C, VDD= 11V to 17V, GND = 0 V

ST(th)

STP(th)

11 - 17 V

-8.5-V

-7.5-V

18.5 - 19.8 V

--200A

-4.5-mA

ref

BST(Max)

CLAMP

132 253

--200kHz

--3.7-mA

BSTZCD(th)

BSTZCD

ZCD

-200-mV

-3.5-s

-2 - - mA

-VDD+0.6 - V

132 253

BOP(th)

OLP(th)

Pk_Max(th)

LEB

-200-mV

-1.4-V

-550-ns

133 133

590 508

0.0

6.4

162 148

147 143

A A

mA mA

s s

A A

4 DS929F6

CS1610/11/12/13

GD OUT

GND

VDD

Buffer

+15V

-15V

0.25 nF

Parameter Condition Symbol Min Typ Max Unit

Second Stage Zero-current Detect

FBZCD Threshold V

FBZCD(th)

FBZCD Blanking

CS1610/12

FBZCB

CS1611/13

ZCD Sink Current

FBAUX Upper Voltage

(Note 2) I

=1mA

ZCD

Second Stage Pulse Width Modulator

Minimum On Time - 0.55 - s

Maximum On Time

CS1610/11/13 CS1612

Minimum Switching Frequency t

Maximum Switching Frequency t

FB(Min)

FB(Max)

Second Stage Gate Driver

Output Source Resistance

Output Sink Resistance

Rise Time

Fall Time

(Note 5)

VDD=12V

=0.25nF

OUT

Second Stage Protection

Overcurrent Protection (OCP) V

Overvoltage Protection (OVP) V

Open Loop Protection (OLP) V

OCP(th)

OVP(th)

OLP(th)

External Overtemperature Protection (eOTP), Boost Peak Current, Second Stage Frequency Gain

Pull-up Current Source – Maximum I

Conductance Accuracy

Conductance Offset

(Note 3) --±5

(Note 3) -±250-nS

Current Source Voltage Threshold V

CONNECT

CONNECT(th)

Internal Overtemperature Protection (iOTP)

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

Notes: 1. The CS1610/11 /12/13 has an internal shunt regulator that limits the voltage on the VDD pin. Shunt regulation voltage VZ is

defined in the VDD Supply Voltage section on page 4.

2. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased does not exceed specification.

3. The conductance is specified in Siemens (S or 1/). Each LSB of the internal ADC corresponds to 250nS or one parallel 4 M resistor. Full scale corresponds to 256 parallel 4M resistors or 15.625k.

4. Specifications are guaranteed by design and are characterized and correlated using statistical process methods.

5. For test purposes, load capacitance C

(Note 4) T

is 0.25nF and is connected as shown in the following diagram.

SD(Hy)

-200-mV

2.8

s s

-2 - - mA

-VDD+0.6 - V

8.8

12.0

s s

-625-Hz

-200-kHz

-24-

-11-

--30ns

--20ns

-1.69-V

-1.25-V

-200-mV

-80-A

-1.25-V

-135-ºC

-14-ºC

DS929F6 5

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