Cirrus Logic CS1613 User Manual

CS1610/11

T1

D8

C9

LED+

LED-

D7

R12

NTC

Z2C8

R11

D6

R8

R13

R

FBGA IN

Q4

CS1610/11

IAC

SOURCE

FBGAIN

FBAUX

BSTOUT

GNDSGND

13

16

5

4

IPK

CLAMP

GD

FBSENSE

eOTP

15

8

9

10

12

11

1

14

2

BSTAUX

VDD

R10

3

R

S

C

NTC

R9

R

IPK

BR1 BR1

AC

Mains

L1

D2

BR1 BR 1

L2

C2

R4

R6

R7

Q2

Z1 C4

C3

R2

D1

R1

C1

R5

C6

D4

D3

C5

Q1

R3

V

rect

V

BST

D5

C7

Q3

CS1612/13

TRIAC Dimmable LED Driver IC

Features & Description

• Best-in-class Dimmer Compatibility

- Leading-edge (TRIAC) Dimmers

- Trailing-edge Dimmers

- Digital Dimmers (with Integrated Power Supply)

• Up to 90% Efficiency

• Optimized for 25W Input Power

• Flicker-free Dimming

• 0% Minimum Dimming Level

• Quasi-resonant Second Stage with Constant-current Output

- Flyback and Buck

• Fast Startup

• Tight LED Current Regulation: Better than ± 5%

• Primary-side Regulation (PSR)

• >0.9 Power Factor

• IEC-61000-3-2 Compliant

•Soft Start

• Protections:

- Output Open/Short

- Current-sense Resistor Open/ Short

- External Overtemperature Using NTC

Overview

The CS1610/11/12 /13 is a digital control IC engineered to deliver
a high-efficiency, cost-effective, flicker-free, phase-dimmable,
solid-state lighting (SSL) solution for the incandescent lamp
replacement market. The CS1610/11 is designed to control a
quasi-resonant flyback topology. The CS1612/13 is designed to
control a buck topology. The CS1610/12 and CS1611 /13 are
designed for 120VAC and 230VAC line voltage applications,
respectively.

The CS1610/11/12 /13 integrates a critical conduction mode
(CRM) boost converter that provides power factor correction and
dimmer compatibility with a constant output current, quasi­resonant second stage. An adaptive dimmer compatibility
algorithm controls the boost stage and dimmer compatibility
operation mode to enable flicker-free operation to < 2% output
current with leading-edge, trailing-edge, and digital dimmers
(dimmers with an integrated power supply).

Applications & Description

• Dimmable Retrofit LED Lamps

• Dimmable LED Luminaries

• Offline LED Drivers

• Commercial Lighting

Ordering Information

See page 15.

Cirrus Logic, Inc.

http://www.cirrus.com

MAY’13

DS929F6

Copyright  Cirrus Logic, Inc. 2013

(All Rights Reserved)

1. INTRODUCTION

V

Z

POR

+

-

Volt age

Regul ator

14

VDD

11

FBSENSE

+

-

15

FBAUX

+

-

13

GD

2

IAC

DAC

+

-

Peak

Cont rol

Second St age ZCD

+

-

Output O pen

12

GND

OLP

+

-

16

BSTOUT

MUX

OCP

Boost ZC D

3

CLAMP

V

ST(th)

V

STP(th)

V

OCP(th)

V

FBZC D(th)

V

OVP(th)

V

OLP(th)

V

Pk_Max(th)

9

4

SGND

5

SOURCE

+

-

+

-

I

CONNECT

V

CONNECT(th)

V

SOURCE(th)

10

FBGAIN

8

IPK

eOTP

15 k

ADC

MUX

15 k

I

ref

t

FBZC D

I

CLAMP

t

BS TZCD

I

SOURCE

+

-

1

BSTAUX

V

FBZC D(th )

VDD

VDD

Blank

3

Figure 1. CS1610/11/12/13 Block Diagram

CS1610/11/12/13

A typical schematic using the CS1610/11 for flyback
applications is shown on the previous page.

Startup current is provided from a patent-pending, external,
high-voltage, source-follower network. In addition to providing
startup current, this unique topology is integral in providing
compatibility with digital dimmers by ensuring V
always available to the IC. During steady-state operation, an
auxiliary winding on the boost inductor back-biases the
source-follower circuit and provides steady-state operating

DD

power is

current to the IC to improve system efficiency.

The rectified input voltage is sensed as a current into pin IAC
and is used to control the adaptive dimmer compatibility
algorithm and extract the phase of the input voltage for output
dimming control. During steady-state operation, the external
high-voltage, source-follower circuit is source-switched in
critical conduction mode (CRM) to boost the input voltage.
This allows the boost stage to maintain good power factor,
provide dimmer compatibility, reduce bulk capacitor ripple
current, and provide a regulated input voltage to the second
stage.

2 DS929F6

The output voltage of the CRM boost is sensed by the current
into the boost output voltage sense pin BSTOUT. The quasi­resonant second stage is implemented with peak-current
mode primary-side control, which eliminates the need for
additional components to provide feedback from the
secondary and reduces system cost and complexity.

Voltage across an external user-selected resistor is sensed
through pin FBSENSE to control the peak current through the
second stage inductor. Leading-edge and trailing-edge
blanking on pin FBSENSE prevents false triggering.

Pin FBAUX is used to sense the second stage inductor
demagnetization to ensure quasi-resonant switching of the
output stage.

When an external negative temperature coefficient (NTC)
thermistor is connected to the eOTP pin, the
CS1610/11/12/13 monitors the system temperature, allowing
the controller to reduce the output current of the system. If the
temperature reaches a designated high set point, the IC is
shut down and stops switching.

2. PIN DESCRIPTION

No Connect

Source Switch

Source Ground

Boost Zero-current Detect

Rectifier Voltage Sense

Boost Peak Current

NC

NCNo Connect

SOURCE

SGND

BSTAUX

eOTP External Overtemperature Protection

FBSENSE Second Stage Current Sense

GND Ground

GD Gate Driver

VDD

IC Supply Voltage

FBAUX

Second Stage Zero-current Detect

BSTOUT

Boost Output Voltage Sense

IAC

CLAMP

Voltage Clamp Current Source

16-lead SOICN

IPK

FBGAIN Second Stage Gain

7

6

5

4

3

2

1

10

11

12

13

14

15

16

8

9

Figure 2. CS1610/11/12/13 Pin Assignments

CS1610/11/12/13

Pin Name

BST AUX

IAC

CLAMP

SGND

SOURCE

NC
NC

IPK

FBGAIN

eOTP

FBSENSE

GND

GD

VDD

Pin # I/O

1IN

2IN

3OUT

4PWR

5IN

6IN

7IN

8IN

9IN

10 IN

11 IN

12 PWR

13 OUT

14 PWR

Description

Boost Zero-current Detect — Boost inductor demagnetization sensing input for

zero-current detection (ZCD) information. The pin is connected to the PFC boost
inductor auxiliary winding through an external resistor divider.

Rectifier Voltage Sense — A current proportional to the rectified line voltage is fed

into this pin. The current is measured with an A/D converter.

Voltage Clamp Current Source — Connect to a voltage clamp circuit on the output

of the boost stage.

Source Ground — Common reference current return for the SOURCE pin.
Source Switch — Connected to the source of the boost stage external high-voltage

FET.

No Connect — Connect this pin to VDD using a pull-up resistor.
No Connect — Connect this pin to VDD using a pull-up resistor.
Boost Peak Current — Connect a resistor to this pin to set the peak current of the

boost circuit.

Second Stage Gain — Connect a resistor to this pin to set the switching frequency

gain for the second stage.

External Overtemperature Protection — Connect an external NTC thermistor to

this pin, allowing the internal A/D converter to sample the change to NTC resistance.

Second Stage Current Sense — The current flowing in the second stage FET is

sensed across a resistor. The resulting voltage is applied to this pin and digitized for
use by the second stage computational logic to determine the FET's duty cycle.

Ground — Common reference. Current return for both the input signal portion of the

IC and the gate driver.

Gate Driver — Gate drive for the second stage power FET.
IC Supply Voltage —

Connect a storage capacitor to this pin to serve as a reservoir for

operating current for the device, including the gate drive current to the power transistor

.

FBAUX

BSTOUT

DS929F6 3

15 IN

16 IN

Second Stage Zero-current Detect — Second stage inductor sensing input. The

pin is connected to the second stage inductor’s auxiliary winding through an external
resistor divider.

Boost Output Voltage Sense — A current proportional to the boost output is fed

into this pin. The current is measured with an A/D converter.

CS1610/11/12/13

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 E lectrical Characteristics

Typical characteristics conditions:

•TA=25°C, VDD=12V, GND=0V

• All voltages are measured with respect to GND.

• Unless otherwise specified, all currents are positive
when flowing into the IC.

Parameter Condition Symbol Min Typ Max Unit

VDD Supply Voltage

Operating Range

Turn-on Threshold Voltage

Turn-off Threshold Voltage (UVLO)

Zener Voltage

(Note 1)

After Turn-on

VDD Increasing

VDD Decreasing

I

=20mA

DD

VDD Supply Current

Startup Supply Current

Operating Supply Current

(Note 5)

VDD<V

C

= 0.25nF, Fsw70 kHz

L

Reference

Reference Current

V

CS1610/12
CS1611/13

= 200 V

BST

V

= 400 V

BST

Boost

Maximum Switching Frequency f

Clamp Current I

Dimmer Attach Peak Current

CS1610/12
CS1611/13

108  V
207 V

line

line

DCM Delay in No-dimmer Mode

CS1610
CS1611/12/13

Boost Zero-current Detect

BSTZCD Threshold V

BSTZCD Blanking t

ZCD Sink Current

BSTAUX Upper Voltage

(Note 2) I

I

=1mA

ZCD

Boost Protection

Boost Overvoltage Protection (BOP)

CS1610/12
CS1611/13

108  V
207 V

line

line

Clamp Turn On

CS1610/12
CS1611/13

108  V
207 V

line

line

Second Stage Current Sense

Sense Resistor Short Threshold V

Peak Control Threshold V

Leading-edge Blanking t

Delay to Output --100ns

Minimum/Maximum characteristics conditions:

•TJ= -40°C to +125 ° C, VDD= 11V to 17V, GND = 0 V

ST(th)

V

V

ST(th)

V

STP(th)

V

I

DD

Z

ST

11 - 17 V

-8.5-V

-7.5-V

18.5 - 19.8 V

--200A

-4.5-mA

I

ref

-

-

BST(Max)

CLAMP

132
253

--200kHz

--3.7-mA

-

-

-

-

BSTZCD(th)

BSTZCD

ZCD

-200-mV

-3.5-s

-2 - - mA

-VDD+0.6 - V

132
253

132
253

V

BOP(th)

OLP(th)

Pk_Max(th)

LEB

-

-

-

-

-200-mV

-1.4-V

-550-ns

133
133

590
508

0.0

6.4

162
148

147
143

-

-

-

-

-

-

-

-

-

-

A
A

mA
mA

s
s

A
A

A
A

4 DS929F6

CS1610/11/12/13

GD OUT

GD

GND

VDD

Buffer

S

1

R

1

R

2

R

3

TP

+15V

-15V

S

2

V

DD

C

L

0.25 nF

Parameter Condition Symbol Min Typ Max Unit

Second Stage Zero-current Detect

FBZCD Threshold V

FBZCD(th)

FBZCD Blanking

CS1610/12

t

FBZCB

CS1611/13

ZCD Sink Current

FBAUX Upper Voltage

(Note 2) I

I

=1mA

ZCD

ZCD

Second Stage Pulse Width Modulator

Minimum On Time - 0.55 - s

Maximum On Time

CS1610/11/13
CS1612

Minimum Switching Frequency t

Maximum Switching Frequency t

FB(Min)

FB(Max)

Second Stage Gate Driver

Output Source Resistance

Output Sink Resistance

Rise Time

Fall Time

(Note 5)

(Note 5)

VDD=12V

VDD=12V

C

=0.25nF

L

=0.25nF

C

L

Z

Z

OUT

OUT

Second Stage Protection

Overcurrent Protection (OCP) V

Overvoltage Protection (OVP) V

Open Loop Protection (OLP) V

OCP(th)

OVP(th)

OLP(th)

External Overtemperature Protection (eOTP), Boost Peak Current, Second Stage Frequency Gain

Pull-up Current Source – Maximum I

Conductance Accuracy

Conductance Offset

(Note 3) --±5

(Note 3) -±250-nS

Current Source Voltage Threshold V

CONNECT

CONNECT(th)

Internal Overtemperature Protection (iOTP)

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

Notes: 1. The CS1610/11 /12/13 has an internal shunt regulator that limits the voltage on the VDD pin. Shunt regulation voltage VZ is

defined in the VDD Supply Voltage section on page 4.

2. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased
does not exceed specification.

3. The conductance is specified in Siemens (S or 1/). Each LSB of the internal ADC corresponds to 250nS or one parallel 4 M
resistor. Full scale corresponds to 256 parallel 4M resistors or 15.625k.

4. Specifications are guaranteed by design and are characterized and correlated using statistical process methods.

5. For test purposes, load capacitance C

(Note 4) T

(Note 4) T

is 0.25nF and is connected as shown in the following diagram.

L

SD

SD(Hy)

-200-mV

-

-

2

2.8

-

-

s
s

-2 - - mA

-VDD+0.6 - V

-

-

8.8

12.0

-

-

s
s

-625-Hz

-200-kHz

-24-

-11-

--30ns

--20ns

-1.69-V

-1.25-V

-200-mV

-80-A

-1.25-V

-135-ºC

-14-ºC

DS929F6 5

CS1610/11/12/13

3.2 Thermal Resistance

Symbol Parameter Value Unit





Junction-to-Ambient Thermal Impedance 2 Layer PCB

JA

Junction-to-Case Thermal Impedance 2 Layer PCB

JC

4 Layer PCB

4 Layer PCB

3.3 Absolute Maximum Ratings

Characteristics conditions:

All voltages are measured with respect to GND.

Pin Symbol Parameter Value Unit

14 V

1, 2, 5, 8, 9,
10,11,15,16

1, 2, 8, 9, 10,

11, 15, 16

13 V

13 I

5I

3I

SOURCE

CLAMP

-P

-T

-T

All Pins ESD

IC Supply Voltage 18.5 V

DD

Analog Input Maximum Voltage -0.5 to (V

Analog Input Maximum Current 5 mA

Gate Drive Output Voltage -0.3 to (VDD+0.3) V

GD

Gate Drive Output Current -1.0 / +0.5 A

GD

Current into Pin 1.1 A

Clamp Output Current 5 mA

Total Power Dissipation 400 mW

D

Junction Temperature Operating Range (Note 6) -40 to +125 °C

J

Storage Temperature Range -65 to +150 °C

Stg

Electrostatic Discharge Capability Human Body Model

Charged Device Model

84
47

39
31

DD

2000

500

°C/W
°C/W

°C/W
°C/W

+0.5) V

V
V

Note: 6. Long-term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at

the rate of 50 mW /°C for variation over temperature.

WARNING:

Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

6 DS929F6

4. TYPICAL PERFORMANCE PLOTS

0

1

2

3

-50 0 50 100 150

UVLO Hysteresis

Temperature (ºC)

-2

0

2

4

6

8

0 2 4 6 8 10 12 14 16 18 20

I

DD

(mA)

VDD(V)

Falling Edge

7

8

9

10

-50 0 50 100 150

VDD (V)

Temperature (ºC)

Turn Oī

Turn On

18

18.5

19

19.5

20

-50 0 50 100 150

V

Z

(V)

Temperature (ºC)

0

10

20

30

40

-50 0 50 100 150

Z

OUT

(:)

Temperature (ºC)

Sink

Source

-2.0

-1.5

-1.0

-0.5

0.0

0.5

-50 0 50 100 150

Drift (%)

Temperature (ºC)

CS1610/11/12/13

Rising Edge

Figure 3. UVLO Characteristics

Figure 5. Turn On/Off Threshold Voltage vs. Temperature

Figure 4. Supply Current vs. Voltage

Figure 6. Zener Voltage vs. Temperature

Figure 7. Gate Drive Resistance vs. Temperature

DS929F6 7

Figure 8. Reference Current I

Drift vs. Temperature

ref

CS1610/11/12/13

5. GENERAL DESCRIPTION

5.1 Overview

The CS1610/11/12 /13 is a digital control IC engineered to
deliver a high-efficiency, cost-effective, flicker-free, phase­dimmable, solid-state lighting (SSL) solution for the incandescent
lamp replacement market. The CS1610/11 is designed to control
a quasi-resonant flyback topology. The CS1612 /13 is designed
to control a buck topology. The CS1610 /12 and CS1611/ 13 are
designed for 120VAC and 230VAC line voltage applications,
respectively.

The CS1610/11/12 /13 integrates a critical conduction mode
(CRM) boost converter that provides power factor correction and
dimmer compatibility with a constant output current, quasi­resonant second stage. An adaptive dimmer compatibility
algorithm controls the boost stage and dimmer compatibility
operation mode to enable flicker-free operation to <2% output
current with leading-edge, trailing-edge, and digital dimmers
(dimmers with an integrated power supply).

5.2 Startup Circuit

An external, high-voltage source-follower circuit is used to
deliver startup current to the IC. During steady-state operation,
an auxiliary winding on the boost inductor biases this circuit to
an off state to improve system efficiency, and all IC supply
current is generated from the auxiliary winding. The patent­pending technology of the external, high-voltage source­follower circuit enables system compatibility with digital
dimmers (dimmers containing an internal power supply) by
providing a continuous path for the dimmer’s power supply to
recharge during its off state. During steady-state operation,
high-voltage FET Q2 in this circuit is source-switched by a
variable internal current source on the SOURCE pin to create
the boost circuit.

0.6V is recommended for diode D5. Schottky diode D5 will limit
inrush current through the internal diode, preventing damage to
the IC.

5.3 Dimmer Switch Detection

The CS1610/ 11/12 /13 dimmer switch detection algorithm
determines if the SSL system is controlled by a regular switch,
a leading-edge dimmer, or a trailing-edge dimmer. Dimmer
switch detection is implemented using two modes: Dimmer
Learn Mode and Dimmer Validate Mode. These assist in
limiting the system power losses. Once the IC reaches UVLO
start threshold V
CS1610/ 11/12/13 is in Dimmer Learn Mode, allowing the
dimmer switch detection circuit to set the operating state of the
IC to one of three modes: No-dimmer Mode, Leading-edge
Mode, or Trailing-edge Mode.

5.3.1 Dimmer Learn Mode

In Dimmer Learn Mode, the dimmer detection circuit spends
approximately two line-cycles learning whether there is a
dimmer switch and, if present, whether it is a trailing-edge or
leading-edge dimmer. In Dimmer Learn Mode, a modified

A Schottky diode with a forward voltage less than

and begins operating, the

ST(th)

version of the leading-edge algorithm is used. The trailing-side
slope of the input line voltage is sensed to decide whether the
dimmer switch is a trailing-edge dimmer. The dimmer detection
circuit transitions to Dimmer Validate Mode once the circuit
detects a dimmer is present.

5.3.2 Dimmer Validate Mode

During normal operation, CS1610/11/12 /13 is in Dimmer
Validate Mode. This instructs the dimmer detection circuit to
periodically validate that the IC is executing the correct
algorithm for the attached dimmer. The dimmer detection
algorithm periodically verifies the IC operating state as a
protection against incorrect detection. As additional protection,
the output of the dimmer detection algorithm is low-pass filtered
to prevent noise or transient events from changing the IC’s
operating mode. The IC will return to Dimmer Learn Mode when
it has determined that the wrong algorithm is being executed.

5.3.3 No-dimmer Mode

Upon detection that the line is not phase cut with a dimmer, the
CS1610/11/12/13 operates in No-dimmer Mode, where it
provides a power factor that is in excess of 0.9. The
CS1611/12/13 accomplishes this by boosting in CRM and DCM
mode. The CS1610 boosts in CRM mode only. The peak
current is modulated to provide link regulation. The
CS1610/11/12/13 alternates between two settings of peak
current. To regulate the boost output voltage, the device uses a
peak current set by resistor R
used is determined by an internal compensation loop to
regulate the boost output voltage. The internal algorithm will
reduce the peak current of the boost stage to maintain output
voltage regulation and obtain the desired power factor.

. The time that this current is

IPK

5.3.4 Leading-edge Mode

In Leading-edge Mode, the CS1610/ 11/12 /13 regulates boost
output voltage V
To accomplish this, the CS1610/11/ 12/13 uses CCM boosting
with dimmer attach current as the initial peak current on the
initial firing event of the dimmer. After gaining control of the
incoming current, the CS1610/11/12 /13 transitions to a CRM
boost algorithm to regulate the boost output voltage. The
CS1610/ 11/12/13 periodically executes a probe event on the
incoming waveform. The information from the probe event is
beneficial to maintaining proper operation with the dimmer
circuitry.

while maintaining the dimmer phase angle.

BST

5.3.5 Trailing-edge Mode

In Trailing-edge Mode, the CS1610/ 11/12 /13 determines its
operation based on the falling edge of the input voltage
waveform. To allow the dimmer to operate properly, the
CS1610/ 11/12/13 must charge the capacitor in the dimmer on
the falling edge of the input voltage. To accomplish this, the
CS1610/ 11/12/13 always executes the boost algorithm on this
falling edge. To ensure maximum compatibility with dimmer
components, the device boosts during this falling edge event
using a peak current that must meet a minimum value. In
Trailing-edge Mode, only CRM boosting is used.

8 DS929F6

5.4 Boost Stage

P

IN max

 I

PK BSTVrms typ



2

------------------------------------------------------------ -

=

[Eq.1]

R

IPK

4M

I

PK code

-----------------------

=

[Eq.2]

V

BST

CS1610 /11/12/13

15 k

ADC

R8

R

BST

I

BSTOUT

R9

I

ref

16

BSTOU T

12

Figure 9. BSTOUT Input Pin Model

R

BST

V

BST

I

ref

------------- -

400V

133 A

----------------- -

3M==

[Eq.3]

R3

R

IA C

I

AC

IAC

V

rect

CS1610 /11/12/13

15 k

ADC

R4

2

I

ref

12

Figure 10. IAC Input Pin Model

R

IAC

R

BST

=

[Eq.4]

The high-voltage FET in the source-follower startup circuit is
source-switched by a variable current source on the SOURCE
pin to operate a boost circuit. Peak FET switching current is
set with an external resistor on pin IPK.

In No-Dimmer Mode, the boost stage begins operating when
the start threshold is reached during each rectified half line-cy­cle and is disabled at the nominal boost output voltage. The
peak FET switching current determines the percentage of the
rectified input voltage conduction angle over which the boost
stage will operate. The control algorithm adjusts the peak FET
switching current to maximize the operating time of the boost
stage, thus improving the input power factor.

When operating in Leading-edge Dimmer Mode, the boost
stage ensures the hold current requirement of the dimmer is
met from the initiation of each half-line dimmer conduction
cycle until the peak of the rectified input voltage. Trailing-edge
Dimmer Mode boost stage ensures that the trailing-edge is
exposed at the correct time with the correct current.

5.4.1 Maximum Peak Current

The maximum boost inductor peak current is set using
external resistor R
periodically by an ADC. Maximum power output is proportional
to peak current code I

where,

 = a correction term of 0.55

V

I

PK(BST)

Resistor R
See Equation 2:

= nominal operating input RMS voltage

rms(typ)

= peak current code I

is calculated using peak current code I

IPK

on pin IPK, which is sampled

IPK

PK(code)

. See Equation 1:

PK(code)

 4.1 mA

PK(code)

CS1610/11/12/13

Resistor R
output voltage. For the CS1611/13, resistor R
as shown in Equation 3:

where,

V

BST

I

ref

For 120 VAC line voltage applications (CS1610/12), nominal
boost output voltage V
By using digital loop compensation, the voltage feedback
signal does not require an external compensation network.

A current proportional to the AC input voltage is supplied to the
IC on pin IAC and is used by the boost control algorithm (see
Figure 10).

.

sets the feedback current at the nominal boost

BST

BST

= nominal boost output voltage

= internal reference current

is 200V, and resistor R

BST

is calculated

BST

is 1.5M.

5.4.2 Output BSTOUT Sense & Input IAC Sense

A current proportional to boost output voltage V
to the IC on pin BSTOUT and is used as a feedback control
signal (see Figure 9). The ADC is used to measure the
magnitude of current I
magnitude of current I
reference current I

DS929F6 9

through resistor R

BSTOUT

is then compared to an internal

BSTOUT

of 133A.

ref

is supplied

BST

BST

. The

Resistor R

sets current IAC and is defined in Equation 4:

IAC

For optimal performance, resistors R
1% or better resistors for best V

BST

IAC

and R

should use

BST

voltage accuracy.

CS1610/11/12/13

CLAMP

R10

I

CLAMP

V

BST

S1

CS1610 /11/12/ 13

VDD

3

Q3

Figure 11. CLAMP Pin Model

13

11

T1

D8

C9

LED +

LED -

D7

R12

Z2C8

R11

R13

R

FBGA IN

Q4

FBGAIN

FBAU X

GND

GD

FBSEN SE

15

912

CS1610/11

V

BST

Figure 12. Flyback Model

5.4.3 Boost Aux iliary W inding

The boost auxiliary winding is used for zero-current detection
(ZCD). The voltage on the auxiliary winding is sensed through
the BSTAUX pin of the IC. It is also used to deliver current
during steady-state operation, as mentioned in section 5.2

Startup Circuit on page 8.

5.4.4 Boost Overvoltage Protection

The CS1610/ 11/12/13 supports boost overvoltage protection
(BOP) to protect the bulk capacitor C8 (see Figure 12 on
page 10). If the boost output voltage exceeds the overvoltage
protection thresholds of 249V for a 120V system, or 448V for
a 230V system, a BOP fault signal is generated. The control
logic continuously averages this BOP fault signal, and if at any
point in time the average exceeds a set event threshold, the
boost stage is disabled. The BOP fault averaging algorithm
sets the event threshold such that the boost output voltage is
never allowed to stay above the BOP threshold for more than

1.6ms.

During a boost overvoltage protection event, the second stage
is kept enabled, and its dim input is railed to full scale. This
allows the second stage to dissipate the stored energy on bulk
capacitor C8 quickly, bringing down the boost output voltage
to a safe value. A visible flash on the LED might appear,
indicating that an overvoltage event has occurred. When the
boost output voltage drops to 195V for a 120V application or
368V for a 230V application, the boost stage is enabled, and
the system returns to normal operation.

5.5 Voltage Clamp Circuit

To keep dimmers conducting and prevent them from misfiring,
a minimum power needs to be delivered from the dimmer to
the load. This power is nominally around 2 W for 230V and
120 V TRIAC dimmers. At low dim angles (90°), this excess
power cannot be converted into light by the second output
stage due to the dim mapping at light loads. Boost stage
output voltage V
of primary-side bulk capacitor C6.

The CS1610/11/12/ 13 provides active clamp circuitry on the
CLAMP pin, as shown in Figure 11.

can rise above the safe operating voltage

BST

A PWM control loop ensures that the boost output
voltage V

does not exceed 227 V for 120VAC applications

BST

or 424 V for 230VAC applications. This control turns on the
MOSFET of the voltage clamp circuit, allowing the clamp
circuit to sink current through the load resistor, preventing
boost output voltage V

from exceeding the maximum safe

BST

voltage.

5.5.1 Clamp Overpower Protection

The CS1610/11/ 12/ 13 clamp overpower protection (COP)
control logic averages the turn-on time of the clamp circuit. If
the output of the averaging logic exceeds 49%, a COP event
is actuated, disabling the boost and second stages. The clamp
circuitry is turned off during the fault event. The turn-on time
averaging algorithm sets the COP threshold such that the
clamp circuit cannot be continuously turned on for more than

13.8ms.

5.6 Dimming Signal Extraction and the Dim Mapping Algorithm

When operating with a dimmer, the dimming signal is
extracted in the time domain and is proportional to the
conduction angle of the dimmer. A control variable is passed
to the quasi-resonant second stage to achieve 2% to 100%
output currents.

5.7 Quasi-resonant Second Stage

The second stage is a quasi-resonant current-regulated
DC-DC converter capable of flyback or buck operation,
delivering the highest possible efficiency at a constant current
while minimizing line frequency ripple. Primary-side control is
used to simplify system design and reduce system cost and
complexity.

The digital algorithm ensures monotonic dimming from 2 % to

100% of the dimming range with a linear relationship between
the dimming signal and the LED current. The flyback stage is
controlled by sensing current in the transformer primary.

10 DS929F6

CS1610/11/12/13

13

11

R

FBGA IN

FBGAIN

FBAUX

GND

GD

FBSEN SE

15

912

CS1612/13

R12

R11

R13

Q4

LED +

LED -

V

BST

C8

D8 C9

L3

Figure 13. Buck Model

TT T

critical

T1 T2+=

[Eq.5]

TT I

PK FB

T2

FB

Gain



------------------ -





[Eq.6]

TT I

PK FB

T1 T2+

FB

Gain



------------------ -





[Eq.7]

R

FBGAIN

62.5k 

FB

Gain

21–

-------------------------------------------

=

[Eq.8]

A quasi-resonant buck stage is illustrated in Figure 13. The
buck stage is controlled by measuring current in the buck
inductor and voltage on the auxiliary winding.

The FB

R

FBGAIN

input is set using resistor R

Gain

FBGAIN

must be selected to ensure that the switching
period TT is greater than the resonant switching period T
at maximum output power. See Equation 5:

where,

T

= resonant switching period at maximum power

critical

T1 = gate turn-on time

T2 = demagnetization time

The total switching period TT is computed for flyback topology
using Equation 6:

where,

 = dimming factor, proportional to the duty cycle of the

dimmer, between 0 and 1

I

= transformer primary winding current

PK(FB)

FB

= constant TT/T2; computed at full load
The digital buck algorithm ensures monotonic dimming from
2% to 100% of the dimming range with a linear relationship
between the dimming signal and the LED current.

Gain

For buck topology, the total switching period TT is computed
using Equation 7:

Quasi-resonant operation is achieved by detecting second
stage inductor demagnetization via an auxiliary winding. The
digital control algorithm rejects line-frequency ripple created
on the second stage input by the front-end boost stage,
resulting in the highest possible LED efficiency and long LED
life.

5.7.1 Auxiliary Winding Configuration

The auxiliary winding is also used for zero-current
detection (ZCD) and overvoltage protection (OVP). The
auxiliary winding is sensed through the FBAUX pin of the IC.

where,

 = dimming factor, proportional to the duty cycle of the

dimmer, between 0 and 1

I

= transformer primary winding current

PK(FB)

FB

= constant TT/ (T1 + T2); computed at full load

Gain

An appropriate value for resistor R
selected to provide the correct gain constant FB
R

is calculated using Equation 8:

FBGAIN

FBGAIN

needs to be

Gain

5.7.2 Control Parameters

The second stage control parameters assure the following:

• Line Regulation — The LED current remains constant

despite a ±10% AC line voltage variation.

• Effect of Variation in Transformer Magnetizing
Inductance — The LED current remains constant over

a ±20% variation in magnetizing inductance.

The second stage requires three inputs and generates one
key output. The FBSENSE pin is used to sense the current in
the second stage inductor. When the current reaches a certain
threshold, the gate drive turns ‘OFF’ (output on pin GD). The
sensed current and the FB

input are used to determine the

Gain

total switching period TT . The zero-current detect input on pin
FBAUX is used to determine the demagnetization period T2 .
The controller then uses the total switching period TT to
determine gate turn-on time.

The value of gain constant FB
linearity of the dimming factor versus the LED current curve

and must be selected using Application Note AN364: Design

Guide for a CS1610 and CS1611 Dimmer-compatible SSL
Circuit and AN372: Desig n Guide for a CS1612 and CS16 13
Dimmer-compatible SSL Circuit.

5.7.3 Output Open Circuit Protection

Output open circuit protection and output overvoltage
protection (OVP) is implemented by monitoring the output
voltage through the transformer auxiliary winding. If the
voltage on the FBAUX pin exceeds the threshold
voltage V
output is disabled, and the controller attempts to restart after
one second.

of 1.25V, a fault condition occurs. The IC

OVP(th)

DS929F6 11

also has a bearing on the

Gain

. Resistor

critical

. Resistor

CS1610/11/12/13

CS1610/11/12/13

+

-

I

CONNECT

V

CONNECT

(th)

Com p_O ut

eOTP

Control

eOTP

R

S

C

NTC

NTC

V

DD

10

(Optional)

Figure 14. eOTP Functional Diagram

I

CONNECT

V

CONNECT th

R

-------------------------------------

=

[Eq.9]

CODE

I

CONNECT

2

N

-------------------------- -



V

CONNECT th

R

NTCRS

+

-------------------------------------

=

[Eq.10]

CODE

2NV

CONNECT th



I

CONNECTRNTCRS

+

-------------------------------------------------------------------

=

256 1.25 V

80AR

NTCRS

+

-----------------------------------------------------------

=

4M

R

NTCRS

+

---------------------------------

=

[Eq.11]

5.7.4 Overcurrent Protection

Overcurrent protection (OCP) is implemented by monitoring
the voltage across the second stage sense resistor. If this
voltage exceeds the threshold voltage V

OCP(th)

of 1.69V, a
fault condition occurs. The IC output is disabled, and the
controller attempts to restart after one second.

5.7.5 Open Loop Protection

Both open loop protection (OLP) and protection against a
short of the second stage sense resistor are implemented by
monitoring the voltage across the sense resistor. If the voltage
on pin FBSENSE does not reach the protection threshold
voltage V

of 200mV, the IC output is disabled, and the

OLP(th)

controller attempts to restart after one second.

5.8 Overtemperature Protection

The CS1610/11/12/ 13 incorporates both internal overtemper­ature protection (iOTP) and the ability to connect an external
overtemperature sense circuit for IC protection. Typically, a
negative temperature coefficient (NTC) thermistor is used.

5.8.1 Internal Overtemperature Protection

Internal overtemperature protection (iOTP) is activated, and
switching is disabled, when the die temperature of the device
exceeds 135°C. There is a hysteresis of about 14°C before
resuming normal operation.

Current I

CONNECT

is generated from an 8-bit controlled current

source with a full-scale current of 80A. See Equation 9:

When the loop is in equilibrium, the voltage on the eOTP pin
fluctuates around threshold voltage V

CONNECT(th)

. The digital
‘CODE’ output by the ADC is used to generate
current I

CONNECT

. In normal operating mode, the I

CONNECT

current is updated once every seventh half line-cycle by a
single ±LSB step. See Equation 10:

Using Equation 10, solve for digital CODE. See Equation 11:

5.8.2 External Overtemperature Protection

The external overtemperature protection (eOTP) pin is used to
implement overtemperature protection using an external NTC
thermistor. The total resistance on the eOTP pin is converted
to an 8-bit digital ‘CODE’ (which gives an indication of the
temperature) using a digital feedback loop, which adjusts
current I

CONNECT

maintain a constant reference voltage V
Figure 14 illustrates the functional block diagram when
connecting an optional external NTC temperature sensor to
the eOTP circuit.

into the NTC and series resistor RS to

CONNECT(th)

of 1.25V.

The tracking range of this resistance ADC is approximately

15.5k to 4M. The series resistor R

is used to adjust the

S

resistance of the NTC to fall within this ADC tracking range so
that the entire 8-bit dynamic range of the ADC is well used. A
14k (±1% tolerance) series resistor is required to allow
measurements of up to 130°C to be within the eOTP tracking
range when a 100k NTC with a Beta of 4334 is used. The
eOTP tracking circuit is designed to function accurately with
external capacitance up to 470 pF. A higher 8-bit code output
reflects a lower resistance and hence a higher external
temperature.

The ADC output code is filtered to suppress noise and
compared against a reference code that corresponds to
125/130 °C. If the temperature exceeds this threshold, the
chip enters an external overtemperature state and shuts
down. This is not a latched protection state, and the ADC
keeps tracking the temperature in this state in order to clear
the fault state once the temperature drops below 110°C.

12 DS929F6

CS1610/11/12/13

Temp erature ( °C)

Current (I

LED

, Nom. )

125

95

50%

100%

0

25

Figure 15. LED Current vs. eOTP Temperature

When exiting reset, the chip enters startup and the ADC
quickly (<5ms) tracks the external temperature to check if it is
below the 110°C reference code before the boost and second
stages are powered up. If this check fails, the rest of the
system will not be initialized until the external temperature is
below 110C.

For external overtemperature protection, a second low-pass
filter with a time constant of two minutes filters the ADC output
and uses it to scale down the internal dim level of the system
(and hence LED current I

) if the temperature exceeds

LED

95 °C (see Figure 15). The large time constant for this filter
ensures that the dim scaling does not happen spontaneously
and is not noticeable (suppress spurious glitches).
Current I

starts reducing when resistor R

LED

NTC

approximately 6.3k (assuming a 14k 1% tolerance,
series resistor), which corresponds to a temperature of 95°C
for a 100k NTC (100k

 at 25°C). LED current I

is scaled

LED

until the NTC value reaches 2.5 k (125°C).

The CS1610/11/ 12/13 uses the calculated value of the
second low-pass filter to scale output LED current I
shown in Figure 15.

is

If the measured temperature exceeds 125°C, the IC shuts
down using the mechanism discussed above. If the external
overtemperature protection feature is not required, connect
the eOTP pin to GND using a 50k-to-500k resistor to
disable the eOTP feature.

LED

, as

DS929F6 13

6. PACKAGE DRAWING

16 SOICN (150 MIL BODY WITH EXPOSED PAD)

CS1610/11/12/13

mm inch

Dimension MIN NOM MAX MIN NOM MAX

A -- -- 1.75 -- -- 0.069

A1 0.10 -- 0.25 0.004 -- 0.010

b 0.31 -- 0.51 0.012 -- 0.020

c 0.10 -- 0.25 0.004 -- 0.010

Notes:

1. Controlling dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M.

3. This drawing conforms to JEDEC outline MS-012, variation AC for standard 16 SOICN narrow body.

4. Recommended reflow profile is per JEDEC/IPC J-STD-020.

D 9.90BSC 0.390BSC

D1 4.95 5.10 5.25 0.195 0.201 0.207

E 6.00BSC 0.236BSC

E1 3.90BSC 0.154BSC

E2 2.35 2.50 2.65 0.093 0.098 0.104

e 1.27BSC 0.05 BSC

L 0.40 -- 1.27 0.016 -- 0.050

Θ 0

aaa 0.10 0.004

bbb 0.25 0.010

ddd 0.25 0.010

° -- 8° 0° -- 8°

14 DS929F6

CS1610/11/12/13

7. ORDERING INFORMATION

Ordering Number Container AC Line Voltage Temperature Range Package Description

CS1610-FSZ Bulk

120VAC -40 °C to +125 °C

CS1610-FSZR Tape & Reel

CS1611-FSZ Bulk

230VAC -40 °C to +125 °C

CS1611-FSZR Tape & Reel

CS1612-FSZ Bulk

120VAC -40 °C to +125 °C

CS1612-FSZR Tape & Reel

CS1613-FSZ Bulk

230VAC -40 °C to +125 °C

CS1613-FSZR Tape & Reel

16-lead SOICN, Lead (Pb)

Free

16-lead SOICN, Lead (Pb)

Free

16-lead SOICN, Lead (Pb)

Free

16-lead SOICN, Lead (Pb)

Free

8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

Part Number Peak Reflow Temp MSL Rating

CS1610-FSZ 260°C 3 7 Days

CS1611-FSZ 260°C 3 7 Days

CS1612-FSZ 260°C 3 7 Days

CS1613-FSZ 260°C 3 7 Days

a

Max Floor Life

b

a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

b. Stored at 30°C, 60% relative humidity.

DS929F6 15

REVISION HISTORY

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com

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Revision Date Changes

PP1 MAR 2011 Added second stage gain section. Preliminary Status.

PP2 MAY 2011 Added CS1611 230V device.

PP3 OCT 2011 Moved power supply to boost auxiliary winding.

PP4 NOV 2011 Added CS1612 /13. Edited for content and clarity.

F1 DEC 2011 Edited for clarity and typographical error.

F2 FEB 2012 Corrected typographical errors.

F3 MAR 2012 Edited for content and clarity.

CS1610/11/12/13

F4 APR 2012

F5 MAY 2012

F6 APR 2013

Removed ambient temperature range specification, Increased
power dissipation specification. Corrected typographical errors.

Added CS1610-01 specification to the Boost section in the Charac­teristics and Specifications table and Ordering Information section.
Updated CS1610 DCM value.

Removed CS1610-01, made context changes, and corrected typo­graphical errors.

16 DS929F6