Cirrus Logic CS1601H User Manual

CS1601

R2 R3

C1 C2

Regulated

DC Output

Mains

BR 1

BR1

CS1601

CS1601H

GDZCD

IFB

GND

CSIAC

VDD

STB Y

rect

link

CS1601H

Digital PFC Controller for Electronic Ballasts

Features

 Low PFC System Cost

 Best-in-class THD

 Digital EMI Noise Shaping Reduces Conducted EMI

 Adaptive Switching Frequency Control Minimizes Boost

Inductor Size

 High Efficiency Due to Zero-current Switching

 Integrated Feedback Compensation Simplifies System

Design

 Comprehensive Safety Features

• Undervoltage Lockout (UVLO)

• Output Overvoltage Protection

• Cycle-by-cycle Current Limiting

• Input Voltage Brownout Protection

• Open/Short Loop Protection for IAC & IFB Pins

• Thermal Shutdown

 Pin Placement Similar to Traditional Boundary Mode (CRM)

Controllers

Applications

 LED Power Supply/Driver

 Fluorescent Ballasts

 HID Ballasts

Overview

The CS1601 and CS1601H are digital power factor correction (PFC) controllers designed to deliver the lowest PFC system cost in electronic ballast applications. The controller operates in a variable frequency discontinuous conduction mode (VFDCM) with zero-current switching optimized to deliver best-inclass THD and minimize the size and cost of magnetic components. The CS1601 operates at switching frequencies of up to 70kHz, and the CS1601H operates at frequencies of up to 100kHz.

The VF-DCM control algorithm varies both duty cycle and frequency. This spreads the EMI frequency spectrum, thus reducing conducted EMI filtering requirements. In addition, the maximum switching frequency is reached at the peak of the AC input, which allows the use of a smaller, more cost-effective boost inductor.

The feedback loop is closed through an integrated compensation network within the controller, eliminating the need for additional external components. Protection features such as overvoltage, overcurrent, open and short-circuit protection, overtemperature, and brownout protect the system during abnormal transient conditions.

Ordering Information

See page 16.

Cirrus Logic, Inc.

http://www.cirrus.com

FEB’12

DS931F3

1. INTRODUCTION

POR +

DD ( on)

DD ( off)

Volt age

Regul ator

VDD

ZCD

ZCD( th )

Zero -Crossing

Detect

GND

IFB

IAC

LEB

15 k

24k

15 k

24k

ADC

ZCB

600

Thresh old

CS Clamp

CS (clam p)

CS (t h)

STBY

600 k

ref

CS1601

Figure 1. CS1601 Block Diagram

The CS1601 digital power factor correction (PFC) control IC is designed to deliver the lowest system cost by reducing the total number of system components and optimizing the EMI noise signature, which reduces the conducted EMI filter requirements. The CS1601 digital algorithm determines the behavior of the boost converter during startup, normal operation, and under fault conditions (overvoltage, overcurrent, and overtemperature).

Figure 1 illustrates a high-level block diagram of the CS1601. The PFC processor logic regulates the power transfer by using an adaptive digital algorithm to optimize the PFC activeswitch (MOSFET) drive signal duty cycle and switching frequency. The adaptive controller uses independent analogto-digital converter (ADC) channels when sensing the feedback and feedforward analog signals required to implement the digital PFC control algorithm.

The AC mains rectified voltage (on pin IAC) and PFC output link voltage (on pin IFB) are transformed by the PFC processor logic and used to generate the optimum PFC active-switch drive signal (GD) by calculating the optimal switching frequency and t

An auxiliary winding is typically added to the PFC boost inductor to provide zero-current detection (ZCD) information. The ZCD acts as a demagnetization sensor used to monitor

time on a cycle-by-cycle basis.

the PFC active-switching behavior and efficiency. The auxiliary voltage is normalized using an external attenuator

2 DS931F3

and is connected to the ZCD pin, providing the CS1601 a mechanism to detect the valley/zero crossings. The ZCD comparator looks for the zero crossing on the auxiliary winding and switches when the auxiliary voltage is below zero. Switching in the valley of the oscillation minimizes the switching losses and reduces EMI noise.

The PFC controller uses a current sensor for overcurrent protection. The boost inductor peak current is measured across an external resistor in the switching circuit on a cycleby-cycle basis. An overcurrent fault is generated when the sense voltage applied to the CS pin exceeds a predefined reference voltage.

The CS1601 includes a supervisor and protection circuit to manage startup, shutdown, and fault conditions. The protection circuit is designed to prevent output overvoltage as a result of load and AC mains transients. The PFC power converter main rectified voltage (V

) are monitored for overvoltage faults that would lead to

link

) and output link voltage

rect

shutdown of the PFC controller. The PFC overvoltage protection is designed for auto-recovery; operation resumes once the fault clears.

2. PIN DESCRIPTION

CSPFC Current Sense

IFBLink Voltage Sens e

ZCD PFC Zero-current Detect

GND

Ground

GD P FC Ga te D riv e r

VDD IC Supply Voltage

STBYStandby

IA CRectifier Voltage Sens e

8-lead SOIC

Figure 2. CS1601 Pin Assignments

CS1601

Pin Name

IFB

STBY

IAC

ZCD

GND

Pin # I/O

1IN

2IN

3IN

4IN

5IN

6PWR

7OUT

8PWR

Description

Link Voltage Sense — A current proportional to the output link voltage of the PFC is

input here. The current is measured with an ADC.

Standby — A voltage below 0.8V puts the IC into a non-operating, low-power state. The input has an internal 600k pull-up resistor to the V

Rectifier Voltage Sense — A current proportional to the rectified line voltage is input here. The current is measured with an ADC.

PFC Current Sense — The current flowing in the PFC MOSFET is sensed through a resistor. The resulting voltage is applied to this pin and digitized for use by the PFC computational logic to limit the maximum current through the power FET.

PFC Zero-current Detect — Boost Inductor demagnetization sensing input for zerocurrent detection (ZCD) information. The pin is externally connected to the PFC boost inductor auxiliary winding through an external resistor divider.

Ground — Common reference. Current return for both the input signal portion of the IC and the gate driver.

PFC Gate Driver — The totem pole stage is able to drive the power MOSFET with a peak current of 0.5A source and 1.0A sink.

IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the gate driver. A storage capacitor is connected on this pin to serve as a reservoir for operating current for the device, including the gate drive current to the power transistor. This pin is clamped to a maximum voltage (V

) by an internal zener function.

pin.

DS931F3 3

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 Electrical Characteristics

CS1601

Typical characteristics conditions:

=25°C, VDD= 13V, GND = 0V

Minimum/Maximum characteristics conditions:

TJ= -40° to +125 °C, VDD= 10V to 15V, GND = 0 V

All voltages are measured with respect to GND.

Unless otherwise specified, all currents are positive when

flowing into the IC.

Parameter Condition Symbol Min Typ Max Unit

VDD Supply Voltage

Operating Range After Turn-on V

Turn-on Threshold Voltage V

Turn-off Threshold Voltage (UVLO) V

Increasing V

Decreasing V

UVLO Hysteresis V

Zener Voltage I

Supply Current

Startup Supply Current V

Operating Supply Current

CS1601 CS1601H

CL=1nF, fsw=100kHz

=20mA V

DD=VDD(on)

= 1nF, fsw = 70kHz

Standby Supply Current STBY < 0.8V I

Reference

Reference Current I

PFC Gate Drive

Output Source Resistance I

Output Sink Resistance I

Rise Time

Fall Time

Output Voltage Low State I

Output Voltage High State I

= 100mA, VDD=13V R

= -200mA, VDD=13V R

CL=1nF,VDD=13V t

= -200mA, VDD=13V Vol - 0.9 1.3 V

= 100mA, VDD=13V Voh 11.3 11.8 - V

Zero-current Detection (ZCD)

ZCD Threshold V

ZCD Blanking t

ZCD Sink Current

Upper Voltage Clamp I

Overvoltage Protection (OVP)

IFB Current at Startup Mode I

IFB Current at Normal Mode I

OVP Threshold I

OVP Hysteresis I

=1mA V

ZCD

IFB(startup)

IFB(norm)

=129AI

ref

=129AI

ref

DD(on)

DD(off)

Hys

ref

ZCD(th)

ZCB

ZCD

CLP

OVP

OVP(Hy)

7.9 - 17.0 V

9.8 10.2 10.5 V

7.9 8.1 8.3 V

-2.1-V

17.0 17.9 19.0 V

-6895A

1.5

1.75

2.1

2.25mAmA

-80125A

- 129 - A

-9-

-6-

-3250ns

-1527ns

-50-mV

- 200 - ns

-2 - - mA

-VDD-V

-116-A

- 129 - A

- 139 - A

-2-A

4 DS931F3

CS1601

GD OUT

GND

VDD

Buffer

1nF

+15V

-15V

Parameter Condition Symbol Min Typ Max Unit

Overcurrent Protection (OCP)

Current Sense Reference Clamp V

Threshold on Current Sense V

Leading Edge Blanking t

Delay to Output t

CS(clamp)

CS(th)

LEB

Brownout Protection (BP)

Input Brownout Protection Threshold Gate Drive Turns Off I

Input Brownout Recovery Threshold Gate Drive Turns On I

Thermal Protection

Thermal Shutdown Threshold T

Thermal Shutdown Hysteresis T

Input

STBY

BP(lower)

BP(upper)

SD(Hy)

Logic Threshold Low - - 0.8 V

Logic Threshold High V

Notes: 1. External circuitry should be designed to ensure the ZCD sink current pulled from the internal clamp diode when it

is forward biased does not exceed specification.

2. Specifications guaranteed by design and are characterized and correlated using statistical process methods.

3. STBY

4. For test purposes, load capacitance (C

is designed to be driven by an open collector. The input is internally pulled up with a 600 k resistor.

) is 1nF and is connected as shown in the following diagram.

-1.0-V

-0.5-V

- 300 - ns

- 60 350 ns

-31.6-A

-39.6-A

134 147 159 °C

-9-°C

-0.8 - - V

DS931F3 5

+ 11 hidden pages

Cirrus Logic CS1601H User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Applications

1. INTRODUCTION

2. PIN DESCRIPTION

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 Electrical Characteristics