Cirrus Logic CS1501 User Manual

CS1501

R2 R3

R4 R7

8 1

C1 C2

Regulated

DC Output

Mains

BR 1

BR1

CS1501

GDZCD

IFB

GND

CSIAC

VD D

STB Y

link

rect

Digital Power Factor Correction Control IC

Features

 Digital EMI Noise Shaping

 Adaptive Digital Energy Controller

• Excellent Efficiency Under All Load and Line Conditions

• Zero-voltage Switching Topology

 Minimal External Devices Required

 Adaptive Digital Control Loop

 Comprehensive Safety Features

• Undervoltage Lockout (UVLO)

• Output Overvoltage Protection

• Cycle-by-cycle Current Limiting

• Open/Short Loop Protection for IAC & IFB Pins

• Thermal Shutdown

 Pin Placement Similar to Traditional Boundary Mode (CRM)

Controllers

Applications

 LCD and LED TVs

 Notebooks

 Server/Telecom

Overview

The CS1501 is a high-performance digital power factor correction (PFC) controller designed for switching mode power supply (SMPS) applications. The CS1501 actively manages the power factor correction while achieving high efficiency over a wide load range.

The CS1501 adaptively controls the input AC current so that it is in phase with the AC mains voltage, and its waveform mimics the input voltage waveform. The PFC controller executes adaptive digital algorithms designed to shape the AC mains input current waveform to be in phase with the input voltage waveform.

The CS1501 is equipped with a zero-current detection (ZCD) circuit providing the PFC digital controller the capability to turn on the MOSFET when the voltage across the drain and source is near zero. Additionally, a current-sensing circuit is incorporated for instantaneous overcurrent protection.

Ordering Information

See page 16.

Cirrus Logic, Inc.

http://www.cirrus.com

FEB’12

DS927F4

1. INTRODUCTION

POR +

DD ( on)

DD ( off)

Volt age

Regulator

VDD

ZCD

ZCD(th)

Zero Crossing

Detect

GND

IFB

IAC

LEB

15 k

24 k

15 k

24 k

ADC

ZCB

600

Thresho ld

CS Clamp

CS (c lamp )

CS (t h)

STBY

600 k

ref

CS1501

Figure 1. CS1501 Block Diagram

The CS1501 digital power factor correction (PFC) control IC is designed to deliver the lowest system cost by reducing the total number of system components and optimizing the EMI noise signature, which reduces the conducted EMI filter requirements. The CS1501 digital algorithm determines the behavior of the boost converter during startup, normal operation, and under fault conditions (overvoltage, overcurrent, and overtemperature).

Figure 1 illustrates a high-level block diagram of the CS1501. The PFC processor logic regulates the power transfer by using an adaptive digital algorithm to optimize the PFC active-switch (MOSFET) drive signal duty cycle and switching frequency. The adaptive controller uses independent analog-to-digital converter (ADC) channels when sensing the feedback and feedforward analog signals required to implement the digital PFC control algorithm.

The AC mains rectified voltage (on pin IAC) and PFC output link voltage (on pin IFB) are transformed by the PFC processor logic and used to generate the optimum PFC active-switch drive signal (GD) by calculating the optimal switching frequency and t

An auxiliary winding is typically added to the PFC boost inductor to provide zero-current detection (ZCD) information.

time on a cycle-by-cycle basis.

The ZCD acts as a demagnetization sensor used to monitor

the PFC active-switching behavior and efficiency. The auxiliary voltage is normalized using an external attenuator and is connected to the ZCD pin, providing the CS1501 a mechanism to detect the valley/zero crossings. The ZCD comparator looks for the zero crossing on the auxiliary winding and switches when the auxiliary voltage is below zero. Switching in the valley of the oscillation minimizes the switching losses and reduces EMI noise.

The PFC controller uses a current sensor for overcurrent protection. The boost inductor peak current is measured across an external resistor in the switching circuit on a cycle-by-cycle basis. An overcurrent fault is generated when the sense voltage applied to the CS pin exceeds a predefined reference voltage.

The CS1501 includes a supervisor and protection circuit to manage startup, shutdown, and fault conditions. The protection circuit is designed to prevent output overvoltage as a result of load and AC mains transients. The PFC power converter main rectified voltage (V (V

) are monitored for overvoltage faults which would lead to

link

shutdown of the PFC controller. The PFC overvoltage

) and output link voltage

rect

protection is designed for auto-recovery; operation resumes once the fault clears.

2 DS927F4

2. PIN DESCRIPTION

CSPFC Current Sense

IFBLink Voltage Sens e

ZCD PFC Zero-current Detect

GND

Ground

GD P FC Ga te D r iv er

VDD IC Supply V oltage

STBYStandby

IA CRectifier Voltage S ense

8-lead SOIC

Figure 2. CS1501 Pin Assignments

CS1501

Pin Name

IFB

STBY

IAC

ZCD

GND

Pin # I/O

1IN

2IN

3IN

4IN

5IN

6PWR

7OUT

8PWR

Description

Link Voltage Sense — A current proportional to the output link voltage of the PFC is

input here. The current is measured with an ADC.

Standby — A voltage below 0.8V puts the IC into a non-operating, low-power state. The input has an internal 600k pull-up resistor to the V

Rectifier Voltage Sense — A current proportional to the rectified line voltage is input here. The current is measured with an ADC.

PFC Current Sense — The current flowing in the PFC MOSFET is sensed through a resistor. The resulting voltage is applied to this pin and digitized for use by the PFC computational logic to limit the maximum current through the power FET.

PFC Zero-current Detect — Boost Inductor demagnetization sensing input for zero-current detection (ZCD) information. The pin is externally connected to the PFC boost inductor auxiliary winding through an external resistor divider.

Ground — Common reference. Current return for both the input signal portion of the IC and the gate driver.

PFC Gate Driver — The totem pole stage is able to drive the power MOSFET with a peak current of 0.5A source and 1.0A sink.

IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the gate driver. A storage capacitor is connected on this pin to serve as a reservoir for operating current for the device, including the gate drive current to the power transistor. This pin is clamped to a maximum voltage (V

) by an internal zener function.

pin.

DS927F4 3

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 Electrical Characteristics

Typical characteristics conditions:

TA=25°C, VDD= 13V, GND = 0V

All voltages are measured with respect to GND.

Unless otherwise specified, all currents are positive when

flowing into the IC.

Parameter Condition Symbol Min Typ Max Unit

Supply Voltage

Operating Range After Turn-on V

Turn-on Threshold Voltage V

Turn-off Threshold Voltage (UVLO) V

Increasing V

Decreasing V

UVLO Hysteresis V

Zener Voltage I

Supply Current

=20mA V

Startup Supply Current VDD=V

Operating Supply Current

CL= 1nF, fsw = 70kHz I

Standby Supply Current STBY

Reference

Reference Current I

PFC Gate Drive

Output Source Resistance I

Output Sink Resistance I

Rise Time

Fall Time

Output Voltage Low State I

Output Voltage High State I

= 100mA, VDD=13V R

= -200mA, VDD=13V R

CL=1nF,VDD=13V t

= -200mA, VDD=13V Vol - 0.9 1.3 V

= 100mA, VDD=13V Voh 11.3 11.8 - V

Zero-current Detection (ZCD)

ZCD Threshold V

ZCD Blanking t

ZCD Sink Current

Upper Voltage Clamp I

=1mA V

ZCD

Overvoltage Protection (OVP)

IFB Current at Startup Mode I

IFB Current at Normal Mode I

OVP Threshold I

OVP Hysteresis I

=129AI

ref

=129AI

ref

Overcurrent Protection (OCP)

Current Sense Reference Clamp V

Threshold on Current Sense V

Leading Edge Blanking t

Delay to Output t

Minimum/Maximum characteristics conditions:

TJ= -40° to +125°C, VDD= 10V to 15V, GND = 0 V

DD(on)

< 0.8V I

IFB(startup)

IFB(norm)

DD(on)

DD(off)

Hys

ref

ZCD(th)

ZCB

ZCD

CLP

OVP

OVP(Hy)

CS(clamp)

CS(th)

LEB

CS1501

7.9 - 17.0 V

9.8 10.2 10.5 V

7.9 8.1 8.3 V

-2.1-V

17.0 17.9 19.0 V

-6895A

-1.52.1mA

-80125A

- 129 - A

-9-

-6-

-3250ns

-1527ns

-50-mV

- 200 - ns

-2 - - mA

-VDD-V

-116-A

- 129 - A

- 136 - A

-2-A

-1.0-V

-0.5-V

- 300 - ns

-60350ns

4 DS927F4

CS1501

GD OUT

GND

VDD

Buffer

1nF

+15V

-15V

Parameter Condition Symbol Min Typ Max Unit

Brownout Protection (BP)

Input Brownout Protection Threshold Gate Drive Turns Off I

Input Brownout Recovery Threshold Gate Drive Turns On I

Thermal Protection

Thermal Shutdown Threshold T

Thermal Shutdown Hysteresis T

STBY Input

BP(lower)

BP(upper)

SD(Hy)

Logic Threshold Low - - 0.8 V

Logic Threshold High V

Notes: 1. External circuitry should be designed to ensure the ZCD sink current pulled from the internal clamp diode when it

is forward biased does not exceed specification.

2. Specifications guaranteed by design and are characterized and correlated using statistical process methods.

3. STBY

4. For test purposes, load capacitance (C

is designed to be driven by an open collector. The input is internally pulled up with a 600 k resistor.

) is 1nF and is connected as shown in the following diagram.

-31.6-A

-39.6-A

134 147 159 °C

-9-°C

-0.8 - - V

DS927F4 5

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