Cirrus Logic AN364 User Manual

AN364

Application Note

Design Guide for a CS1610 and CS1611

Dimmer-Compatible SSL Circuit

1 Overview of the CS1610/11

The CS1610 and CS1611 are digital control ICs engineered to deliver a high-efficiency, cost-effective, flicker-free,
phase-dimmable, solid-state lighting (SSL) solution for the incandescent lamp replacement market. The CS1610/11
is designed to control a quasi-resonant flyback topology. The CS1610 and CS1611 are designed for 120VAC and
230VAC line voltage applications, respectively.

The CS1610/11 integrates a critical conduction mode (CRM) boost converter that provides power factor correction
and dimmer compatibility with a constant output current, quasi-resonant second stage. An adaptive dimmer
compatibility algorithm controls the boost stage and dimmer compatibility operation mode to enable flicker-free
operation to 2% output current with leading-edge, trailing-edge, and digital dimmers (dimmers with an integrated
power supply).

1.1 Features

• Best-in-Class Dimmer Compatibility

- Leading-edge (TRIAC) Dimmers

- Trailing-edge Dimmers

- Digital Dimmers (with Integrated Power Supply)

• Up to 90% Efficiency

• Flicker-free Dimming

• 0% Minimum Dimming Level

• Quasi-resonant Second Stage with Constant-current Output

- Flyback for 1610/ 11

• Fast Startup

• Tight LED Current Regulation: Better than ±5%

• Primary-side Regulation (PSR)

• >0.9 Power Factor

• IEC-61000-3-2 Compliant

• Soft Start

• Protections:

- Output Open/Short

- Current-sense Resistor Open /Short

- External Overtemperature Using NTC

Cirrus Logic, Inc.

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2012

(All Rights Reserved)

AUG’12

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Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you
go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives
consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This con­sent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP­ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR
USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER
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AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANT­ABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER
OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE,
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Cirrus Logic, Cirrus, the Cirrus Logic logo designs, EXL Core, the EXL Core logo design, TruDim, and the TruDim logo design are trademarks of Cirrus Logic, Inc.
All other brand and product names in this document may be trademarks or service marks of their respective owners.

IMPORTANT SAFETY INSTRUCTIONS

Read and follow all safety instructions prior to using this demonstration board.

This Engineering Evaluation Unit or Demonstration Board must only be used for assessing IC performance in a
laboratory setting. This product is not intended for any other use or incorporation into products for sale.

This product must only be used by qualified technicians or professionals who are trained in the safety procedures
associated with the use of demonstration boards.

Risk of Electric Shock

• The direct connection to the AC power line and the open and unprotected boards present a serious risk of electric
shock and can cause serious injury or death. Extreme caution needs to be exercised while handling this board.

• Avoid contact with the exposed conductor or terminals of components on the board. High voltage is present on
exposed conductor and it may be present on terminals of any components directly or indirectly connected to the AC
line.

• Dangerous voltages and/or currents may be internally generated and accessible at various points across the board.

• Charged capacitors store high voltage, even after the circuit has been disconnected from the AC line.

• Make sure that the power source is off before wiring any connection. Make sure that all connectors are well

connected before the power source is on.

• Follow all laboratory safety procedures established by your employer and relevant safety regulations and guidelines,
such as the ones listed under, OSHA General Industry Regulations - Subpart S and NFPA 70E.

Suitable eye protection must be worn when working with or around demonstration boards. Always

comply with your employer’s policies regarding the use of personal protective equipment.

All components and metallic parts may be extremely hot to touch when electrically active.

2 AN364REV3

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2 Introduction

This application note is a guide to designing a Solid State Lighting (SSL) LED lamp circuit using Cirrus Logic's
CS1610/11. The first half of the document presents a step-by-step design procedure for calculating the required
components for each stage of the system. The second half of the document supports the design effort by showing
an example of a CS1611 design. The CS1611 example will be based on the Cirrus Logic CRD1611-8W reference
design. See the CS1610/11/12/13 TRIAC Dimmable LED Driver IC data sheet for more details about the CS1610/11
IC. See the CRD1610-8W 8 Watt Reference Design and CRD1611-8W 8 Watt Reference Design data sheets for
more details regarding the reference design.

2.1 Definition of Symbols

Symbol Description

F

sw

TT Switching period

T1 Primary FET ‘ON’ time

T2 Secondary rectifier diode conduction time

T3 Time when the FET and diode are OFF

D Duty ratio (T1/TT)

V

Reflected

V

CLAMP

I

PK(FB)

R

FBGAIN

R

Sense

I

PK(BST)

L

P

L

BST

V

BST

N

V

OUT

P

OUT

 Power stage efficiency

Switching frequency

Voltage across secondary winding reflected onto primary

Primary clamping voltage above boost output voltage (V

Peak current in primary-side FET

A resistor used to program the switching period TT

Primary current sense resistor

Maximum boost inductor current

Flyback transformer primary inductance

Boost inductance

Boost output voltage

Flyback transformer turns ratio N

Secondary output voltage DC = the LED string supply voltage

Load power = Power to the LED string

P/NS

BST

)

2.2 Definition of Acronyms

Acronym Description

PFC Power Factor Correction

OVP Overvoltage Protection

eOTP External Overtemperature Protection

OCP Overcurrent Protection

iOTP Internal Overtemperature Protection

OLP Open Loop Protection

LED Light Emitting Diode

TXF Transformer

TRIAC

SSL

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TRIode for Alternating Current, which is an electronic component that can conduct current in
either direction when it is triggered. It is formally called a bidirectional triode thyristor.

Solid State Lighting. Refers to a type of lighting that uses semiconductor LEDs as a source of
illumination rather than electrical filaments, plasma, or gas.

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T1

D3

LED +

LED -

Z2

L1

L3

R8

R11

R3

R7

R1

R2

Q3

L2

Z1

C2

D7

D6

Q1

R17R13

Q2

D5

R18

NTC

R14

R15

R22

R23

Q4

R21

R19

R9

BR1

F1

R12

D8

R4

CS1610 /11

FBGAIN

IAC

FBAUX

BSTOUT

GNDSGNDIPK

CLAMP

GD

FBSEN SE

eOTP

VDD

SOURCE

CY

D2

L

N

AC Main s

D4

R10

R16

R6

R20

R5

D1

BSTAUX

R24

Boost

Gate Bias

Steady State

Supply

Active
Clamp

FlybackEMI

C11

C8 C10

C9

C7

C6

C5

C4

C3

C1

C12

Figure 1. Block Diagram of CS1610/11 Design

3 Design Process

The design process for a two-stage power converter system can be partitioned into six circuit blocks (see Figure 1).
The AC line voltage is passed through an electromagnetic interference (EMI) filter to suppress conducted interfer­ence found on the power line. The output of the EMI filter is then converted to the desired DC output by a boost­flyback converter. The power converter system includes the Gate Bias, Steady State Supply, and Active Clamp sup­port circuitry.

3.1 Operating Parameters

To initiate the design procedure, a set of operating parameters are required. Operating parameters required
for the analytical process are outlined in the table below. Parameters critical to the overall design, but not
specifically addressed in this document, include: EMI compliance, efficiency, form factor, layout, and operating
temperature.

Output Power

AC line Input Voltage

Output Voltage

Load Current

Parameters Symbol

Maximum Switching Frequency*

4 AN364REV3

* Increasing Fsw may reduce the size of the magnetics but increase switching losses in the FET.

P

OUT

V

IN

V

OUT

I

OUT

F

sw(max)

3.2 Overview of Design Steps

The CS1610/11 LED driver IC controls a power converter system that has two distinct power conversion
stages. The IC requires supporting circuitry to provide a steady state power supply with gate bias, a clamp
circuit, and EMI filtering. The recommended design process is outlined below:

1. Start with the flyback stage.

2. Design for full power at minimum V
operating parameters.

3. Optimize the flyback stage through validation and design iteration.

4. Base the boost stage design on the power requirement of the flyback stage.

5. Start the boost stage design in No-dimmer Mode.

6. Determine the peak current in the boost inductor, I

7. Determine a boost inductance, L
Consider the impact on the EMI.

8. Pick the boost FET based on peak current ratings.

9. Choose the power supply components.

10.Complete the non-power-converting circuitry: ZCD, OVP, eOTP, Clamp Circuit, Charge Pumps, and Bias
Circuits.

11. Design the EMI filter.

12.Lay out the PCB.

. Note that any design may require design trade-offs for different

BST

PK(BST)

, that adjusts the switching frequency within the defined range.

BST

.

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The flyback stage design is carried out at the full brightness (full load) point. To achieve an optimal solution,
several iterations of the design process may be required. The EMI filter is particularly critical because there is
a small degree of freedom in selecting the EMI component values that meet the requirements below:

• Comply with EMI regulations

• Achieve compatibility with the largest variety of dimmers

• Smooth dimming, no flicker with a variable number of identical lamps controlled by one dimmer

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3.3 Flyback Stage Design

Flyback Specification

Determine N, Fsw,

V

Refle cted

, and V

CLAMP

Estimate T3

Calculate TT

fb

Calculate R

Sense

,

R

FBG AIN

, and Primary

Inductance

R

Sense,RFBG AIN

Fit?

Yes

No

Calculate T1,

T2, and I

PK(FB)

Calculate RMS Current

and Output Capacitor

Transformer Core

Steps for the Flyback Design

1. Set boost output voltage V

BST

.

2. Select a MOSFET that aligns with the quality standards of
the designer’s company.

3. Determine the transformer turns ratio from the

V

BST

, FET

voltage, and reflected voltage V

Reflected

.

4. Use the nominal switching frequency and an initial
estimate for time T3 to determine the value of time TT at
full brightness.

5. Use V

BST

, TT, and V

Reflected

to determine time T1 and T2.

6. Use time T2 and TT, turns ratio N and load current to
determine the value of peak primary current I

PK(FB)

.

7. Use I

PK(FB)

to determine R

Sense

.

8. Calculate the primary side inductance using time T1.

9. Calculate flyback gain resistor R

FBGAIN

using full load
conditions. Ensure linearity of the load versus the dim
curve.

10. Calculate primary and secondary RMS currents using
I

PK(FB)

and duty cycle.

11. Select an output capacitor.

12. Determine the flyback transformer specifications.

13. Determine if the flyback transformer fits into specified form
factor after designing and constructing flyback transformer.
Repeat steps 3 to 12 until form factor criteria is met.

14. Refine the circuit using the final flyback transformer
design.

15. Validate that the system meets the operating criteria.

Figure 2 illustrates the steps for designing the flyback stage.

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6 AN364REV3

Figure 2. Flyback Stage Design

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V

Drain maxVBST maxVCLAMP max

+=

[Eq. 1]

V

OvershootVCLAMPVReflecteed

–=

[Eq. 2]

Overshoot is a brief condition
above V

Reflected

, required to
quickly dissipate the energy stored
in the transformer leakage
inductance.

During this time, the primary
current is kept from transferring to
the secondary, siphoning energy
from the load to the clamp zener
(snubber).

Figure 3. FET Breakdown Voltage

V

Margin

V

CLAMP

V

BST

V

Overshoot

V

Reflected

ET Breakdown
Voltage Rating

Clamp

Voltage

Boost Output

Voltage

Margin

Reflected
Voltage

Overshoot
Voltage

Step 1) Select a Value for Boost Output Voltage

The value of the boost output voltage, V
The maximum V

voltage, V

BST

BST(max)

requirement within economical constraints.

V

is determined by an internal parameter and changes slightly depending on the type of dimmer detected.

BST

With sense resistors R7, R8, R14, and R15 set to 1.5M, the resulting V
system. For a 120V system, sense resistors R7, R8, R14, and R15 are set to 750k each, and the resulting
V

is approximately 200V. V

BST

each half line-cycle. V

droops to its lowest value towards the end of each half line-cycle until the boosting

BST

is regulated by charging the boost output capacitor to its nominal value

BST

process starts again in the next half line-cycle.

Step 2) Select an Appropriate FET

Determine the FET breakdown voltage, V
voltage, V

Drain(max)

, is calculated using Equation 1.

The ringing associated with the transformer leakage inductance usually does not have enough energy to
cause a destructive avalanche breakdown. Voltages closely approaching the FET breakdown voltage are
acceptable.

Ideally, V

Reflected

should have nearly the same value as V
duty cycle optimizes the transformer efficiency. Alternatively, V
to rapidly discharge the energy stored in the transformer leakage inductance.

The FET breakdown voltage is constrained by cost and performance. A compromise must be reached in
partitioning voltage between V
divide V

CLAMP

into V

Reflected

, V

BST

CLAMP

and a reasonable overshoot voltage portion, V

The losses caused by the leakage inductance are inversely proportional to V
Equation 2.

, must be greater than the maximum input AC line voltage peak.

BST

, should be kept as low as possible to help maintain the FET breakdown

is approximately 405V for a 230V

BST

Breakdown

, and V

, and reflected voltage, V

because operating the transformer near 50%

BST

CLAMP

. A second compromise will then determine how to

Margin

Reflected

should be much greater than V

Overshoot

. The FET maximum drain

.

Overshoot

, which is determined by

Reflected

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F

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V

Breakdown

V

BSTVReflected

V+

CLAMP

V

Reflected

– V

Minarg

++=

[Eq. 3]

N

V

Reflected

V

OUT max

----------------------------=

[Eq. 4]

T1 T2+

1

F

sw

---------





T3–=

[Eq. 5]

T1
T2

-------

V

Reflected

V

BST

--------------------------=

[Eq. 6]

For optimum efficiency, the increase in transformer losses (created by an uneven duty cycle) must balance the
reduction of the losses caused by discharging the leakage inductance (obtained by increasing the overshoot
voltage). Equation 3 is used to balance all voltages contributing to the FET voltage drain and source.

where

V

Overshoot

Step 3) Determine the Flyback Transformer Turns Ratio

Select a turns ratio based on the output voltage, V

where

V

OUT(max)

Step 4) Select the Full Brightness Switching Frequency

The CS1611 maximum switching frequency is 200kHz. Test results indicate that optimal performance is
obtained in the range of 75kHz to 120kHz. Higher frequencies allow the use of smaller magnetics, but
switching losses increase. Transformer size versus switching frequency is limited by designs that require
isolation. Selecting too low a full brightness switching frequency risks impairing dimmer compatibility while also
allowing the minimum frequency to drop into the audible range.

From the full brightness frequency, determine the value of (T1 +T2) using Equation 5.

= V

CLAMP

- V

Reflected

OUT

, and V

= the maximum LED string forward voltage V

Reflected

at full current plus the rectifying diode voltage VF.

OUT

using Equation 4.

where

T3 is 1/2 the transformer resonant period

The transformer primary inductance resonates with the total parasitic capacitance of the drain node. For initial
calculations, T3 is estimated as 1s and must be measured for final accuracy.

Step 5) Determine the Flyback Nominal Timing T1 and T2

From the reflected voltage and the turns ratio, determine T1 and T2. Equation 6 ensures zero DC voltage
across the transformer T1 magnetizing inductance.

8 AN364REV3

Figure 4 illustrates the switching frequency used in the system design.

t

i(t)

T1 T2

TT

No Curr ent

T3

Peak Primary Current, I

PK(FB)

Primar y
Current

Secondary

Current

Figure 4. Timing Diagram of T1, T2, T3, and TT

T1

1

F

sw

--------- T 3–

V

Reflected

V

ReflectedVBST

+

----------------------------------------------------

=

[Eq. 7]

T2

1

F

sw

--------- T 3–

V

BST

V

ReflectedVBST

+

----------------------------------------------------

=

[Eq. 8]

I

PK FB

2P

OUT max

TT

fb

 V

BST

 T1fb

----------------------------------------------

=

[Eq. 9]

R

Sense

1.4V

I

PK FB

------------------=

[Eq. 10]

L

P

V

BST

T1

I

PK FB

---------------------------

=

[Eq. 11]

Solve for T1 and T2 using Equation 7 and Equation 8:

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Period T1 is limited to a maximum duration of 8.8s by the IC algorithm. Verify that period T1 at full power is
less that 7.8s, leaving sufficient time for a probe cycle, which requires a slightly longer T1 period.

Step 6) Calculate Peak Current on the Flyback Primary-side

Calculate I

using Equation 9:

PK(FB)

where

TT

= switching period at full brightness (full load condition)

fb

T1

= period T1 at full brightness (full load condition)

fb

Step 7) Calculate R

Calculate sense resistor R

Sense

Sense

(R23)

(R23) for flyback using Equation 10:

where

R23 = R

Sense

in 

Step 8) Calculate the Flyback Primary-side Inductance

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