AN241
Analog Input Buffer Architectures
by Kevin L Tretter
1. Introduction
There are many considerations that must be taken into account when designing and implementing an analog input buffer. These include negligible noise contribution, input biasing, isolation from switched capacitor currents, maintaining a low output impedance so as not to cause distortion, and providing antialias filtering appropriate for the modulator sampling rate.
This application note provides several filter topologies that address the above concerns. The following analog input buffers have been divided into four categories: fully differential, single-ended to differential, sin- gle-ended with dedicated reference pins for each channel, and single-ended with a common, or shared, reference.
2. Fully Differential Analog Input Buffer
2.1Applicable Converters
A fully differential analog input buffer is ideal for use with the following Cirrus Logic audio converters:
-CS5361
-CS5381
-CS4272
-CS42528/26/18/16
-CS42428/26/18/16
2.2Introduction to Differential Signals
A differential signal can be defined as two nodes that have equal but opposite signals around a fixed point (called the common mode level). The two signal nodes are typically referred to as positive and negative (or non-inverting and inverting), as shown in the following example of a differential sine wave:
CSxxxx
3.91 V |
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2.50 V |
AIN+ |
1.09 V |
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3.91 V |
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2.50 V |
AIN- |
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1.09 V |
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Full Scale Input Level = (AIN+) - (AIN-) = 5.64 Vpp
Figure 1. Example of a Differential Signal
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Copyright Cirrus Logic, Inc. 2003 |
OCT ‘03 |
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http://www.cirrus.com |
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(All Rights Reserved) |
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In the above example, the full scale input voltage is 5.64 Vpp (differentially), with each leg swinging 2.82 Vpp. Please note that the full scale input voltage level may vary from part to part. Also, the common mode level (which in the above example is 2.5 0V) can also vary depending on the converter.
2.3Recommended Filter Topology
Figure 2 shows a fully differential analog input buffer. This buffer provides proper biasing, isolation from the switched capacitor currents, low output impedance, and anti-alias filtering. The noise contribution of this buffer is determined primarily by the noise floor of the op-amp.
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634 Ω |
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470 pF |
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C0G |
91 Ω |
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10 µF |
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100 kΩ |
10 kΩ |
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634 Ω |
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2700 pF |
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470 Fp |
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C0G |
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10 kΩ |
0.01 µF |
C0G |
91 Ω |
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10 µF |
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100 kΩ |
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1 µF |
0.01 µF |
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634 Ω |
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470 pF |
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C0G |
91 Ω |
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10 µF |
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100 kΩ |
10 kΩ |
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634 Ω |
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2700 Fp |
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470 Fp |
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C0G |
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10 kΩ |
0.01 µF |
C0G |
91 Ω |
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10 µF
100 kΩ
CSxxxx
AIN+
AIN-
VQ or
VCOM
AIN+
AIN-
Figure 2. Fully Differential Input Buffer
2.4Overview of the Filter Topology
2.4.1High Pass Filter and DC Biasing
The first stage of the buffer forms a high pass filter and provides the proper biasing to the positive terminals of the op-amps. The high pass filter is formed from the combination of the AC-coupling capacitor along with the resistor to the bias voltage reference (VQ or VCOM, depending on the naming convention). The 3 dB corner of the high pass filter can be calculated as follows:
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FC |
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2πRC |
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where: R is the value of the resistor (in Ohms)
C is the value of the capacitor (in Farads)
In the input buffer shown in Figure 2, R = 10 kΩ and C = 10 µF. This places the 3 dB corner at approximately 1.59 Hz. Typically, this corner should be at least one decade below the bandwidth of interest in order to prevent a significant droop in the frequency response.
The proper DC biasing (common mode level) is set via the on-chip reference (VQ or VCOM). In the input buffer shown above, the bias is set through a 10kΩ resistor. Please note that this resistor value has several implications. Since the input impedance into the op-amp is extremely high, the effective input impedance into the analog input buffer will be determined by the value of the resistor to the bias voltage in parallel with the 100 kΩ shunt resistor. In the input buffer shown above, the input impedance is approximately 9 kΩ. Ideally, the larger this input impedance the better. However, in the input buffer shown in Figure 2, the AC-coupling capacitor will initially be charged up via the on-chip reference (VQ or VCOM). This charge up time is dependent on the size of the AC-coupling capacitor and the amount of series resistance to the reference voltage supply. The reference pin (VQ or VCOM) has an associated output impedance that must also be considered when calculating the charge up time. The time constant can be calculated as follows:
τ = RC
where R = the amount of resistance between the AC-coupling capacitor and reference voltage (in Ohms)
C = the value of capacitance of the AC-coupling capacitor (in Farads)
In the input buffer shown in Figure 2, R = 35 kΩ (assuming a 25kΩ output impedance on the reference pin), and C = 10 µF. This produces a time constant of 0.35 s. This would indicate that the capacitor will charge up to within 99% of the final DC value in approximately 1.75 s (which is 5 time constants). The 100 kΩ resistors to ground on the input node allow a DC path to charge the AC-coupling capacitors, regardless of whether or not there is an input signal source present.
2.4.2Op Amp Circuitry and Anti-Aliasing Capacitor
The op-amp topology used in the input buffer shown in Figure 2 addresses two issues. First, it provides an extremely low output impedance and therefore minimizes the amount of distortion presented to the converters internal sampling circuits. By placing the 91 Ω resistor in the feedback loop, it’s resistance is divided by the open-loop gain of the op-amp, providing a sub-ohm output impedance. Secondly, this opamp topology provides a low pass filter. Using the recommended values, this filter remains flat throughout the audio passband and provides approximately 2 0dB of rejection at the modulator sampling rate (where the converter is susceptible to aliasing). The characteristics of this low pass filter can be changed by adjusting the values of the resistors and capacitors in the feedback loop. However, it is important to maintain
a flat frequency response throughout the passband of interest and to provide reasonable attenuation at the input sampling rate of the converter. Also, low value resistors should be used to minimize the addition of resistor thermal noise.
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Figure 2 implements a common mode capacitor between the positive and negative nodes of the differential inputs. This capacitor is commonly referred to as the anti-aliasing capacitor, and performs several functions. The value of the capacitor affects the overall low pass filter response and the amount of attenuation at the modulator sampling rate. This capacitor also acts as a charge reservoir for the internal sampling capacitors. Since this capacitor is located in the signal path, it is very important not to use capacitors with a large voltage coefficient (such as general purpose ceramics) since they can degrade signal linearity.
3. Single-Ended to Differential Input Buffer
3.1Applicable Converters
A single-ended to differential analog input buffer is ideal for use with the following Cirrus Logic audio converters:
-CS5361
-CS4272
-CS42528/26/18/16
-CS42428/26/18/16
3.2Introduction
A single-ended signal consists of only one signal line and hence requires only one input pin. Single-ended inputs typically require less input buffer components, but also have several disadvantages. First, at a given voltage level, a single-ended input cannot produce as much signal swing as a differential signal, hence reducing the dynamic range. Also, single-ended inputs are more prone to errors caused by DC offsets and coupled-noise.
3.3Recommended Filter Topology
Figure 3 shows a single-ended to differential analog input buffer. This buffer provides proper biasing, isolation from the switched capacitor currents, low output impedance, and anti-alias filtering. The second opamp stage is set up in an inverting configuration to produce the negative node of the differential input. In the input buffer shown below, the second stage has unity gain, and the single-ended input level will effectively be doubled when presented differentially to the converter. For example, a 2Vpp single-ended input will provide a 4Vpp differential input to the converter.
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1 µF
100 kΩ |
VA |
3.3 kΩ
R kΩ
1 µF
100 kΩ |
VA |
3.3 kΩ
R kΩ
634 Ω
470 Fp
C0G
-91 Ω
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634 Ω |
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100 kΩ |
470 pF |
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C0G |
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0.01 µF |
100 µF |
634 Ω
470 pF C0G
-91 Ω
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634 Ω |
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100 kΩ |
470 pF |
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C0G |
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0.01 µF |
100 µF |
CSxxxx
AIN+
634 Ω
2700 pF |
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C0G |
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91 Ω |
AIN- |
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VQ or |
1 µF 0.01 µF |
VCOM |
AIN+
634 Ω
2700 pF C0G
91 Ω
AIN-
Figure 3. Single-Ended to Differential Input Buffer
3.4Overview of the Filter Topology
3.4.1High Pass Filter and DC Biasing
The first stage of the buffer forms a high pass filter and provides the proper biasing to the positive terminals of the op-amps. The value of the resistors denoted as “R” will vary depending on the optimal DC bias for the given converter. Typically this is around half of the VA voltage supply. The high pass filter is formed from the combination of the AC-coupling capacitor along with the resistor that connects the positive terminal of the op-amp to the DC bias voltage. The 3dB corner of the high pass filter can be calculated as follows:
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