CS1501
CS1601
8
VDD
V
DD
7
GD
6
GND
GD OUT
GD
GND
CS
VDD
Buffer
S
1
R
1
R
2
R
3
TP
C
L
1nF
+15V
-15V
S
2
V
DD
AN352
Application Note
DRIVING MOSFETs WITH THE CS1501 & CS1601
1. Introduction
The CS1501 & CS1601 are high-performance digital power factor correction (PFC) controllers designed for switching mode power supply (SMPS) & lighting applications. This papers discusses the basics of driving power MOSFETs, including so me guidelines for layout & component choices.
2. CS1501 & CS1601 Gate Drive
The CS1501 & CS1601 internal gate driver is a dual MOSFET between VDD & GND.
The CS1501 & CS1601 parameters for its internal gate drive are listed below.
Parameter Condition Symbol Min Typ Max Unit
PFC Gate Drive
Output Source Resistance IGD= 100 mA, VDD=13V R
Output Sink Resistance IGD=-200mA,VDD=13V R
Rise Time
Fall Time
1
1
CL=1nF,VDD=13V t
CL=1nF,VDD=13V t
OH
OL
r
f
-9-Ω
-6-Ω
-3245ns
-1525ns
Output Voltage Low State IGD=-200mA,VDD=13V Vol - 0.9 1.3 V
Output Voltage High State IGD= 100 mA, VDD=13V Voh 11.3 11.8 - V
is defined as the capacitive load that the IC drives. For test purposes, load capacitance (CL) is 1 nF and is
1. C
L
connected as shown in the following diagram.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
AN352REV1
MAR ‘11
AN352
A
7
R
g
7
GD
C
7
R
g
7
GD
B
7
R
g
7
GD
7
4
CS
7
4
CS
7
4
CS
R
cs
R
cs
R
cs
Q
off
D
off
3. Gate Drive External Components
High voltage MOSFETs generally have low gate-charge capacitance. As a result, they can be driven di rectly from the IC. The
CS1501 & CS1601 are designed to function as power factor corre cted SMPS working in discontinu ous mode (DCM). They are
best suited for supplies less than150 W. With relatively low switching frequencies (<70kH z) and l ow switching current, the b enefits of having very fast rise & fall times is reduced.
- The simplest implementation is a low-value resistor (~10 Ω) in series with the driver & MOSFET gate. (Option A.)
- Efficiency can be improved by adding a diode in parallel with the resistor. (Option B.) This turns the MOSFET off quickly,
and reduces the I – V losses as the voltage rises while current is still flowing.
- Adding a small-signal PNP transistor further reduces turn off time. (Option C.)
4. PCB Layout
The IC should be placed as close as possible to the MOSFET, with a short, direct connectio n from the driver to the gate . The
return path from the FET source to the IC should also be minimal. This reduces issues with PCB trace impedance interfering with
the drive — both resistive and inductive. For further details, please refer to Cirrus Logic application note AN350, CS1601 Layout
Guidelines.
5. Summary
Simple gate drive structures are sufficient for most PFC applications. A choice from one of the sch emes listed above wi ll work,
with focus on following basic layout rules.
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6. Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com
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Revision Date Changes
REV1 MAR 2011 Initial Release.
AN352
4 AN352REV1
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