Cirrus Logic AN339 User Manual

AN339

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Figure 1. DAC THD+N

CS8414

CS8416

CS8416 Delivers Performance Gains Over CS8413/14

Jonathan Schwartz

1. INTRODUCTION

The CS8413/14 S/PDIF receivers have long held a position of respect as the industry-favored receivers for recovered clock quality. As of early 2009, an upcoming end-of-life of these products has many system designers wondering what their next move will be, and where they’ll go to get the level of performance they’ve become accustomed to. Others simply need 192 kHz support, which the CS8413/14 does not provide.

Satisfying both of these requirements, Cirrus Logic offers the CS8416 S/PDIF receiver with new features and lower recovered clock jitter than the CS8413/14.

When the CS8416 was first released in 2002, it used a phase detector scheme that resulted in higher recovered clock jitter compared to the CS8413/14. To improve on its performance and follow in the tradition of the CS8413/14, a new phase detector option wa s added to the CS8416 in 2004. This new option offers even lower recovered clock jitter than the CS8413/14 and results in measurably improved audio performance as shown in Figure 1.

This application note details how the CS8416 improves upon the performance of the CS8413/14. A summary of important functional differences and detailed jitter and audio performance measurements are included to clearly demonstrate the improvements that can be expected when transitioning to the CS8416.

2. SUMMARY OF IMPROVEMENTS

Many improvements were made in the generational leap from the CS8413/14 to the CS8416. For reference, some of the high-level improvements are summarized in the table below. For more information, please refer to each device’s datasheet.

Maximum Sample Rate 96 192 kHz Baseband Jitter (Note 1) 158.5 122.6 (Note 2) ps Logic Supply Voltage Range 5 3.3 - 5 V Power Supply Consumption 175 47.5 mW Back-up System Clock During Receiver Error None OMCK pin Receiver Input Pins 1 8 in SW Mode, 4 in HW Mode Dedicated Reset Pin None Yes Control Port Protocol Parallel Port, CS8413 Only I²C and SPI -

Notes: 1. Values listed are from experiment results. See Section 5

2. PDUR=1. See Section 3

http://www.cirrus.com

Parameter CS8413/14 CS8416

Table 1. Summary of CS8416 Improvements

Unit

JUL '09

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General Enhancements

• Optional automatic enable of de- em p ha sis filte r based on channel status bits.

• Dedicated S/PDIF receiver pass-through pin.

• Selectable recovered master clock frequency of 256 x Fs or 128 x Fs.

• SOIC, TSSOP, and QFN package options.

• Available in automotive grade.

Software Mode Enhancements

• Three configurable GPO pins.

• Data output muting capability.

• Data format detection and reporting.

• Channel status register update inhibit function.

• User data Q-channel subcode deco d i ng into reg isters.

• IEC61937 Pc/Pd burst preamble registers.

Phase

Comparator

VCO

Recovered

Mast er Clock

Input

LPF

÷N

Figure 2. PLL Block Diagram

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Beyond those listed in the table, several other no table enhancements are available in the CS8416:

There are a number of other differences between the CS8 413/14 and the CS8416 that a designer con sidering a transition from the CS8413/14 to the CS8416 should be aware of. For reference, a list of some of the more significant differences is included in Section9.1 on page10.

3. BASICS OF CLOCK RECOVERY

The purpose of a S/PDIF receiver is to convert a 1-wire S/PDIF inpu t signal containing both clock and d ata information into discrete serial audio clock and data signals. A phase-locked loop (PLL) is used to derive a system clock signal synchronous to the S/PDIF stream, and digital logic is used to decode the data.

In some limited applications, a S/PDIF receiver is used to source data into a purely digital system where clock jitter needs to be only good enough to operate the internal digital components. However, the vast majority of systems with a S/PDIF receiver also contain a D/A converter, an A/D converter, or a combination of the two, all being clocke d by the PLL recovered system clock generated by the S/PDIF receiver. In these systems, the jitter performance of the S/PDIF recovered clock is of extreme importance because it has a direct impact on the system’s analog audio performance.

clock frequency is adjusted by the error signal voltage until the ou tput clock frequency matches th e input. The feedback loop contains a frequency divider so that the output clock frequency can be a multiple of the input frequency.

The amount of jitter present on the recovered clock is dependent on the characteristics of the PLL that generates the clock. Since the CS8413/14 and CS8416 have different PL Ls, the jitter on their recovered clocks is expected to be different as discussed in the following section.

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As a result, an important qualifying factor for a S/PDIF receiver is the performance of its r ecovered clock. If the S/PDIF receiver does not provide a low-jitter recovered clock, then any converters that use the clock for sampling can be expected to exhibit reduced performance as a result.

The basic block diagram of the PLL is shown in

Figure 2. The PLL uses a negative feedback loop

to compare the phase of the input clock to that of the output clock. The resulting error voltage signal is low pass filtered and sent to an internal voltage-controlled oscillator (VCO). The VCO output

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Time (seconds)

VCO

Frequency

(MHz)

Ideal VCO Frequency

Phase Detector

Update Rate

VCO Jit t e r

Figure 3. Slow Phase Detector Update Rate

Time (seconds)

VCO

Frequency

(MHz)

Ideal VCO Frequency

Phase Detector

Update Rate

VCO Jitter

Figure 4. Fast Phase Detector Update Rate

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4. CS8413/14 AND CS8416 CLOCK RECOVERY COMPARED

The primary difference between the CS8413/14 and CS8416 PLLs is foun d in the input source to each PLL’ s phase detector block. In each of these devices, digital logic analyzes the incoming biphase enco ded S/PDIF stream to generate pulses that serve as the input to the pha se comparator. The frequency of th ese pulses is referred to as the phase detector update rate.

The more often the phase detector is updated, the more often the VCO output frequency is corrected to match the frequency of the input S/PDIF signal. A slower update rate allows the VCO frequency a greater degree of wander, leading to increased low frequency (audio-band) recovered clock jitter. See Figure 3 and Figure 4.

In practice, the CS8413/14 detector is updated once per bit of the input S/PDIF signal; thus the update rate is da ta dependent 64 times the input sample rate. With an update rate of this frequency, the CS8413/14 has good audio-band output jitter.

When the CS8416 was first released in 2002, its digital logic was designed to update its phase detector only once per subframe of the S/PDIF input signal, or at 2 times the input sample rate. This was done as a measur e desig ned to support 192 kHz sample rates and to reduce data dependency. The unfortunate result of this slower update rate was higher audio-band jitter present on the recovered master clock.

To address this issue and improve upon the CS8416 and CS8413/14, in 2004 a new phase detector update rate option was added to the CS8416.

When enabled, the newer update rate option causes the phase detector to be updated on every edge of the biphase S/PDIF input signal; thus the update rate is data dependent from 64 to 128 times the input sample rate. This new detector lowers the audio-band r ecovered clock jitter and results in improved converter performance.

It’s important to note that the maximum sample rate is limited to 108 kHz in this newer mode. The different detector modes in the CS8416 are selected by the Phase Detector Update Rate (PDUR) control. PDUR set low (‘0’) selects the original and slower update rate, while PDUR set high (‘1’) selects the new fast update rate. The PDUR setting can be accessed at start-up through the TX pin in hardware mode, or in register 00h in software mode.

Since the CS8416 with PDUR = 1 has the same update rate or faster than the CS8413/14, the CS8416 is expected to have lower audio-band recovered clock jitter. Section 5 below details the results of jitter measurement tests that empirically support this conclusion.

5. MEASURED JITTER COMPARISON

Although there are several d ifferent jitt er spe cification s used to quantify the jitter present on a clock signal (period, cycle-to-cycle, etc.), they are not all useful for correlating measured jitter to the THD+N performance of an audio converter that uses the measured clock signal to drive its sampling circuits.

The best jitter specification for this correlation is ‘baseband jitter’ as defined in section 3.4.2 of AES-12id-2006. A baseband jitter measurement band-passes the measured jitter signal, calculating the jitte r amplitude over a frequency band from 100 Hz to 40 kHz. Jitter outside of this frequency band is said to have no effect on the THD+N performance of an audio converter because the resulting modulation tones will either be psycho-acoustically masked (jitter less than 100 Hz) or higher than the upper limit of the 20 kHz audio band (jitter greater than 40 kHz).

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Sample

Rate

CS8414

CS8416

PDUR=1

CS8416

PDUR=0 Unit

48 kHz 158.5

(Figure 5)

122.57

(Figure 7)

531.41

(Figure 9)

96 kHz 1 11.01

(Figure 6)

45.278

(Figure 8)

212.35

(Figure 10)

192 kHz - - 215.43

(Figure 11)

Table 2. Baseband Jitter - Summary

Figure 5. CS8414 MCK Phase Noise

Fs = 48 kHz

Figure 6. CS8414 MCK Phase Noise

Fs = 96 kHz

Figure 7. CS8416 RMCK Phase Noise

Fs = 48 kHz, PDUR = 1

Figure 8. CS8416 RMCK Phase Noise

Fs = 96 kHz, PDUR = 1

Figure 9. CS8416 RMCK Phase Noise

Fs = 48 kHz, PDUR = 0

Figure 10. CS8416 RMCK Phase Noise

Fs = 96 kHz, PDUR = 0

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Each receiver, including both of the CS8416 phase detector update modes, was tested with input S/PDIF sample rates at common values of 48 kHz and 96 kHz. Additionally, the CS8416 was tested at 192 kHz with PDUR = 0.

The resulting baseband jitter measurement data is presented in Table 2. Phase noise plots showing the measured jitter signal on the receivers’ recovered clocks are displayed in Figures 5 through 11. Refer to Section 9.2 for detailed test set-up information and diagrams.

The highlighted portions of each plot denote the 100 Hz to 40 kHz bandwidth specified by the AES-12id-2006 baseband jitter definition. As the definition suggests, the magnitude o f the hig hlighted portion of the plots corr elate to audio-band converter THD+N performance. Thus, the lower the magnitude, the better the converter performance.

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