Cirrus Logic AN331 User Manual
AN331
Increasing ADC Dynamic Range with Channel Summation
by
Steve Green
1. Introduction
A commonly used technique to increase the system dynamic range of audio converters is to operate two converter
channels in parallel with the same signal and sum the outputs. The summation of the correlated signals creates a
6 dB increase in signal level while the summation of the uncorrelated noise sources increases the noise level by
only 3 dB. This summation effectively results in a 3 dB increase in dynamic range compar ed to each individual channel. This technique is most commonly associat ed w ith digit al- to -ana lo g co nve r ter s bu t is als o ap p licab le to an alo g to-digital converters; as presented at the 87
A/D Converter, with 19-bit Mono Application Example” by Clifton Sanchez of Crystal Semiconductor. In the case of
an A/D converter, it may be necessary to divide each of the digital signals by two prior to sum mation to avoid signal
overload in the processor. This approach is shown in the eq uations below, where A repre sents the signal in channel
A, B the signal in channel B and e
e
= A/2 + B/2
o
is the summed signal.
0
th
AES Convention, “An 18-bit Dual Channel Oversampling Delta-Sigma
If A = B
eo = A/2 + A/2
e
Another approach, which achieves the identical mathematical results, is to invert one of the analog inputs prior to
conversion and perform a subtraction of the two independent digital outputs. The advantage of this approach is that
any common in-phase signal between the individual digital output signals that may be introduced during the conversion process (e
e
If B = - A
eo = ((A + eN) / 2)) - ((-A + eN) / 2)
e
Though applicable to any A/D converter summing channels, using either technique, to increase dynamic range is
generally implemented in applications requiring the ultimate in dyna mic range. As a result, this technique is generally
utilized with the highest performance A/D converters that are available. This application note will demonstrate an
implementation using the CS5381, which achieves 120 dB dynamic range for each individual channel in a standard
two-channel configuration, to achieve 123 dB dynamic range.
= A
o
) is cancelled in the subtraction. This approach is shown in the equations below.
N
= (A + eN) / 2) - (B+ eN) / 2)
o
= A
o
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AUG ‘08
AN331REV1
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AN331
2. Implementation Requirements for the CS5381
The block diagram shown in Figure 1 shows an implementation of the CS5381 A/D. Notice that the same analog
signal is applied to each of the A/D converters within the CS5381. The require d mathematical opera tion is th en performed in either a Digital Signal Processor (DSP) or Field Programmable Gate Array (FPGA).
It is very important to note that the addition (or subtraction) must be performed with synchronously sa mpled and time
aligned data pairs. Within the serial audio interface, the Left followed by Right cha nnel data pairs are synchronously
sampled data. However, the Right followed by Left channel data pairs are shifted in time by one sample period relative to each other and the addition or subtraction of these pairs will produce erroneous results. Please refer to the
Cirrus Logic application note AN282 “The 2-Channel Audio Interface: A Tutorial” for more information concerning
the serial audio interface and synchronously sampled data pairs.
Analog Input
CS5381
Right Channel A/D
Serial Audio Interface
CS5381
Left Channel A/D
Figure 1. Mono-Mode Block Diagram
Data
Processing in
DSP or FPGA
Mono-Channel
Output
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AN331
3. Recommended Analog Input Buffers for the CS5381 in Mono-Mode
An implementation with the CS5381 requires separate inpu t buffer stages for th e differential analog in puts. A single
buffer driving both differential inputs has been shown to result in an unacceptable level of distortion. The recommended buffer topologies are near ly id entical to th at shown on the CS5381 evalua tio n board , CDB538 1. The schematic in Figure 2 is a suggested buffer implementation for the equation e
connection is routed to the AINR+ and the AINL+, and the AIN- connection is routed to the AINR- and the AINLwhich results in the signals being in-phase.
634 Ω
470 pF
COG
+
= A/2 + B/2. Notice that the AIN+
o
91 Ω
AINR+
COG
2700 pF
AIN+
AIN-
10 uF
100 kΩ
10 uF
100 kΩ
+
10 kΩ
10 kΩ
+
-
634 Ω
470 pF
COG
VQ
470 pF
COG
91 Ω
91 Ω
+
-
91 Ω
AINR-
470 pF
COG
634 Ω
AINL+
COG
2700 pF
AINL-
634 Ω
Figure 2. CS5381 Recommended Buffer Implementation for Non-inverting Configuration
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