Cirrus Logic AN314 User Manual

AN314

Multiplexing the CS556x/7x/8x Delta-Sigma ADCs

1. INTRODUCTION

The CS556x/7x/8x devices represent a new generation of delta-sigma analog-to-digital converters that compete with SAR (successive approximation register) converters, with some distinct advantages. The unique features of these over-sampling converters allow them to be multiplexed at high speed across many input channels, because every conversion produces a fully settled result. In this application note the similarities and differences between SAR converters and the CS556x/7x/8x family of ADCs will be discussed as well as some design tips on choosing the right multiplexer and input amplifiers to drive these ADCs.

2. COMPARING THE CS556X/7X/8X WITH A SAR

Typically SAR ADCs have been used in the past for any high-throughput multiplexed application. This is because most delta-sigma converters require multiple conversions to fully settle. In other words, a large step change on the input takes a considerable amount of time to be reflected accurately (settled) in the output of the digital filter. Most delta-sigma converters use single-bit modulators and sample at kilohertz rates, and many samples are required as input to the digital filter to achieve the required accuracy. The CS556x/7x/8x family of converters is unique in that the modulator output is multi-bit and the sample rate is 8 MSps (megasamples per second). This, in combination with a specially designed FIR filter that only takes a few clock cycles to compute a result, produces a converter that can fully settle in a single conversion.

There are several distinct advantages of delta-sigma converters over SAR converters such as their superior DNL (differential non-linearity) performance and excellent noise immunity. One of the main reasons for the increased noise immunity is that the digital filter attenuates the out-of-band noise. However, a SAR ADC typically has a bandwidth much higher than Nyquist, and out-of-band noise can alias down into the pass band. Another reason is that a SAR converter samples the input signal once per conversion (Figure 1a) while the delta-sigma converter averages many samples per conversion (Figure 1b). As can be seen in Figure 1a, a noisy input signal (one with noise transients as illustrated) can result in significant errors within a SAR ADC unless multiple conversions are taken and averaged in software. In Figure 1b, the delta-sigma converter does this internally in the digital filter resulting in a conversion much less susceptible to transient noise.

Error

}

Noise

Figure 1a. SAR ADC Sampling (One Sample per Conversion)

Noise

http://www.cirrus.com

Figure 1b. Delta-Sigma ADC Sampling (Many Sample per Conversion)

AUG ‘07

AN314REV1

AN314

3. REQUIREMENTS FOR MULTIPLEXING THE CS556X/7X/8X

For higher-throughput in multiplexed applications, it is desirable for the converter to fully settle on each conversion. In other words, the digital filter's output must accurately reflect the analog value on the input during the conversion. Additionally, the input multiplexer and any buffer amplifiers must be settled to the full accuracy of the converter before the samples are taken. This requires both the converter and the analog input circuitry to be fast settling. This is especially true if any amplifier or anti-aliasing resistor and capacitor is placed between the multiplexer and the ADC as illustrated in Figure 2. With a multiplexer it is possible for the ADC input to see a full-scale change from one conversion to the next. Any amplifier, or RC time constant due to resistance and capacitance, between the multiplexer and the ADC must fully settle to the new value before the sampling begins.

AIN1

AIN2

AIN3

MUX

AMP

ADC

AIN4

Figure 2. Amplifier and Filter between Multiplexer and ADC

With high-throughput converters like the 50 kSps CS5560/61, 100 kSps CS5570/71, or the 200 kSps CS5580/81 the circuit must settle in less than 10 MCLK periods (625 nanoseconds). The multiplexer before a SAR converter can be switched to the next channel after the conversion begins since the signal has already been sampled. However, many SAR ADC data sheets warn that a certain "quiet" period should be observed to prevent coupling of noise. The CS556x/7x/8x requires that the multiplexer be switched at the end of the conversion, since it is taking multiple samples of the input signal during the conversion (see Figure 3).

Analog Input must be settled here.

If CONV is held low , input must be

settled within 10 MCLKs after RDY falls.

CONV

RDY

See data sheet for specific timing

Therefore, an alternative should be considered where the amplifiers and anti-aliasing capacitors are on the input of the multiplexer. This generally requires a multiplexer with very low “on” resistance but the benefits are that the amplifier(s) and RC networks do not have to settle from possible large step changes when the multiplexer switches to another input. Figure 4 illustrates this arrangement.

2 AN314REV1

CS 5560/ 61 –304 MCLKs CS 5570/ 71 –144 MCLKs CS 5580/ 81 – 64 MCLKs

Switch MUX here

Figure 3. Multiplexer Timing Requirements

AIN1

AN314

AIN2

ADC

MUX

AIN3

AIN4

Figure 4. Amplifier(s) and Filter(s) Placed Before Multiplexer

As illustrated, not every input may require an amplifier or buffer. This is because there is an on-chip buffer in the CS556x/7x/8x. This rough charge buffer minimizes the sampling current on the input by charging the internal sample capacitor to a value very close to the input voltage using current from the supply pins rather than the input pin. This results in much higher effective impedance on the analog input. Where the full-scale range needs to be changed, an amplifier with gain or attenuation can be used.

4. SELECTING A MULTIPLEXER

There are several key parameters that need to be considered when selecting a MUX device. These include the “on” resistance, on/off capacitance, and switching speed. The on resistance should be as low as possible in order to assure that the input of the ADC fully settles on every sample. The inputs of modern converters consist of an analog switch and a sample capacitor. For most SAR converters this sample capacitor (or array of capacitors) is in the 70 pF to 100 pF range and must be charged once per conversion. For the CS556x/7x/8x, the input sample capacitor is only 4 pF but it is sampled once every 125 nanoseconds (8 MHz sample frequency). The CS556x/7x/8x also includes a rough-charge buffer which charges the sample capacitor to near its final value before switching the sample capacitor directly to the input pin for the fine-sample period. This greatly increases the effective input impedance of the device. However, this fine-sample period is only 20 nanoseconds out of each 125-nanosecond sample period, so excessive resistance in the input path may result in inadequate settling. Another reason the on resistance should be kept low is that the on resistance of a multiplexer is nonlinear across the full-scale range of the ADC and this may result in distortion. The lower the on resistance, the less distortion will result from this nonlinearity. As a general rule, an on resistance of less than 10 ohms should be used in order to minimize settling delays in charging the sample capacitance of the ADC.

The second parameter that should be considered is the channel capacitance or the on and off capacitance of the multiplexer. Typically the inputs or source of a multiplexer have a capacitance of 5 pF to 20 pF when the switch is open. However, when an input switch closes, additional capacitance is added from the other analog-switch channels that are part of the multiplexers output/drain. This capacitance typically increases as the number of multiplexer inputs increase. For example, a 16-to-1 MUX will usually have a higher drain capacitance than an 8-to-1 MUX. What needs to be considered here is that the output-channel capacitance will always be charged to the previously

AN314REV1 3

+ 7 hidden pages