Cirrus Logic AN312 User Manual

AN312
CobraNet® Clocking Modes

1. INTRODUCTION

In most cases, a CobraNet® system is used with its default audio clocking mode (0x00). This allows automatic syn­chronization of audio clocks network wide. However, the clocking circuitry of a CobraNet device can be configured to operate in a number of ways that are specified by the values written to the syncConductorClock and syncPerform­erClock Management Interface (MI) variables. These two MI variables are used independently to set the clocking mode of an interface depending on whethe r it is operating as a Conductor or a Performer. These variables can be set by using SNMP or the Host Management Interfac e (HM I) .
Please see the CobraNet Programmer's Reference Manual formation on the variables, SNMP, and the Host Management Interface.

2. IMPORTANT CONCEPTS REGARDING CobraNet CLOCKING

All devices in a CobraNet network must operate within the same clock domain. It is therefore a requirement that, regardless of clock mode, all audio clocks on the network should be derived from the same master clock to ensure that they remain synchronized. This is accomplished automatically when using the default clock mode, 0x00, and when any digital devices attached to the CobraNet interface receive their audio clocks from the CobraNet interface.
Any CobraNet interface that uses one of the external clocking modes must use external clocks that are syn­chronous with the network audio clock.
and the CobraNet Hardware User's Manual for more in-
A digital audio device that does not receive its audio clocks from th e CobraNet inte rface must be connected to the CobraNet interface using a sample rate converter. For instance, all digital audio devices connected to CobraNet devices must be in the same audio clock domain as the CobraNet network.
Any clock mode that uses the external word clock (REFCLK_IN) will not work unless the REFCLK_IN pin is first enabled by clearing the second bit (bit 1) of the syncBuddyLinkControl MI variable.

3. CORE CLOCK CIRCUITRY OF A CobraNet INTERFACE

The core clock circuitry of a CobraNet interface is depicted in Figures 1 and 2. Note that not all inputs and outputs to the clock module are used at the same time in all modes. Op eration of the circuitry, a nd activity on each path, are dependent on the clock mode selected. These different clocking modes can be used in many ways, depending on the requirements of a particular application. Common usage of the different modes is described in this document. The user-available external clock connections are REFCLK, MCLK_IN, MCLK_OUT, FS1, and SCLK. The other connections are internal to the interface and utilized by the interface's firmware in response to the particular mode in use.
The five audio clock modes are:
0x00 - Internal (Normal Default Mode)
0x10 - Internal with External Sample Synchronization
0x01 - External Word Clock
0x04 - External Master Clock
0x14 - External Master Clock with External Sample Synchronization
Copyright © Cirrus Logic, Inc. 2008
http://www.cirrus.com
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MAY 08
AN312REV2
MCLK_OUT (master)
AN312
DAC
MCLK_IN
MCLK_SEL
REFCLK_Enable
REFCLK_Polarity
REFCLK
Beat Received
Clock Config
Signal
Path
Control
Path
control
VCXO
24.576MHz
+/- 100 PPM
Clock
Out
MCLK
MUX
Edge
Detect
RST
Beat MUX
Sample
Phase
Counter
Hardware FPGA Software

Figure 1. - CobraNet Clock Circuit for CM-1 Module

Audio Clock
Generator
Phase
Detector
FS1 (word)
SCK (bit)
Loop Filter
DAC
MCLK_IN
MCLK_S EL
REFCLK
Beat Received
Clock Config
Signal
Path
Control
Path
control
VCXO
24.576MHz
+/- 100 PPM
Clock
Out
MCLK
MUX
Beat MUX
Sample
Phase
Counter
External
Hardware
Audio Clock
Generator
CobraNet Processor

Figure 2. CobraNet Clock Circuit for CM-2 Module and Semiconductors

Phase
Detector
MCLK _OU T (m aster)
FS1 (word)
SCK (bit)
Loop Filter
Software
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3.1 CobraNet Clock Modes

This section describes each of the CobraNet clock modes.

3.1.1 0x00 Mode - Internal Mode (Default)

The 0x00 Mode is the default clock mode of a CobraNet interface. When operating in this mode:
As Conductor: The master audio clock (MCLK) is generated by the VXCO parked at its center fre­quency. Word clock (FS1) and bit clock (SCLK) are derived directly from MCLK.
As Performer: The master audio clock (MCLK) is generated by the VXCO, which receives frequency adjustments from the beat packets received from the Conductor node over the network interface, in­suring that the Performer's clock is in sync with th e Conductor. Wo rd clock (FS1 ) and bit clock (SCLK) are derived from MCLK.
MCLK_OUT
(Master Audio
(
DAC or ADC
Clock)
S
F
c
R
L
AN312
1
c
l
)
o
k
CobraNet Int erface
DAC
MCLK_IN
MCLK_SEL
REFCLK _Enable
REFCLK_Polarity
REFCLK
Beat Received
Clock Config
control
SCLK
(Bit clock)
Figure 3. 0x00 Mode Typical Connections
VCXO
24.576MHz
+/- 100 PPM
Clock
Out
MCLK
MUX
Edge
Detect
RST
Beat MUX
Sample
Phase
Counter
Audio Clock
Generator
Phase
Detector
MCLK_OUT (master)
FS1 (word)
SCK (bit)
Loop Filter
Signal
Path
Control
Path
Active Signal
Path
Hardwa re FPGA Software
Figure 4. Clock Circuit as Used by 0x00 Mode with CM-1 Module
AN312REV2 3
DAC
MCLK_IN
MCLK_SEL
REFCLK
Beat Received
Clock Config
control
VCXO
24.576MHz
+/- 100 PPM
Clock
Out
MCLK
MUX
Beat MUX
Sample
Phase
Counter
Audio Clock
Generator
Detector
Phase
MCL K_O U T (m aster)
FS1 (word)
SCK (bit)
Loop Filte r
AN312
Signal
Path
Control
Path
Active Signal
Path
External
Hardware
CobraNet Processor
Figure 5. Clock Circuit as Used by Mode 0x00 with CM-2 and Semiconductors

3.1.2 0x10 Mode - Internal Mode with External Sample Synchronization

Note: This will not work properly with CM-2 modules or semiconductor-based designs due to the ab­sence of the edge detect circuit in the semiconductor.
This mode is similar to Internal Mode (0x00), but allows synchronization of the derived SCLK and FS1 signals with external clock circuits. It is typically used when it is necessary to sync hronize CobraNet clocks with existing external clock circuitry. When operating in this mode:
As Conductor: MCLK, FS1, and SCLK are all generated as in 0x00 Mode. Howeve r, the REFCLK in­put is used to align the clock edges of the generated MCLK, insuring that the audio clocks generated externally are kept in sync with the CobraNet inte rface's audio clocks. This mode does not alter the clock frequency and implies that the REFCLK input should be derived from the MCLK_OUT supplied by the CobraNet interface (see Figure 6).
As Performer: MCLK is generated by the VXCO, which receives frequency adjustments from the beat packets received over the network interface as in 0x00 Mode. FS1 and SCLK are derived from MCLK. As above in Conductor Mode, the REFCLK input is used to ensure that the external and CobraNet gen­erated audio clocks are in sync.
Softw a re
SCLK
Clock Circuit
Clock In
FS1
24.576 MHz MCLK_OUT
FS1
REFCLK
CobraNet Interface
Figure 6. 0x10 Mode Typical Connections (Sync of CobraNet Clocks with External Clock Circuitry)
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3.1.3 0x01 Mode - External Word Clock

External Word Clock Mode allows synchronization of all CobraNet clocks with an externally supplied word clock. The external clock can be any integral division of FS1 from 750 Hz to 48 kHz. This is most often used to synchronize a CobraNet network with a house sync signal whereby the Conductor will supply the network clock and operate in this mode with Performer Nodes operating in 0x00 Mode. When operating in this mode:
As Conductor: The VCXO generating MCLK is steered to synchronize with REFCLK. FS1 and SCLK are derived from MCLK.
As Performer: The VCXO generating MCLK is steered to synchronize with REFCLK. FS1 and SCLK are derived from MCLK.
FS1
SCLK
MCLK_OUT
AN312
CobraNet Interface
(External Word Clock Mode)
(conductor)
From house sync
Figure 7. 0x01 Mode Typical Connection (External Sync Attached to Conductor)
Note: Connection used to provide synchronized audio clocks via Ethernet
REFCLK
FS1
SCLK
CobraNet Interface
(External Word Clock Mode)
From house sync
Figure 8. 0x01 Mode Typical Connection - External Sync
MCLK_OUT
REFCLK
(conductor)
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