Cirrus Logic AN306 User Manual

PCM

Serial

Interface

Serial Data Input

Right Channel Output

Left Channel Output

Left-Right Clock

Master Clock

Interpolation

Filter with

Volume Control

Interpolation

Filter with

Volume

Control

Multibit ΔΣ

Modulator

Multibit ΔΣ

Modulator

Amp

Filter

Amp

Filter

DAC

Serial Clock

Figure 1. Typical DAC Architecture with Master Clock Input

PCM

Serial

Interface

Serial Data Input

Right Channel Output

Left Channel Output

Left-Right Clock

Recovered MCLK

Phase

Locked

Loop

Interpolation

Filter with

Volume Control

Interpolation

Filter with

Volume

Control

Multibit ΔΣ

Modulator

Multibit ΔΣ

Modulator

Amp

Filter

Amp

Filter

DAC

Serial Clock

Internal MCLK

Figure 2. CS4350 PLL DAC Architecture

AN306

Simplifying System Design Using the CS4350 PLL DAC

1. INTRODUCTION

Typical Digital to Analog Converters (DACs) require a high- speed Master Clock to clock their digital filter s and modulators, as well as some portions of their discrete time analog circuitry. This Master Clock (or system clock) is typically required to be synchronous to the left-right (frame or word) clock (LRCK) in order to maintain sample alignment in the digital filters, state machines, modulator and discrete time analog sections. Figure 1 below shows an example of a typical DAC clocked by an external Master Clock. The clock is applied to the MCLK pin and then distributed to any internal logic that requires it.

As an alternative, PLL DACs are designed to derive their internal synchronous Master Clock from some other external source. This source could be any clock, but in practice it is commonly a video clock (27 MHz) or one of the slower SCLK or LRCK signals which are mandatory for typical PCM audio interfaces (See AN282 “The 2-Channel Serial Audio Interface: A Tutorial”). In practice, the CS4350 PLL DAC generates its Master Clock from the input leftright clock. Figure 2 shows the CS4350 PLL DAC architecture; from the input LRCK signal, the internal PLL derives the Master Clock signal that is used to drive the internal system timing.

The internal Master Clock generation of a PLL DAC yields inherent benefits that simplify the design of audio systems. The CS4350’s unique implementation of the feature ta kes the concept a ste p further to provide an even grea ter degree of design simplicity, flexibility, and performance.

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2. SIMPLIFIED SYSTEM DESIGN

In the design and layout of an audio mixed signal system, the conditioning and routing of the clocks are one of the most important considerations. Because a converter’s Master Clock signal provides the sample clock that is used as the time base for its modulator and switched ana log filters, it is typically the most sensitive to jitter and clock coupling. Eliminating the need for an external Master Clock signal provides for easier signal routing, reduced potential for electromagnetic interference (EMI), and improved jitter immunity.

2.1 Eased Signal Routing

The Master Clock is typically generated in the digital section of a mixed signal system. This high-speed clock then needs to be routed across the board to the an alog or mixed signal section in order to p rovide the master clock for the converters. Since the CS4350 PLL DAC does not require a Master Clock input signal, it does not need to be routed across the system board to re ach the conver ter. This eases the routing necessary for the remaining clocks.

2.2 Reduced Potential for EMI

The Master Clock is typically the fastest clock used by a mixed signal audio converter. Routing any highspeed clock takes careful consideration in order to keep EMI to a minimum. The CS4350 PLL DAC provides an easy way to ease EMI concerns by removing the dependency on the Master Clock, thus reducing the number of high-speed clocks necessary to implement an audio subsystem.

2.3 Improved Jitter Immunity

As system designs become increasingly complex, the system clocking sources also become increasingly complex. In many designs, the system clock is derived from a PLL within a large SOC (System on a Chip), and is often used as the Master Clock source for the audio converters. The clocks generated from such SOCs often exhibit high amounts of jitter, primarily as a result of the many asynchronous operations within the SOC coupling into the clock signal. This high amount of jitter often limits the distortion (THD+N) performance and dynamic range of the mixed signal systems that use the SOC generated system clock.

Because the CS4350 PLL DAC generates its Master Clock internally, the jitter on an SOC or other system clock source is of no consequence. When locking to LRCK, the CS4350’s PL L can reject any high-frequency jitter that may be present on the slower LRCK.

3. LOCKING TO LRCK

The CS4350’s PLL locks to the incoming LRCK signal, and locking to LRCK provides some noteworthy advantages over locking to another clock in the system. Specifically, locking to a system or video clock requires routing a highspeed clock to the converter and does not provide the EMI and routing advantages of locking to LRCK. Locking to LRCK also provides for improved jitter rejection due to the lower native frequency of the left-right clock; this allows a lower high-pass corner to be achieved in the PLL’s loop filter. When locking to LRCK, no other clocks are needed beyond those already required in the serial PCM interface (SCLK, LRCK, and SDATA).

4. NO EXTERNAL LOOP FILTER COMPONENTS

A typical PLL consists of a phase comparator, ch arge pump, loop filte r and a VCO. The loo p filter creates an ana log filter for the internal VCO control signal. Many PLLs require the loop filter components (typica lly two capacitors and a resistor) to be external to the device because of internal size constraints. The CS4350 PLL uses a PLL configuration that requires no external PLL loop filter components. This allows the converter’s PLL to be self-sufficient and also reduces the implementation cost in terms of external component price and total integration area.

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