Cirrus Logic AN301 User Manual

AN301

Time Division Multiplexed Audio Interface:

A Tutorial

INTRODUCTION

Transferring multiple channels of digital audio data within an audio product can be a challenge. The complexities
involving signal routing and providing a sufficient number of input/output ports on digita l-signal-processors and con­verters can be a daunting task. As a result, the industry has adopted a Time Division Multiplexed (TDM) interface
that allows multiple channels of data to be transmitted on a single data lin e. The TDM inte rface is by fa r the most
common mechanism used to transfer multiple channels of audio data betwe en devices withi n a system as shown in

Figure 1. The TDM interface has not been standardized and there can be variants between the TDM formats. For-

tunately the TDM ports in DSP devices are programmable and will support the multitude of options.
It is advantageous to limit the degrees of flexibility in a TDM interface for analog-to-digital converters, digital-to-an-

alog converters, multiple function audio CODECs and other high-performance mixed-signal products to avoid po­tential performance degradation due to clock interference. As a result, Cirrus Logic has chosen to standardize on a
TDM format for audio converter products and support a subset of the options that are available with DSP devices,
including the DSP products from Cirrus Logic. The goal of this document is to present an overview of the TDM in­terface and a discussion of the TDM format that is supported in Cirrus Logic audio converter products.

Multi-Channel

Analog-to-Digi tal Converter

Frame Sync

Serial Clock

Serial DataSerial Data

DSP

Figure 1. TDM System Block Diagram

Multi-Channel

Digital-to-Analog Conve rter

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SEPTEMBER '06

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1. TDM OVERVIEW

The TDM interface is similar to the 2-Channel Serial Audio Interface, discussed in Cirrus Applications Note AN282,
with the exception that more channels, typically 4, 6 or 8, are transmitted within a sample frame or sample period,
as shown in Figure 2. As with the 2-Channel Serial Audio Interface, the TDM interface is comprised of two control
clocks, a frame synchronization pulse (FSYNC) and serial clock (SCLK), and the serial audio data line (SDATA).

Frame

FSYNC

SCLK

SDATA

Channel 1

Channel 2

Figure 2. Generic TDM Interface

1.1 Channel Block

Each channel block is comprised of the audio data word followed by a sufficient number of zero data bits to
complete the N-bit channel block. The example shown in Figure 3 shows a 32-bit chan nel block with 24-bit
audio data. Notice that the audio word is typically transmitted with the Most Significant Bit (MSB) first. The
industry standard for representing Pulse-Coded-Modulation (PCM) audio data is a 16 to 32 bit word (16­and 24-bit are the most common) coded in a two’s-complement format.

MSB

-1 -2

-4 -5

-3

24-Bit Audio Word

-7

-6

Figure 3. 32-Bit Channel Block

1.2 Frame Synchronization Pulse

The function of the FSYNC pulse is simply to identify the beginning of a frame. The beginning is always
indicated by the rising edge of the pulse, as shown in Figure 2. Another notable point is that the frame rate
is always at the audio sample rate, such as 44.1 kHz, 48 kHz, etc.

The majority of the TDM implementations only use the rising edge of FSYNC and ignore the falling edge.
However, device product documentation often implies that the width of the pu lse is important. There are two
common representations for the required width of the FSYNC pulse. The first is a frame synchronization
pulse where the width is equivalent to a channel block. The second is a pulse where the width is equivalent
to a single period of the serial clock. Unfortunately, the product documentation rarely supplies a sufficient
amount of information to determine if the falling edge is used. The safe approach is to follow the product
documentation and assume the falling edge is used or contact the manufacturer for clarification.

32-Bit Channel Block

+3

Channel N-1 Channel N

LSB

+1

+2

8-Bit Zero Pad

1.3 Channel Block Alignment with Frame Sync

There are two common options for the alignment of the first channel block and the rising edge of FSYNC.
The first is shown in Figure 2. where the beginning of the channel block aligns with the rising edge of the
FSYNC. In the second option, the channel block is delayed one per iod of the serial clock following the rising
edge of the FSYNC.

1.4 Serial Clock

The sole purpose of the serial clock is to shift the audio data into or out of the ser ial audio ports. The required
frequency for the serial clock is directly proportional to the system audio sample rate, the number of channel
blocks within a frame and the bit-wi dth of each channel block. As an example, an 8-channel frame with 32­bit channel blocks operating at 48 kHz requires a 12.288 MHz serial clock.

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