Cirrus Logic AN299 User Manual

AN299

Optimizing the Performance of CS553x ADCs

1. INTRODUCTION

Getting optimum performance with high-performance converters is not a trivial task. Good system grounding tech­niques, power supply filtering, careful board layout, and control of system clocks and high-speed digital signals is of
utmost importance. We will cover these and other subjects in this application note in order to allow your design to
get the best performance from the CS5531/2/3/4 converters.

The CS5531/2/3/4 family of Delta-Sigma converters are some of the lowest-noise DC measurement devices in the
market. These devices are suitable for many applications where high-resolution measurements of very small DC
voltages are required, such as weigh scales, pressure transducers, and thermocouples. With a built in, low-noise,
programmable gain amplifier, the full-scale input range can be as low as 39.0625 mV DC in unipolar mode with a

2.5 V or 5 V VREF. As will be demonstrated in this application note, the input scale can be reduced even further,
allowing very small differential inputs to be measured to a high degree of resolution. For example, as explained in
this document, a 10 mV full-scale unipolar input can be measured to 0.596 nV per least-significant bit with the 24­bit devices. Obviously the output will contain noise, but with software averaging, that noise can be resolved to an
impressive number of noise-free bits.

2. THE IMPORTANCE OF A GOOD GROUND PLANE

In order to reduce board costs, some designs may attempt to use single- or double-sided boards and fill unrouted
areas with a ground plane. Please be aware that this is not an effective practice in a high-performance analog-to­digital conversion circuit. A low-noise, low-impedance, uninterrupted ground plane is extremely important in order
to get optimum performance from the ADC. However, filling unused areas around the input traces with copper and
connecting that copper to the ground plane does have some additional advantages regarding Faraday shielding.

The ground plane is the point of reference for many signals on the board. The extremely low-level analog input sig­nals are very susceptible to corruption from noise voltage transients on the ground plane. Since the ground plane is
used to conduct supply and return currents for high-speed signals, it is possible to introduce unwanted noise voltage
drops across the ground plane.

Consider the best possible PCB layout for the simple schematic shown in Figure 1 below.

V+

R1

AIN+

AIN-

R2

C1C2 C4

C3

1
2

5

6
7

8

AIN+
AIN-

CS5534

C1

C2
VA+

VA-

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Figure 1. Analog Input Circuit for a CS5534 ADC

Copyright © Cirrus Logic, Inc. 2006

(All Rights Reserved)

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In this layout C1, C2, and C3 are connected to the ground plane with
three separate vias which may have noise voltage deltas among
them.

Figure 2. Preferred Layout for Minimizing Differential Noise from the Ground Plane

This layout is preferred because all three capacitors are connected to
the ground plane with one via so there can be no noise voltage delta
present.

As illustrated in Figure 2, if a high-speed signal return path or power supply return path flows through the ground
plane in such a way that introduces a noise voltage drop between the point where two capacitors, one on AIN+ and
one on AIN-, connect to the ground plane, a differential noise voltage will be inadvertently applied to the ADC input
through those capacitors.

This does not necessarily mean that, in order to avoid voltage drops across the plane, one should avoid using a
common ground plane for both digital and analog circuitry The debate about whether digital ground and analog
ground should be separated has gone on for years but one thing remains indisputable –

the digital ground (DGND)

pin and any other pin on the ADC that connects to analog ground must be tied together at the ADC via a very low­impedance path. This includes bypass capacitors on the power pins and anti-aliasing and filter capacitors on the
AIN and VREF pins. If separate DGND and analog ground (AGND) planes are used, they must be tied together be­neath the ADC. Also, take great care to prevent clock or high-speed digital signal traces from crossing splits in the
ground plane (or splits in an adjacent power plane). The problem with split or non-continuous planes is that high­speed return currents tend to return to the source in a path that is as close to the active trace as possible. However,
discontinuities in the adjacent ground or power plane force the currents to deviate from that path. This deviation re­sults in “antenna” loops that radiate high-frequency energy as illustrated in Figure 3. Once these signals are radiated
it is very difficult to prevent them from being picked up by the sensitive analog inputs.

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AGND

DGND

Loop antenna effect

radiates high-frequency

energy to other traces

Return Current

High-speed Digital Signal Trace On Adjacent Layer

Figure 3. Antenna Loop Caused by Ground or Power Plane Splits

It is important to note that the CS5531/2/3/4 devices do not have an AGND pin. The common-mode reference for
the analog inputs is VA- (the die substrate). In single-supply configurations it is important that VA- be connected to
the DGND pin through a low-impedance ground plane. In dual-supply configurations the bypass capacitors on VA­and VA+ should be connected to the same ground as the DGND pin through low-ESR (effective series resistance)
bypass capacitors. The reason for this is that any noise differential between these pins will result in noise from the
digital core ground (DGND pin) getting into the internal analog circuitry through the level shifters and parasitic ca­pacitance on the die. Also, any noise differential between the VA- pin and the anti-aliasing capacitors on the analog
inputs will result in common-mode noise being directly coupled to the inputs. Although the ADC has an excellent
common-mode rejection ratio (CMRR) at DC and low frequencies, the higher the frequency of the common mode
noise, the more likely it is that it will be sampled by the ADC and aliased into the pass band. This is especially true
of noise from switch-mode power supplies.

In general, the ADC should be located such that any heavy dynamic currents flowing in the ground plane are kept
away from the converter. This may require that the converter be located on the PCB as far from the power connec­tions as possible. Furthermore, digital IO ports that leave the PCB should
currents these ports often must provide to charge parasitic capacitance on the cabling can create significant noise
differentials in the ground plane. If these guidelines are followed it may not be necessary to use separate analog
and digital ground planes. Therefore the problem of high-speed signals crossing splits in the plane is avoided.

not be located near the ADC. The transient

3. DECOUPLING (BYPASS) CAPACITORS

As noted previously, the choice and placement of capacitors for power supply decoupling is very important. The sup­ply currents to mixed-signal devices are dynamic, not steady-state DC. If this dynamic current was supplied only by
a power source located away from the ADC, very large fluctuations in the voltages at the power pins of the device
would be seen as a result of the series impedances between the device and the power source. Therefore, capacitors
are required at the power pins of the device to act as a reservoir of charge for these dynamic currents. For this rea­son, these capacitors must be located as close as physically possible to the power pins in order to minimize the
series impedance between the power pins and the capacitors. The bypass capacitors for VA+ and VA- should be
between these power pins instead of from each pin to ground since they provide a reservoir of charge between the

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