Cirrus Logic AN273 User Manual

AN273

EP93xx Silicon Rev E

Design Guidelines

1. Introduction

This document is intended to inform customers using EP93xx Rev E0/E1/E2 devices in their designs of certain important considerations. The recommendations contained in this document are le sser-known requ irements of the EP93xx devices. Unless otherwise noted, these guidelines apply for all EP93xx Rev E devices.

This document should be used in conjuction with the particular EP93xx device data sheet and/or user’s guide.

2. Real Time Clock (RTC)

A real time clock (RTC) signal is required to be connected to the EP93xx device. This clock is used by internal logic to boot the device. The EP93xx device will not power up if there is no connection to the EP93xx RTC clock pin(s).

3. RTC External Oscillator Circuit

An external RTC oscillator circuit is required to ensure proper EP93xx power-up and RTC time tracking accuracy. The circuit must provide a clean, symmetrical square wave. For the recommended RTC circuit design, please refer to AN265, which can be found at:

http://www.cirrus.com/en/pubs/appNote/AN265REV2.pdf

4. External Memory Configuration

A problem exists when performing a Sync boot (ADSO=1 when reset is released) with the 32-bit EP93xx device using 16-bit Flash memory and 32-bit SDRAM connected to SDCS3

The EP93xx devices were originally designed to support booting from Synchronous Flash devices such as the AT49LD3200 or the MT28S4M16LCTG-10. These Sync Flash devices were designed to be accessed by an SDRAM controller. They behaved like SDRAM but were actually Flash devices. If one of these Sync Flash devices was used, it was intended to be con nected to SDCS3 figuration would apply the boot memory width to SDCS3 vice was originally designed to use are no longer produced. The EP93xx devices do not sup port the newer Sync Flash devices like the K3 product offered from Intel Corporation.

The EP93xx device latches the state of ASD0 and nCS[7:6] upon reset, alo ng with several other sig nals. If ASD0 is sampled high, Sync boot mode is selected. The EP93xx swaps the address map for nCS0 with nSDCS3. Bits nCS[7:6] specify the data bus width of the boot memory device. Refer the appropriate EP93xx User's Guide for more detail on boot modes.

. These Sync Flash devices that the EP93xx de-

. That way, the boot con-

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AN273

If the EP93xx device is configured for Sync boot mode as described above, the EP93xx device will force SDCS3

To avoid this situation, configure the EP93xx device to boot in the Async mode. Refer to the Appropriate EP93xx User's Guide for details about the memory map for Sync and Async modes. Refer to the ARM920T Core and Advanced High Speed Bus (AHB) chapters.

to be 16 bits wide. Software can not reprogram SDCS3 to be 32 bits wide.

Another way to avoid this situation is to use an SDRAM chip select other than SDCS3 mode.

, when in Sync Boot

5. Default Static Memory Wait State

When the EP93xx device is configured for internal boot mode, it first executes the on-chip boot ROM after reset. The boot ROM sets the Static Memory Controller (SMC) registers with a wait state value that may be suitable for faster Flash memory devices, such as the Intel Strata Flash, but this value may not be suitable for other slower Flash devices.

EP93xx users that plan to use slower Flash devices are advised to configure the EP93xx for external boot mode so that the boot ROM is bypassed. The hardware default wait state value for external boot mode is set to its maximum to accommodate slow Flash devices.

6. 2x SSP (Synchronous Serial Port) Clock – Revision E2 only

The hard-coded divide-by-2 block in the SSP (also called SPI™) clock input path was removed for Rev E2. This change increases the upper and lower operating range by a factor of 2. The maximum SPI clock rate of 3.6864 MHz is now increased by 2x to 7.3728MHz.

The deletion of the hard coded divide by 2 block will require those using SSP to adjust the SSPCPSR or the SSPCR0 register divider value if the external device can not accommodate the increased SSP clock rate automatically.

If a mixture of revisions are used, then the CHIP_ID register can be used to identify the silicon revision and adjust the SSP registers accordingly. The CHIP_ID register, bits 31:28, identifies the silicon revision. The silicon revision is decoded as follows:

0000 - Rev A 0001 - Rev B 0010 - Rev C 0011 - Rev D0 0100 - Rev D1 0101 - Rev E0 0110 - Rev E1 0111 - Rev E2

If SSP is not being used, or the external SPI device can automatically accommodate the 2x clock increase, then no software modifications are required.

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