Cirrus Logic AN269 User Manual
AN269
Using the EP93xx's Raster Engine
1. INTRODUCTION AND SCOPE
The purpose of this document is to he lp a u ser und er st and how to conn ect an LCD module to the EP93xx serie s of
embedded processors from Cirrus Logic. A wide variety of timings and output settings are available, which allows
connection to many color and black-and-white LCD displays. Some timing modes will also allow connection to an
external video DAC, which can be used to drive any type of display.
This application note is focused on th e typical usage of certain exampl e LCD screens. As such, the examples were
designed and tested at typical values to show how the LCD controller can be used. If plannin g to use the LCD controller outside these typical cases, the user should test and verify the application in the target environment. In addition, this document is not a replaceme nt for the information in the EP93xx User's Guide and the EP93xx Data
Sheet. It should be used in conjunction with these documents. It is highly recommended that the user read the
EP93xx User Guide chapter titled "Raster Engine With Analog/LCD Integrated Timing and Interface" before using
this Application Note.
Throughout this document, signals will be identified in diagrams and equations by their corresponding EP93xx signal
names, unless otherwise specified.
2. HOW TO DETERMINE IF AN LCD IS COMPATIBLE WITH THE EP93XX
The EP93xx raster engine is very versatile, and will work with a variety of LCD display types. In order to determine
if a display is compatible, follow these steps:
1. Check the appendices at the back of this manual to see if the display is listed as an example. If so, use the
specified register settings for that display. Otherwise, proceed to step 2.
2. Examine the waveforms in Figures 9, 14, and 20. If the desired displa y timings match any of these diagrams
(or vary only in signal polarity), Section 6, 6.2, or 6.3 will describe how to set up the EP93xx raster timing
registers. If the display does not match any of these, refer to “Other Types of Framed Data Displays” on
page 41 for more information. Note that the sig nals AC, XECL, and YSCL are not discus sed in these d ia-
grams, but are described in the “Video Timing” section of the Raster Engine chapter of the EP93xx User’s
Guide.
3. After determining that the sy nchronization signals can be generated by the EP93xx, the appropriate pixel
output mode should be chosen. “General Description of Pixel Output Modes” on page 9 describes this pro-
cess.
If the timing requirements or the pixel input format of the display are not supported, than the display may still be
supported using GPIO pins to generate the appropriate timings. However, this will consume much more processor
time, but may be a viable option for slower/smaller displays.
The versatility of the EP93xx raster engine attempts to cover the most common types of displays. Even though care
has been taken in the design of this block, please keep in mind that not all LCD panels can be supported.
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AUG '05
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3. GENERATION OF THE VIDEO CLOCK, VIDCLK
The internal video clock (VIDCLK), which drives the raster engine and the external pixel clock (SPCLK), is derived
from PLL1, PLL2, or the external clock input. The SPCLK signal clocks data fr om the EP9 3xx into the exter nal LCD
or display. The number of pixels per SPCLK may be 1, 2, 4, 8, or 2-2/3.
Conceptually, the external clock (SPCLK) is generated by di viding the VIDCLK by the appropriate clock divider. The
necessary divider depends on the output mode. For 1 pixel-per-SPCLK, there will be 1 VIDCLK-per-SPCLK. For 2
pixels-per-SPCLK, there will be 2 VIDCLKs-per-SPCLK (SPCLK runs at VIDCLK/2). For the case of 4 pixels-perSPCLK, there are 4 VIDCLKs-per-SPCLK. Note that 2-2/3 mode is a special case in which there are 3 VIDCLKs for
the first SPCLK, 2 for the second SPCLK, and 3 for the third SPCLK. This pattern then repeats every 8 pixels (and
therefore 8 VIDCLKs).
To derive VIDCLK, the clock source (PLL1, PLL2, or External Clock) is divided by a prescaler and then by a divideby-N block, where N
VDIV are all bit fields of the VidClk Div register, contained in the system controller. Please refer to the EP93xx User’s
Guide (“System Controller” section) for more information on the VidClkDiv register.
≥ 2. This is shown in the block diagram in Figure 1. The values of PSEL, ESEL, PDIV, and
Disable
÷ 2
External
Clock
PLL1
PLL2
Below is one algorithm for integer math operations (similar to the Linux 2.6 video display driver) for determining the
proper VidClkDiv settings for a desired VIDCLK rate. Essentially, the algorithm examines the frequency of the external clock source, PLL1, and PLL2, and then attempts differ ent combinations of the divider settings to find a setting
that generates the smallest error. The divider settings are a combination of PDIV (pre-divider) and VDIV (divide-by-
N). Since PDIV can be set to 2, 2.5, or 3, the algorithm uses twice that value (and therefore twice the value of the
PLL1, PLL2, etc.). Note that the accuracy of this algorithm may be improved through the use of floating-point math.
0
1
PSEL
0
÷ 2.5
1
÷ 3
ESEL
Figure 1. Video Clock Generation
00
01
10
11
PDIV
÷ N
VDIV
(≥ 2)
Video Clock
Output
(To Raster
Block)
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/* Desired SPCLK frequency is passed in as "freq" */
int ep93xx_set_video_div(unsigned long freq)
{
/* pdiv, div, psel and esel are the final values of the appropriate bit settings in the
VidClkDiv register. The current "guess" for pdiv and div are j-3 and k, respectively. */
unsigned long pdiv = 0, div = 0, psel = 0, esel = 0, err, f, i, j, k;
/* Algorithm may return -1 if no valid setting can be found */
err = -1;
/* Try the External Clock, PLL1 an d PLL2 */
for (i = 0; i < 3; i++) {
if (i == 0)
/* The External Clock, multiplied by 2 */
f = 14745600 * 2;
else if (i == 1)
/* PLL1 output frequency, multiplied by 2 */
f = ep93xx_get_pll_frequency(1) * 2;
else
/* PLL2 output frequency, multiplied by 2 */
f = ep93xx_get_pll_frequency(2) * 2;
/* Try each setting of PDIV, the pre-divider , and look for a VDIV
setting that would give us the desired frequency. Note that we are
using PDIV*2, since we multiplied the frequency by 2 above. */
for (j = 4; j <= 6; j++) {
k = f / (freq * j);
if (k < 2) {
/* VDIV must be at least 2 */
continue;
}
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/* Calculate how far off of the desired frequency this setting is,
and then set the values of PDIV and VDIV from j and k.
At this point, the clock source is set, also. */
if (abs(((f / (j * k))) - freq) < err) {
pdiv = j - 3;
div = k;
psel = (i == 2) ? 1 : 0;
esel = (i == 0) ? 0 : 1;
err = (f / (j * k)) - freq;
}
}
}
if (err == -1) {
/* We were unable to determine a setting that is appropriate */
return -1;
}
/* Unlock the registers */
outl(0xaa, SYSCON_SWLOCK);
/* Write the values to the registers */
outl(SYSCON_VIDDIV_VENA | (esel ? SYSCON_VIDDIV_ESEL : 0) |
(psel ? SYSCON_VIDDIV_PSEL : 0) |
(pdiv << SYSCON_VIDDIV_PDIV_SHIFT) |
(div << SYSCON_VIDDIV_VDIV_SHIFT), SYSCON_VIDDIV);
/* Return the actual value of what frequency we set */
return freq + err;
}
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4. USING THE HORIZONTAL AND VERTICAL COUNTER FOR TIMINGSIGNAL GENERATION
Conceptually, all timing synchronization outputs from the EP93xx are driven from a series of down counters followed
by combinational logic. The input clock to these counters is the video clock signal, VIDCLK (see “Generation of the
Video Clock, VIDCLK” on page 2). There are two banks of down counter/comparators - one for horizontal and one
for vertical timing generation. A block diagram of the horizontal and vertical timing generation is shown in Figure 2,
and brief descriptions of each of the corresponding timing registers are found in Table 1.
REGISTER DESCRIPTION
VLINESTOTAL
Vertical Lines Total
VSYNCSTRTSTOP
Vertical Sync Pulse Start/Stop
VACTIVESTRTSTOP
Vertical Active Start/Stop
VBLANKSTRTSTOP
Vertical Blank Start/Stop
VCLKSTRTSTOP
Vertical Clock Start/Stop
HLINESTOTAL
Horizontal Lines Total
HSYNCSTRTSTOP
Horizontal Sync Pulse Start/Stop
HACTIVESTRTSTOP
Horizontal Active Start/Sto p
HBLANKSTRTSTOP
Horizontal Blank Start/Stop
HCLKSTRTSTOP
Horizontal Clock Start/Stop
VIDEOATTRIBS
Video Signal Attributes
Table 1. Summary of Synchronization Registers
Total number of horizontal lines in a single video frame (Includ-
ing SYNC, BLANK & ACTIVE regions).
Vertical counter: Defines when the VCSYNC pulse becomes
active (Start) and goes inactive (Stop)
Vertical counter: Defines when the VACTIVE signal becomes
active (Start) and goes inactive (Stop). This internal signal is
OR’d with HACTIVE to define the active portion of the video
frame (when active pixel data is clocked out).
Vertical counter: Defines when the VBLANK signal becomes
active (Start) and becomes inactive (Stop) before and after the
active video portion of the video frame. BLANK is the AND of
HBLANK and VBLANK.
Vertical counter: Defines when the VCLKEN Signal goes active
(Start) and becomes inactive (Stop) at the beginning or end of
the video frame. SPCLK is only generated when the VCLKEN
and HCLKEN signals are BOTH active.
Total Number of VIDCLKs in a single horizontal line of video,
including both active and inactive regions.
Horizontal counter: Defines when the HSYNC pulse becomes
active (Start) and goes inactive (Stop).
Horizontal counter: Defines when the HACTIVE signal
becomes active (Start) and goes inactive (Stop). This signal is
OR’d with VACTIVE to define the active portion of the video
frame (when active pixel data is clocked out).
Horizontal counter: Defines when the HBLANK signal
becomes active (St art) and becomes inactive (Stop) before
and after the active video portion of the video frame. BLANK is
the AND of HBLANK and VBLANK.
Horizontal counter: Defines when the HCLKEN Signal goes
active (Start) and becomes inactive (Stop) at the beginning or
end of the video frame. SPCLK is only generated when the
VCLKEN and HCLKEN signals are BOTH active.
Synchronization Control, Polarity Selection, Output Enables,
etc.
The video clock (VIDCLK) decrem ent s the h orizon tal do wn counter at one count per video clock period. When the
count reaches 0, the counter loads the value contained in the HClkTotal register, and continues co unting down. The
HSYNC output is generated by comparing the value of the horizontal down counter with the HSyncStrtStop register.
If the value of the counter is in the active range (HSyncStrtStop.Start > Horizontal Counter > HSyncStrtStop.Stop),
the HSYNC output becomes active. Similarly, the HBlankStrtStop, HActiveStrtStop, and HClkStrtStop values are
compared with the horizontal down counter, and then control the BLANK Output, Pixel Output Enable, and Pixel
Clock Output Enable (once combined with the appropriate signals from the vertical timing block).
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When the output of the horizontal down counter rolls over, it will decrement the vertical down counter at one count
per horizontal line. When the count reaches 0, the vertical down counte r loads the value contained in the VLinesTo-
tal register, and continues counting down. The VCSYNC ou tput is ge ne rate d by compar ing the value of the ve rtical
down counter with the VSyncStrtStop register. If the value of the counter is in the active range (VSyncStrtStop.Start
> Vertical Counter > VSyncStrtStop.Stop), the VCSYNC output becom es active. Similarly the VBlankStrtStop, VAc-
tiveStrtStop, and VClkStrtStop values are compared with the vertical down counter, and then control the BLANK
Output, Pixel Output Enable, and Pixel Clock Output Enable (once combined with the appropriate signals from the
horizontal timing block).
4.1 Counter Offsets
Due to internal delays inside the raster timing block, various register settings must be offset to align data,
sync, and clock outputs properly at the output of the ep93xx. In the following sections, th ese delays are added at the last stage of computing the timings (when setting the actual register values).
These delays are listed in Table 2.
Registers Offset in SPClocks
HSYNCSTARTSTOP 0
HACTIVESTRTSTOP -1
HACTIVESTRTSTOP (2 2/3 pi xe l mod e) 0
HBLANKSTRTSTOP -1
HCLKSTRTSTOP -6
Ta ble 2. Offsets for Horizon tal and Vertical Counters
4.1.1 Horizontal and Vertical Offset Example
Given the following:
Screen Width = 16 Pixels
Screen Height = 1 Line
Screen Resolution = 16 bpp, 565.
Total Number of Horizontal Clocks = 20
Two Lines in the vertical direction
The Start of HSync signal,Blank and Vsync signal and start of data coming out must line up.
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Figure 2. Offset for HSync, HActive, VSync and HCLK
HSync and Blank must be raised high after the last byte of data is transferred.
Find the register values for HClksTotal, HSyncStart, HSyncStop, HActiveStrt, HActiveStop, HBlankStrt,
HBlankStop, HClkStrt and HClkStop. To create these timings you must perform the following calculations.
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The Calculations for HClksTotal are
HClksTotal = Number of Horizontal Clocks - 1
= 20 -1
= 19
The Calculations for HSyncStart are
HSyncStart = HClksTotal + Offset of Sync
= 19 + 0
= 19
TheCalculations for HSyncStop are
HSyncStop = HClksTotal - Screen Width + Offset of Sync
= 19 - 16 + 0
= 3
TheCalculations for HActiveStrt are
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HActiveStrt = HClksTotal + Offset of HActive
= 19 -1
= 18
The Calculations for HActiveStop are
HActiveStop = HClksTotal - Screen Width + Offset of HActive
= 19 - 16 -1
= 2
The Calculations for HBlankStrt are
HBlankStrt = HClksTotal + Offset of HActive
= 19 -1
= 18
The Calculations for HBlankStop are
HBlankStop = HClksTotal - Screen Width + Offset of HActive
= 19 - 16 -1
= 2
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The Calculations for HClkStrt are
HClkStrt = HClkstotal - Offset of HClk
= 19 - 6
= 13
The Calculations for HClkStop are
HClkStop = HClksTotal - Screen Width + Offset of HClk
= 19 - 16 - 6
= -3
Since -3 is not in the range of 0 and HClksTotal, add the number of Horizontal Clocks.
= -3 + Number of Horizontal Clocks
= -3 + 20
HClkStop = 17
The values for HSyncStart, HSyncStop, HActiveStrt, HActiveStop, HBlankStrt, HBlankStop, HClkStrt and
HClkStop are shown in Figure 2.
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5. GENERAL DESCRIPTION OF PIXEL OUTPUT MODES
Each display type specifies the number of bits (and therefore bits per color) clocked out per SPCLK period. The
EP93xx supports a variety of formats, as specified in the “Output Shift Mode Table” an d “Color Mode Definition Ta-
ble” in the PixelMode register (refer to the Raster Engine chapter in the EP93xx User’s Guide for these tables).
Certain restrictions apply to these settings (as certain m odes must be used together). These restrictions, along with
the appropriate pins, are located in the table entitled “Output Pixel Transfer Modes” (again refer to the EP93xx Ras-
ter Engine chapter).
To use the “Output Pixel Transfer Modes” table, locate the output mode that corresponds to the display that is being
used. For both monochrome and color displays, the bits with highest significance should be attached to the display.
For example, if the output mode offers bits 7, 6, and 5, but the display only allows a single bit for each color, then
bit 7 should be chosen from each color. For monochrome displays, consecutive pixels should be chosen from the
same color. This will ensure that the grayscale look-up tables function as expected, as each LUT performs operations on a single color.
Some of the more common output modes are listed in the following diagrams, detailing where the pixel outputs end
up on the display and which corresponding pins are used for each color. These diagrams are most helpful wh en
viewed in color. A brief description of the mode follows each diagram. The input to these diagrams would be the
most-significant bits from the color and/or grayscale LUTs and the pixel MUX. Again, for monochrome displays, a
single color output (Red, Green, or Blue) should be used to ensure proper output.
Note that these diagrams are only a graphical representation of the information from the “Output Pixel Transfer
Modes” table in the Raster Engine chapter in the EP93xx User’s Guid e. Unused or redu ndant output pins ar e those
specified with gray text and a black background.
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P ixel D ata B u s
Pins P[17:0]
Pixel 0 (First SPCLK)
Pixel Data Most Significant Bits
(from LUT and Blink Logic)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Pixel 1 (Second SPCLK)
0
0
0
1
1
1
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Figure 3. Single 16-bit 565 Pixel Per Clock Output
The output mode “Single 16-bit 565 Pixel Per Clock” is shown in Figure 3. In this mode, each SPCLK will clock out
a single pixel, with 5 bits representing the Blue component on P[5:1], the Red component on P[17:13], and 6 bits
representing the Green component on P[11:6].
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Pixel Data Bus
Pins P[17:0]
Pixel 0 (First SPCLK)
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Pixel 1 (Second SPCLK)
Pixel Data Most Significant Bits
(from LUT and Blink Logic)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
1
0
1
Figure 4. Single 16-bit 555 Pixel Per Clock Output
The output mode “Single 16-bit 555 Pixel Per Clock” is shown in Figure 4. In this mode, each SPCLK will clock out
a single pixel, with 5 bits representing the Blue component on P[5:1], Green component on P[11:7], and Red component of the pixel on P[17:13].
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(from LUT and Blink Logic)
Pixel Data Most Significant Bits
Pixel Data Bus
Pins P[17:0]
17
16
Pixels 0, 1, and 2 (First SPCLK)
15
14
13
12
11
10
9
8
7
2
6
2
5
1
4
1
3
1
2
0
1
0
0
0
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Figure 5. 3 Bit Per Pixel Formatted as 2-2/3 Bits, First SPCLK
The output mode “2-2/3 Pixels Per Cloc k” is shown in Figures 5, 6, and 7. Since this mode is rather complex, one
diagram shows data during each of the first, second, and third SPCLK outputs. In this mode, each SPCLK will clock
out 2-2/3 pixels, with 1 bit representing the Red, Green, and Blue components of the pixel.
In the first SPCLK, pixel 0’s Red, Green, and Blue comp onents are clocked o ut of P[2:0]. Pixel 1’s Red , Green, and
Blue components are clocked out of P[5:3]. Note that ONLY the Blue and Green component of Pixel 2 are clocked
out of P[7:6]. The Red component of pixel 2 will be clocked out during the second SPCLK.
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Pixel Data Bus
Pins P[17:0]
1
Pixel Data Most Significant Bits
(from LUT and Blink Logic)
1
7
1
6
1
5
Pixels 2, 3, 4 and 5 (Second SPCLK)
1
4
1
3
1
2
1
1
0
9
8
5
7
4
6
5
4
4
4
3
3
2
3
1
3
0
2
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Figure 6. 3-Bit Per Pixel Formatted as 2 2/3 Bits, Second SPCLK
In the second SPCLK for 2-2/3 mode, pixel 2’s Red component will be clocked out of P[0]. All of the Red, Green,
and Blue components of pixel 3 are clocked out of P[3:1]. Pixel 4’s Red, Green, and Blue components are clocked
out of P[6:4]. Note that ONLY the Blue component of Pixel 5 is clocked out of P[7]. The Green and Red components
of pixel 5 will be clocked out during the third SPCLK.
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Pixel Data Bus
Pins P[17:0]
17
16
15
Pixel Data Most Significant Bits
(from LUT and Blink Logic)
14
13
12
Pixels 5, 6 and 7 (Third SPCLK)
11
10
9
8
7
7
6
7
5
7
4
6
3
6
2
6
1
5
0
5
Figure 7. 3-Bits Per Pixel Formatted as 2-2/3 Bits, Third SPCLK
In the third SPCLK for 2 2/3 mode, pixel 5’s Green and Red comp onents will be clocked out of P[1:0 ]. All of the Red,
Green, and Blue components of pixel 6 are clocked out of P[4:2]. Pixel 7’s Red, Green, and Blue components are
clocked out of P[7:5]. On successive SPCLK periods, the pattern of pixels will repeat.
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Pixel Data Bus
Pins P[17:0]
Pixels 0, 1, 2 and 3
17
16
Pixel Data Most Significant Bits
(from LUT and Blink Logic)
15
14
13
12
11
10
3
3
3
3
2
2
9
2
8
2
7
1
6
1
5
1
4
1
3
0
2
0
1
0
0
0
Figure 8. 4 Pixels Per Shift Clock
In “4 Pixels-Per-Shift-Clock mode“, shown in Figure 8, only 1 bit (the MSB) will be available for the Blue and Green
components of the pixel. The Red component will have the two MSBs available. In this mode, there are 4 pixels
clocked during each SPCLK. As can be seen from the diagram, pixel 0 is outp ut on P[3:0], pixel 1 is output on P[7:4],
pixel 2 is output on P[11:8], and pixel 3 is output on P[15:12]. Note that the diagram does not show bit 6 (the secondmost-significant bit) for the Red component connected to the display, as most displays will only be using 1 bit for
each color in this mode.
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6. SETTING UP DISPLAY TIMING
6.1 HSYNC/VSYNC-Style Displays
In displays using a HSYNC/VSYNC-style timing interface, the following control signals are commonly used
for data synchronization:
– DCLK - Data Input Clock. Usually one rising/falling edge occurs per pixel or set of pixel data. This is
the highest frequency interface signal, and transitions occur many times during each horizontal line.
– DE - Data Enable or Valid. Used to indicate valid data is currently being clocked into the display.
This may be referred to as a blanking signal, and will become active one time per valid line.
– VSYNC - Vertical Synchronization Signal. Indicates the beginning of a full frame of data. This signal
becomes active one time during one frame if in progressive mode, or two times per frame in
interlaced mode.
– HSYNC - Horizontal Synchronization Signal. Indicates the beginning of the next horizontal line. This
signal becomes active one time during the line, and many times per frame.
These signals should be connected to the EP93xx with the signal mapping shown in Table 3. Note that level
buffers may be required to meet the electrical specifications of the display.
Display Pin EP93xx Pin
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DCLK SPCLK
DE BLANK
VSYNC VCSYNC
HSYNC HSYNC
Table 3. HSYNC/VSYNC Pin Mapping
An example set of timings for an HSYNC/VSYNC-style display is shown in Figure 9. The signal names used
are those of the corresponding EP93xx pins.
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HSYNC
BLANK
SPCLK
DATA
t
HSYNC
Single Horizontal Line
Active Video
t
DCLK
t
HACTIVE
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VCSYNC
HSYNC
BLANK
Back Porch Interval t
HBACKPORCH
t
Single Video Frame
VSYNC
Front Porch Interval t
Active Video
HFRONTPORCH
t
VACTIVE
Back Porch Interval t
VBACKPORCH
Front Porch Interval t
VFRONTPORCH
Figure 9. Example Timings for an HSYNC/VSYNC-Style Display
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6.1.1 Pixel Data Clock Rate and HClkTotal/VLinesTotal
The pixel clock rate VIDCLK can be determined from the total number of VIDCLK periods per line, total
number of horizontal lines, and the Refresh Rate .
The timing specifications for this type of display interface will usually list an HSYNC Width, Horizontal
Back Porch Width, Horizontal Front Porch Width, Horizontal Valid, Horizontal B lank length, VCSYNC
Width, VCSYNC frequency, Vertical Back Porch Width, Vertical Front Porch Width, Vertical Valid, and
Vertical Blank lengths.
A typical horizontal line for this type of display can be found in Figure 10. This line can be divided into
regions, which are in units of VIDCLK. The total number of VIDCLK periods per line is the sum of the Horizontal Valid (tHACTIVE) region, the Horizontal Front Porch region (tHFRONTPORCH), the HSYNC region (tHSYNC), and the Horizontal Back Porch region (tHBACKPORCH). The equation for this is shown
here, where tHORIZ represents the number of VIDCLK periods per horizontal line (all values are in VIDCLK periods):
tHORIZ = tHACTIVE + tHFRONTPORCH + tHSYNC + tHBACKPORCH
Note that there may be 1, 2, 4, 8, or 2-2/3 pixels per SPCLK. This will mean that tHACTIVE is not necessarily the number of horizontal pixels on the screen. Con sult the datasheet o f the display to dete rmine the
number of pixels per SPCLK per horizontal line. “Genera tion of the Vide o Clock, VIDCLK” o n page 2 has
examples of the number of pixels per SPCLK (VIDCLKs/pixel is usually 1).
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A typical full video frame for this type of display can be found in Figure 12. The time spent on a single
frame is the sum of the Vertical Valid (tVACTIVE) region, the Vertical Front Porch Width (tVFRONTPORCH), the VCSYNC Width (tVSYNC), and the Vertical Back Porch Width (tVBACKPORCH). The
equation for this is shown here, where tVERT represen ts the amount of time spent per single video frame
(all time is in horizontal line periods):
tVERT = tVACTIVE + tVFRONTPORCH + tVSYNC + tVBACKPORCH
Next, the specification for the refresh ra te sho uld b e dete rmined from the da tash eet. This may b e spec ified as VCSYNC or VSYNC frequency. We will call this value fVSYNC.
Now the VIDCLK rate can be determined as a product of the above 3 values. This is shown below, where
VIDCLK refers to the VIDCLK rate (Hz):
VIDCLK = tHORIZ * tVERT * fVSYNC
To generate the proper frequency for VIDCLK, either PLL1, PLL2, or an external clock must be used. Any
of these sources may be divided down using the settings in the VidClkDiv (Video Clock Divider) register.
A simple block diagram of this divide structure and a method for determining the proper settings of
VidClkDiv can be found in “Generation of the Video Clock, VIDCLK” on page 2.
Once the VIDCLK rate has been determined, the horizontal and vertical alignment signals ca n be derived.
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6.1.2 Horizontal Alignment Signals
Timings for a single horizontal line can be seen in Figure 10. To determine when these signals become
active, the horizontal frame timing registers HClkTotal, HSyncStrtStop, HActiveStrtStop, HBlankStrtStop
and HClkStrtStop must be set.
t
HSYNC
HSYNC
BLANK
SPCLK
DATA
Single Horizontal Line
Active Video
t
DCLK
t
HACTIVE
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Back Porch Interval t
HBACKPORCH
Front Porch Interval t
HFRONTPORCH
Figure 10. Typical Horizontal Line for HSYNC/VSYNC Display
“Using the Horizontal and Vertical Counter for Timing-Signal Generation” on page 4 for a description o f
the horizontal timing registers.
Recall that the timing specifications for this type of display interface will list an HSYNC Width, Horizontal
Back Porch Width, Horizontal Front Porch Width, Horizontal Valid, and Horizontal Blank lengths.
The HClkTotal register will hold the total length of a single line measured in VIDCLK periods.The equation
for this is shown here:
HClkTotal = tHORIZ – 1
Note that 1 is subtracted for the total as this is a 0-based counte r implementation. Also, remember all measurements are assumed to be in periods of VIDCLK. All other signals are determined using this as a time
base.
To determine when the HSYNC, SPCLK (via HCLKEN), and BLANK (via HBLANK) signals should become active during a horizontal line, it is easiest to draw them out as shown in Figure 11. This diagram
shows the line counter along the bottom , starting at HClkTotal and cou nting down to 0. Each line start s
with the counter set to HClkTotal. It then decrements by 1 for each VIDCLK clock period, regardless of
whether SPCLK is present or not. When the counter reaches 0, it is reset to HClkTotal.
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Single Horizontal Line
Active Video
t
HSYNC
HSYNC
t
HACTIVE
BLANK
t
DCLK
SPCLK
DATA
HSyncStop
HSyncStart
Horizontal Line
Counter Value
Count = HClkTotal Count = 0
Count = HClkTotal - 1
Count = HClkTotal - 2
HSyncStop
HBlankStart
HActiveStart
HBlankStop
HActiveStop
AN269
Back Porch Interval t
HBACKPORCH
Front Porch Interval t
HFRONTPORCH
Figure 11. Horizontal Line for HSYNC/VSYNC Display with Register Timings
Next we will determine the appropriate time for the HSYNC signal to become active. As can be seen from
the diagram, it should become active during the tHSYNC region, when the line counter is set to HClkTotal
(the beginning of the horizontal line). HSYNC becomes inactive after a period of time tHSYNC has
elapsed. Therefore, the HSYNC signa l should become inactive after the tHSYNC region, when the line
counter is HClkTotal-tHSYNC. This is shown using the equations below, where HSyncStart is the point at
which HSYNC becomes active and HSyncStop is the point at which HSYNC becomes inactive:
HSyncStart = HClkTotal
HSyncStop = HClkTotal – tHSYNC
The active data/blank signal HBLANK becomes inactive when valid data starts, and active once the vali d
data stops. In other words, the HBLANK signal should be active for all regions except the active region
(tACTIVE). Therefore, when the h orizontal line counter reaches the end of the ba ck porch interval, it
should become inactive. At the beginning of the front porch interval, it should become active again. The
following equations show this, using HBlankStart as the position at which this signal becomes active, and
HBlankStop as the position at which this signal becomes inactive (note that HBlankStop is 1 less than the
front porch, as this is a 0-based counter implementation):
HBlankStart = HClkTotal - tHSYNC - tHBACKPORCH -1
HBlankStop = tHFRONTPORCH - 1
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