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How to Connect NAND Flash Memory to an EP93xx
1. Introduction
This document describes two different methods that can be used to connect NAND FLASH to an EP93xx
device. The first approach takes advantage of the data bus and uses fewer GPIO pins. The second appraoch uses GPIO exclusively.
2. Implementation Using GPIO Interrupt (for EP93xx)
Please refer to the partial schematic below. GPIOx, GPIOy, and GPIOz may be any GPIO pins from the
EP93xx device. Not all of the devices in the EP93xx family have all of their GPIO port pins bonded out.
Refer to the datasheet for the specific device you are using. It is suggested that all the GPIO pins connected to the NAND device belong to the same port for efficient code. However, this is not a requirement.
There is no GPIO signal connected to pin 7 of the NAND device in the figure below. It is not required because the ready status can be read from a bit in the Status register. If the design uses pin 7, make sure
that the GPIO line used has interrupt capability. Referring to the EP93xx User's Guide, GPIO section, you
will notice Ports A, B, and F have interrupt capability. Note that Port A and B have interrupt capability but
it is implemented as a single interrupt signal called GPIOINTR. All pins on Port F are availab le to the system interrupt controller as GPIO[7:0]INTR.
The example below connects an EP93xx to the SAMSUNG K9F2G08U0M.
/CSx
/WE
/RE
http://www.cirrus.com
PWR_3V3
U2
38
1
2
1
2
3
3
/NAND_WE
/NAND_RE
GPIOz
GPIOy D0
GPIOx
19
18
8
17
16
9
12
37
K9F2G08
Figure 1. Example of Implementation Using Minimal GPIO
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
PRE
WP
WE
RE
ALE
CLE
CE
PWR_3V3
PWR_3V3
D7
D6
D5
D4
D3
D2
D1
D0
R/B
GND
GND
44
43
42
41
32
31
30
29
7
13
36
D7
D6
D5
D4
D3
D2
D1
FEB ‘05
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3. Implementation Using GPIO (for EP931x)
Alternatively, the general purpose I/O (GPIO) pins can be used to provide an easy way to control an external NAND flash memory device. EP93xx GPIO signals provide great flexibility in meeting the NAND
device timing requirements. However, this may not be the most efficient way to connect an EP931x to a
NAND flash memory device because it requires the use of many of the available GPIO pins.
The example below connects an EP931x to the SAMSUNG K9F2G08U0M. See “Read Flash ID” Sample
Code on page 3 for a code example for this particular approach.
EP931x
GPIO Port C[0]
GPIO Port C[7]
GPIO Port B[1]
GPIO Port B[2]
GPIO Port B[3]
GPIO Port B[4]
GPIO Port B[5]
GPIO Port B[6]
…
Figure 2. Example of Implementation Using GPIO Ports B and C
I/O0
…
I/O7
WE
RE
ALE
CLE
R/B
CE
K9F2G08U0M
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3.1 “Read Flash ID” Sample Code
ULONG ulMakerCode;
ULONG ulDeviceCode;
ULONG ulIDData;
*GPIO_PBDDR = 0x5E;
//
// Write Read ID Command
//
*GPIO_PBDR = 0x14;
*GPIO_PCDR = 0x90;
*GPIO_PCDDR = 0xFF;
*GPIO_PBDR = 0x06;
//
// Write Reading ID Address
//
*GPIO_PBDR = 0x0C;
*GPIO_PCDR = 0x00;
*GPIO_PCDDR = 0xFF;
*GPIO_PBDR = 0x06;
//
// Prepare to Read Data from IO
//
*GPIO_PCDDR = 0x00;
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//
// Read Maker Code
//
*GPIO_PBDR = 0x02;
ulMakerCode = *GPIO_PCDR;
*GPIO_PBDR = 0x06;
//
// Read Device Code
//
*GPIO_PBDR = 0x02;
ulDeviceCode = *GPIO_PCDR;
*GPIO_PBDR = 0x06;
//
// Don't care this byte
//
*GPIO_PBDR = 0x02;
ulIDData = *GPIO_PCDR;
*GPIO_PBDR = 0x06;
//
// Read Page Size, Block Size, Spare Size, Organization
//
*GPIO_PBDR = 0x02;
ulIDData = *GPIO_PCDR;
*GPIO_PBDR = 0x06;
// Disable NAND Flash
*GPIO_PBDR = DISABLE_CHIP;
printf("Maker Code = 0x%X\r\n",ulMakerCode);
printf("Device Code = 0x%X\r\n",ulDeviceCode);
printf("IDData = 0x%X\r\n",ulIDData);
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Table 1. Revision History
Release Date Changes
REV1 Febuary 2005 Initial Release
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com
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